CSC 480/580 -- Computer Organization Tues

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CSC/MTH 231 Discrete Structures II
Spring, 2010
Name ________________________________
Applied Math Lab 1
Boolean Algebra and Combinational Circuits
Tasks 1-3 are due Tuesday, May 11
Task 4 is due Thursday, May 13
(40 points)
Purpose: -----
To
To
To
To
gain familiarity with the LD2 Logic Trainer
learn to read pin diagrams
investigate the behavior of several basic gates
design and implement a combinational circuit
Equipment: LD2 Logic Trainer, power supply, and 22 gauge solid wire
ICs -- one 7408 quad 2-in AND
one 7432 quad 2-in OR
one 7486 quad 2-in XOR
two 7400 quad 2-in NAND
one 7402 quad 2-in NOR
one 7420 dual 4-in NAND
Task: I. Investigate AND gate behavior by doing the following:
1. Place the 7408 chip on the board and wire it to power and ground.
2. Select one of its 4 gates and wire the inputs to LD2 switches and the
output to a LED.
3. Try all 4 switch positions and observe the results. Write down the truth
table of expected vs. observed results.
4. Once you have verified that it works correctly, make sure ALL of the LEDs
on your kit work by putting both input switches in the UP (i.e. ON)
position and connecting the output wire, in turn, to each of the LEDs.
5. Next make sure all of your input switches work by connecting your two
input wires, in turn, to each pair of input switches.
6. Repeat steps 1-3 above for the 2-input OR, NAND, NOR, and XOR gates.
7. Repeat steps 1-3 above for the
inputs. Then make it work like
using only two of the gate's 4
must be input to its other two
7408 AND
Expected
4-input NAND gate. First test it with 4
a 2-input NAND gate. Since you will now be
inputs for data values, figure out what
input pins to make the gate work correctly.
7432 OR
Observed
7486 XOR
Expected
Observed
x
y || x  y || x  y
x
y || x + y || x + y
0
0 ||
||
0
0 ||
||
0
1 ||
||
0
1 ||
||
1
0 ||
||
1
0 ||
||
1
1 ||
||
1
1 ||
||
7400 NAND
Expected
7402 NOR
Observed
Expected
Observed
x
y ||(x  y)’||(x  y)’
x
y ||(x + y)’||(x + y)’
0
0 ||
||
0
0 ||
||
0
1 ||
||
0
1 ||
||
1
0 ||
||
1
0 ||
||
1
1 ||
||
1
1 ||
||
Expected
Observed
x
y || x○
+ y || x○
+ y
0
0 ||
||
0
1 ||
||
1
0 ||
||
1
1 ||
||
Task 2. Figure out how to create the logical equivalent of each of the gates
listed below using only the indicated chips. For each of the six
requested circuits, wire the circuit and test the output. You do not
have to make a truth table, but do make sure in each case that your
observed results match the expected results for all input switch
combinations. Then draw a logic diagram showing how you implemented the
circuit.
CREATE THE LOGICAL
EQUIVALENT OF
USING
A. 4-input AND gate
one 7408
B. 4-input OR gate
one 7432
C. 3-input NAND gate
one 7400
D. 3-input NOR gate
one 7402
E. an equivalence gate
one 7486
F. an equivalence gate
two 7400s
Task 3. Create a 3-input majority circuit. This is a circuit with three inputs
whose output is equal to the majority of the inputs. If two or more
inputs are zeroes, the output should be a zero. If two or more inputs
are ones, the output should be a one. This circuit is to be implemented
with one 7400 IC and one 7420 IC.
Design the circuit by writing down the following on the bottom of this page.
Use the back of the page if you need more space.
 The truth table for the function the circuit will implement
 A minimal SOP expression for the function
 A neatly drawn and well labeled logic diagram for implementing the
function using AND and OR gates
 Conversion of this into a neatly drawn and well labeled logic diagram for
implementing the function using only 2-input and 4-input NAND gates
 A wiring diagram showing how you will implement the circuit using one 7400
quad 2-input NAND and one 7420 dual 4-input NAND
Once you have done this, wire the circuit as neatly as possible. Be sure to
test it. If it does not work correctly for all possible input combinations,
find the bug, fix it, and retest until everything works correctly. You will
turn in all the design materials listed in the bullets above as well as
demonstrate the final working circuit for the instructor.
Due Thursday, May 13
Task 4. Implement and add to your logic trainer board the working circuit
for the prison security system problem we began in class together. Be ready
to demonstrate the final working circuit for the class and the instructor.
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