National College of Computer Studies (NCCS)
Final Examination (2010)
Set: A
BIM/First Semester/ ITC 212: Digital Logic
Full Marks: 40
Time: 2 Hour
Candidates are required to give their answer in their own words as far as practicable.
Group A
Brief answer questions:
1. Convert 1A3H to decimal
[101=10]
2. What happens in JK flip flop if both inputs are 1?
3. What is an ASCII code?
4. In a DMUX with 3 select lines the number of input is ________
5. If you want to design a counter with 17 states then what is the minimum number of flip-flops required?
6. What is the number of comparators required in a 3 bit flash ADC?
7. ROM is not random access. Is this statement true?
8. Differentiate between TTL and I2L.
9. How many clock pulses are required to load a 4 bit serial register with the data 1011?
10. How many full adders and half adders are required to add two 4 bits words.
Group ‘B’
Short Answer Questions:
11. Given A= 89 and B= 76 in to binary and perform the following operations:
[5x4=20]
a. A - B (Using 2’s complement)
b. A + B
12. How can you make S-R latch using NOR gate? Explain with necessary diagrams and tables?
13. Design a logic circuit with inputs A, B, C whose output X is HIGH only when a majority of input is
high.
14. What do you mean by digital displays? Differentiate LED and LCD. Design a digital clock.
15. What is a shift register? Draw a shift register that can be used for serial data input and serial data output
Group ‘C’
Long answer Questions:
[2x5=10]
16. Draw simplified logic circuit by using K- map:F(A,B,C,D) = ∑ m (0,2,5,7,8,9,10,11,13,15)
a. By using AND – OR Gate
b. By using NAND gate.
Use NOT gate wherever necessary.
17. a. Design a state diagram and state table of a sequential machine which counts upwards when y =0 and
downwards when y = 1. The sequence is given as 00. Also draw the logic circuit of the machine
b. Draw the circuit diagram of seven segment display.
National College of Computer Studies (NCCS)
Final Examination (2010)
Set: B
BIM/First Semester/ ITC 212: Digital Logic
Full Marks: 40
Time: 2 Hour
Candidates are required to give their answer in their own words as far as practicable.
Group A
Brief answer questions:
1. Convert 1CA1H to octal
[101=10]
2. Define Propagation delay time.
3. Which condition is illegal in S- R flip flop constructed with cross coupled NAND gate?
4. What is the role of the clock input in edge triggered flip-flops?
5. What is the maximum number of states that you can attain by using a 3 bit counter?
6. SRAM is faster then DRAM? Is it true?
7. Write down the truth table for a full adder.
8. A multiplexer has 32 input lines, how many select lines and o/p lines are required?
9. A memory device has 4000 bits. Each memory location is arranged in a group of 16 bits each. How
many address lines are required to address (decode) each memory location distinctly.
10. A 5 bit word has to be stored using a register. At least how many flip flops are required for this?
Group ‘B’
Short Answer Questions:
11. Given A= 79 and B= 85 in to binary and perform the following operations:
a.
A - B (Using 2’s complement)
b.
A+B
[5x4=20]
12.
How can you make S-R latch using NAND gate? Explain with necessary diagrams and tables?
13.
Design a logic circuit with inputs P,Q,R so that output S is HIGH whenever P is 0 or whenever Q=R=1.
14.
What is memory? How are data stored in a RAM cell? Explain with necessary diagram.
15.
Design a circuit which can add and subtract two 4 bit words.
Group ‘C’
Long answer Questions:
[2x5=10]
16. a. Design a MOD-50 Counters.
b. Design the circuit diagram of digital clock.
17. a. Design a state diagram and state table of a sequential machine which counts upwards when x =0 and
downwards when x = 1. The sequence is given as 001. Also draw the logic circuit of the machine.
b. Design a 4 bit SISO register with the data 1101. Assume all the flip flops are in cleared state. show how data transferred
serially?