Exam:
EECS 373 Midterm
Winter 2009, Prof. Mark Brehob
Name: ____________________________________
uname: _____________
Sign the honor code:
I have neither given nor received aid on this exam nor observed anyone else doing so.
___________________________________
Scores:
Problem # Points
1
/20
2
/15
3
/15
4
/10
Design 1
/20
Design 2
/20
Total
/100
NOTES:
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Open ABI/white book. If you don’t have your white book with you please contact the
proctor – you will need it!
Don’t spend too much time on any one problem.
You have 80 minutes for the exam.
The exam is 10 pages long.
1) Fill-in-the-blank or circle the best answer. [20 points, -2 per wrong or blank answer]
a) When building a 1024 by 4 bit memory device out of a square memory array, the row
decoder will need 2/4/6/8/12 of the address, while the column MUX will need
2/4/6/8/12 bits of the address.
b) Consider pages 13-17 to 13-24 of the white book. For a burst transaction on the
PowerPC823 bus, the target / the initiator / both target and initiator can stall individual
“beats” of the transaction.
c) A 10MHz clock with a duty cycle of 25% is high for _______________ ns at a time.
d) An ABI-compliant leaf function should be sure to restore all Volatile Registers /
Non-Volatile Registers / Registers that it uses. An ISR should be sure to restore all
Volatile Registers / Non-Volatile Registers / Registers that it uses.
e) If the top 2 bytes of SIPEND were 0x7474 and the top 2 bytes of SIMASK were
0x8F8F then the value of the top byte in SIVEC would be ___________. (in decimal).
f) SPI is most commonly used to connect one / two / many master device(s) to
one / two / many slave devices.
g) You would in general expect that CAN / SPI / Ethernet would have the highest
bandwidth.
h) Differential signaling over a twisted pair of wires is used in a number of modern busses
to reduce the impact of external noise / make it easier to not have a shared clock /
implement Manchester encoding / increase the speed of the data lines.
i) The largest (closest to infinity) value that can be used as an immediate in an addi
instruction is ____________________ (in decimal).
j) A page fault is a synchronous / asynchronous / external interrupt.
2/10
2) The designers at BobTom Design Inc. have discovered that their FPGA tools don’t have
support for a flip-flop with an enable. As such, they’ve chosen to use “clock gating” of the
clock by “ANDing” the clock with the enable signal (E) as shown below. [15]
A
B
E
C
D
Q
Out
Clock
They’ve hired you to figure out if this might cause a problem for them in their current design.
In their design the following is always true:
 C is a clock with a 50% duty cycle.
 A, B and E are combinational outputs and could glich but settle out significantly
before the rising edge of C.
 For their design the clock period is much longer than combinational logic delays or
clock-to-Q or set-up time.
a) What is the main problem would you expect to see with the above circuit? Draw a timing
diagram that illustrates that problem. [7]
b) Draw a circuit which does manages the enable in a reliable way for the circuit above.
Your solution may only involve the flip-flop shown above (with no other inputs or
outputs), AND gates, OR gates and NOT gates. [8]
3/10
3) PowerPC assembly [15]
a) Write PowerPC assembly code that sets bits 14, 15, and 16 of register R1 to “1s” without
changing any other bits in that register. You may use no more than 5 assembly
instructions. [7]
b) Consider the following code. Assume that r3=0xAABBCCDD, r1=0x1000 and all other
registers and memory locations are initialized to zero.
sthu r3, 2(r1)
oris r3, r3, (0x00FFFF00)@h
stwu r3, -3(r1)
lwz r4, -1(r1)
lhau r5, 3(r1)
What are the values of these registers? You must write your answers as 8-digit hex
numbers! [8, 2 each]
R1=_____________________
R3=_____________________
R4=_____________________
R5=_____________________
4/10
4) Say we execute the instruction lwz r2, 2(r3) where r2=0xAABBCCDD, r3=0x1000 and
memory is as follows:
Address 0x1000 0x1001 0x1002 0x1003 0x1004 0x1005 0x1006 0x1007
0x12
0x34
0x56
0x78
0x9A
0xAB
0xCD
0xF0
DATA
Draw a timing diagram which clearly shows the values of #TS, #TA, TSIZE, ADS and
DATA. Assume the transaction happens as quickly as possible and provide all numbers in
hexadecimal. [10]
Clock
#TA
#TS
TSIZE
ADS
DATA
5/10
Design problem – 20 character LCD [40 points]
It’s the summer, birds are singing, warm breezes are blowing and life is easy. You have taken a
summer position to help investigate new devices for the 373 lab. In particular, we wish to test a
20 character LCD display. The display works by sending it the character code to be displayed
and the display location along its 20 character line.
The display interface consists of two, 8-bit registers built into the display. The registers work
identically to the 8-bit D flip-flops we used in lab 3 to hold the LED display values. The registers
load data on the rising edge of a clock signal and the clock is gated with a special enable (CE)
signal. One register will hold an 8 bit value that will indicate where the character is to be
displayed on the display line and another register will hold the character code to be displayed.
LCD Display
8 Bit Data Path
CE_LOC
8-Bit Location
Register
CLK
8 Bit Data Path
CE_CHAR
8-Bit Character
Register
CLK
6/10
Part 1: The Bus Interface [20 points]
Design the bus controller for these registers that will generate the CE_LOC, CE_CHAR,
TA_LOC and TA_CHAR values. You may use schematic, Verilog form or a combination of
both. Assume standard schematic symbols. The Verilog does not have to syntactically perfect,
but must be logically correct.
Assume the following when designing your controller:
 The registers must be byte addressable.
 The location register’s data path is mapped to D24-31 of the processors data bus.
 The character register’s data path is mapped to D16-23 of the processors data bus.
 Register CLK is mapped to the external bus clock.
 The registers will work with zero wait state timing and you must design for zero wait
state timing.
 You may choose any address between 0x2000000 and 0x3000000 to select the registers.
 A6-11, A24-31, TS*, Bus_Clk, RD/WR*, TSIZ(0:1) are inputs.
 CE_LOC, CE_CHAR, TA_LOC and TA_CHAR are outputs.
(the page after this one is left blank to give you additional room to answer this
question)
7/10
This page left blank to provide additional room to answer the question on the previous page.
8/10
Part 2: The Device Driver [20 points]
You are to write an ABI compliant device driver in PowerPC assembly for the display. The
driver should accept 2 arguments: the location byte and the character byte. The character byte
will be coded as an ASCII character. Your function is to have the following prototype:
int wr_lcd (unsigned byte character, unsigned byte location)
The function is to return a 0 if the write was successful or a -1 if it was not.
Caveat:
It turns out that the LCD uses a custom character code set which is not compatible with
ASCII set. You must call a C function called asc2lcd that will convert the ASCII
codes to the LCD character codes.
You DO NOT have to write the C function asc2lcd, you will just be using it.
Assume the C function returns the LCD code as an unsigned integer. If the function
cannot convert the code it will return 0. The function prototype for asc2lcd is:
unsigned int asc2lcd (unsigned int character)
The driver should write the display and return a 0 if there was not an error and not write
the display and return a -1 if there was an error.
Clarity, providing comments or high level description will improve your chances for partial
credit. The page after this one is left blank to give you additional room to answer the question
should you need it.
9/10
This page left blank to provide additional room to answer the question on the previous page.
10/10