Lab #10
Introduction to State Machines
Fall 2007

A Brief Review
A synchronous circuit is a circuit controlled by a clock. The states are timed by the clock such that all flip-flop state changes occur only when the clock pulse changes state. An element that changes state when the clock changes from “0” to “1” is called a positiveedge triggered device. An element that changes state when the clock changes from “1” to
“0” is called a negative edge triggered device. The important thing to remember is that regardless of whether the element changes state on a positive edge or on a negative edge is that the states can only change at a clock transition in an edge-triggered sequential circuit.
An asynchronous circuit is a circuit that is not controlled by a clock. An element changes states when its inputs change states. You can think of the transitions that occur in an asynchronous circuit as a series of dominos. A domino is knocked down (state changes) when the previous domino (input) changes state (is knocked down). Although the analogy is not perfect, you can see the difference between a synchronous circuit and an asynchronous circuit.
In this lab we will only deal with synchronous (or clocked circuits). A sequential circuit can be modeled by a set of inputs, a block of combinational logic, a set of outputs and a block of memory as shown below. http://ranger.uta.edu/~carroll/cse2341/fall98/chapter8/sld002.htm

The important thing to note is that in a sequential circuit, the inputs can provided by the user (x
1
,…,x n
) and by the present state of the memory (y
1
,…,y n
).
Introduction to State Machines
Although you may not be aware of this yet, you were exposed to state machines when you designed a direction controllable modulo-8 counter in the previous two labs. A state machine is simply a machine whose operation is controlled partially or fully by the present state of the outputs.
There are two basic models for describing state machines. The first is the Mealy model.
In this model, the output is a function of the input and the present state. This model is often referred to as a “transition-assigned circuit” because the output of the circuit is associated with the transitions of the circuit (the arrows between the states).
Mealy Model
Assume that initially the circuit is in state A. If an input x=0 is applied, the next state will be B and the output z=1. Instead if an input x=1 is applied, the next state will be C and the output will be z=0. By continuing this logic, a state table describing the operation of the circuit can be derived.
So, if the initial state is A and if the input sequence x=011010 is applied to the circuit, then the output sequence will be z=110000.

The second model is the Moore model. In this model, the output depends only on the present state.
Moore Model
Assume initially that the circuit is in state W. Whenever the circuit is in state W, the output is “0”. This can be seen by examining the caption in each of the circuits of the state diagram above. The format for the caption is “state”/ “output”. If the input is x=1, then the next state will be X and the output will be “1”. Instead, if the input is x=0, then the next state will be Y and the output will still be “0”. By continuing this logic, a state table can be derived.

Experiment 1
Task 1
Answer the following questions. Make sure you include them in your lab report.
1) What model does the state diagram use?
2) If the circuit is originally at state 11 and the input is 010010, what will the output sequence be? The final state?
3) Finish the following timing diagram (State and Output). Assume negative edge triggered memory elements.
Task 2
Consider the following sequential circuit.
Answer the following questions. Make sure you include them in your lab report.
1) How many states does this sequential circuit have?
2) List the different state conditions for the input, output and the memory element.
3) Write the logic equations for the output, z, and the flip-flop, T.
4) Determine the output sequence, z, for an input sequence x=01101000 and an initial memory state y=0.
5) Draw the timing diagram for question 4.

Task 3
The state table and state diagram of the circuit can be found with the output and excitation equations found in Task 2. In order to find the state table, start with the blank state table given below. Next find the transition table by filling in the table with the next state/output (i.e., “1/0”). Finally, translate the transition table into the state table by giving the memory element states a name (i.e., name “0” state “A” and name “1” state “B”).
Answer the following questions. Make sure you include them in your lab report.
1) Fill in the transition table.
2) Translate the transition table into a state table
Task 4
Once the state table has been defined, the state diagram can be drawn.
Answer the following questions. Make sure you include them in your lab report.
1) Draw the state diagram using the Mealy Model.
2) Verify the timing diagram drawn in Task 2, question 5.

Experiment 2
The binary state table is given below. Complete the realization using D, clocked T, aked
JK flip-flops. To do this, first construct a K-map for the output z. The K-map l have the same form as the state table below, except it will not specify Y
2
Y
1
(i.e., il only specify z).
Next specify the truth tables for each flip-flop. You will need two flip-flops for each realization. Next, write the equations for each realization (i.e., for the D FF realization, you will hav ation for T , etc.)
The results for a few of the equations are given below for you to check your solution
(Note: the MSB has the subscript “2” and the LSB has the subscript “1”).
Experiment 3
Implement the D flip-flop realization on the Spartan 3 FPGA using VHDL. Use the clock file that you used to implement the Modulo-8 counter last week. Send the outputs Q
2 and
Q
1 to the LEDS on the FPGA board.