INTRODUCTION TO LOGIC DESIGN
1.0 LOGIC DESIGN
The basic device used in the operational or calculating sections of digital computers consists of
gates and devices called flip-flops. Every digital computer is constructed of these devices. Flipflops (FF) provides memory while gates provides operation on, or functions of the values stored
in these memory devices.
This section describes
 Flip-flops and their characteristics.
 Use of flip-flops and gates to perform several functions in computers i.e
o Counting in binary and BCD
o Transferring values and shifting or scaling values stored in flip-flops
 Clocks that are used to initiate operations
Flip-flops are also known as binary or toggle. There are other memory devices in computer such
as Inner memory/main memory and High speed memory.
Flip-flops are dominant because
1. It deals with actual operation
2. They are high speed-easy to read from or set
3. Flip-flops and gates interconnect in a natural way.
1.1
FLIP-FLOPS
A flip flop is a basic`circuit for storing information in a digital machine. There are several
fundamental types of flip-flops and many circuit designs although two characteristics are shared
by all flip-flops. These are:
1. It is a bistable device i.e. only two stable states (0 and 1 states)
a. It can retain state – the basis for information storage in the operating or
calculating sections of a digital computer
b. It can remember, or store a binary bit of information because of this
characteristics
c. It responds to inputs such that if an input cause it to go to HIGH state it will
remain there until some other signal causes it to go to the 0 state.
2. The flip-flop has two output signals, one of which is the complement of the other.
BLOCK DIAGRAM OF RS TYPE FLIP-FLOPS
S
X
INPUTS
OUTPUTS
R
X
There are two inputs S and R and two outputs x and x . To analyse its operation there are
several conversions that are standard in the computer industry.
1. Each flip-flop is given a name such as x, A, B or A1 or B2. The given block diagram
flip-flop is called X. It has outputs x and x which are always complement of each other
i.e. if x = 1, x =0 and vice versa.
2. The state of the flip-flop is taken to be the state of the x output. If output line x has
state of 1, we say the flip-flop is in the state of 1 and if the output line has a state of 0 we
say a flip-flop is in the state of 0.
The two input lines, S and R for the RS flip-flop are used to control the state of the flip- flop
according to these rules:
1. As long as both inputs lines S and R carry 0 signals, the flip-flop remains in the same
state, i.e. it does not change state.
2. A 1 signal on the S line (the SET line) and a 0 signal on R (the RESET line) cause the
flip-flop to set to the 1 state.
3. A 1 signal on the R line (the RESET line) and a 0 signal on S (the SET line) cause the
flip-flop to reset to the 0 state.
4. Placing a 1 on the S and a 1 on the R lines at the same time is forbidden. If this occurs,
the flip-flop can go to either state. (It is an ambiguous input condition in that it is telling
the flip-flop to both SET and RESET at the same time.
An example of possible sequence of input signals and the resulting state of the flip-flop is as
follows:
S
1
0
0
0
0
0
0
0
1
0
R
0
0
0
1
0
0
1
0
0
0
X
1
1
1
0
0
0
0
0
1
1
RS flip-flop waveform
The waveform represents a logic 1 as +2V and a logic 0 as 0V. These values are chosen
arbitrarily because these are very frequently used levels. Note that the flip-flop will change level
only when the input levels command it to. There should be a slight delay from when the flipflop is told to change states and when it changes, since no physical device can respond instantly:
Therefore it is assumed that the flip-flops delay in responding is so small that it can be
neglected.
1.2
TRANSFER CIRCUIT
Consider two sets of flip-flops X1, X2, X3 and Y1, Y2, Y3. Any related flip-flops such as X1,
X2, X3 are called a register and therefore this is Register X. So we have Registers X and Y for
these two sets of flip-flops.
A transfer circuit can be used to transfer contents of one register to another upon the transfer
command which consists of a 1 on the Transfer line.
Assume that register Y has been set to some states that we want to remember, or store in register
X while the Y register is used for further calculations.
Placing a 1 on the transfer line will cause this desired transfer of information. If Y1 is in the 0
state, Y1 output line has a 0 on it and so the input line connected to the AND gate will be a 0
and the AND gate will place a 0 on the S input line of X1. While Y 1 output from Y1 will be a 1
causing, in the presence of a 1 on a transfer line, a 1 on the R input of X1. Similarly, a 1 on Y1
will cause a 1 to be placed in X1 with transfer line set to 1.
When a transfer line is at 0 states, both inputs to the X flip-flops (X register) will be 0s and the
flip-flops will remain in the last state it assumed. The above process is called a TRANSFER
OPERATION
Exercise:
Draw a set of waveforms for S and R, X and X so that the flip flop will have the output signals
0011001 on the X output line. (Consider the RS flip-flop)
1.3
CLOCKS
Clocks are devices that sends out signals that are carefully regulated in time to initiate the
operations in digital computers.
The operations that depend on clock signals to initiate are called synchronous operations. There
are other operations that are triggered by other operations when they occurand do not depend on
clock signals to operate. These are called Asynchronous operations and are difficulty in design,
hence are rarely used.
The clock is the mover of the computer
 It measures time
 It sends out regularly spaced signals to make things happen.
It is possible to examine operations of flip-flops and gates before and after the clock initiates
action
Initiating signal are called clock pulses.



Flip-flops respond to either a falling edge or a rising edge.
cLOCKS are used to initiate flip-flops action and therefore are included in most flipflops
A flip-flop can respond to either positive going (rising edge) or negative going (falling
edge) but not both.
Positive going edge clocked flip-flop
Negative going edge clocked flip-flop
Sometimes a flip-flop is not marked with triangles as above but marked with CL to indicate a
presence of a clock. In this case a manufacturer will indicate whether it is a positive triggered or
negative triggered.
In the presence of clocks most clocked flip flops actually responds to a change in clock input
level not to the level itself. Therefore in this case the flip-flop will operate according to these
rules:
1. If the S and R inputs are 0s when the clock edge pulse occurs, the flip-flop does not
change states but remains in its present state.
2. If S is set to 1 and R to 0 when the clock pulse signal occurs the flip flop will go to the 1
state.
3. If the S input is 0
1.4
DESIGN OF FLIP FLOPS
1.5
The
D Latch and the D flip-flop
It is possible to create a latch which has no race condition, simply by providing only one input to
a RS latch, and generating an inverted signal to present to the other terminal of the latch. In this
case, the S and R inputs are always inverted with respect to each other, and no race condition
can occur. The circuit for a D latch is shown in Figure 2.7.
Figure 2.7:
The D latch is used to capture, or ``latch'' the logic level which is present on the Data line when
the clock input is high. If the data on the line changes state while the clock pulse is high, then
the output,
(a).
, follows the input,
. This effect can be seen in the timing diagram, Figure 2.8
The D flip-flop, while a slightly more complicated circuit, performs a function very similar to
the D latch. In the case of the D flip-flop, however, the rising edge of the clock pulse is used to
``capture'' the input to the flip-flop. This device is very useful when it is necessary to ``capture''
a logic level on a line which is very rapidly varying. Figure 2.8 (b) shows a timing diagram for a
D-type flip-flop. This type of device is said to be ``edge triggered'' -- either rising edge triggered
(i.e. a 0-1 transition) or falling edge triggered (i.e., a 1-0 transition) devices are available.
Figure 2.8:
Both the D latch and D flip-flop have the following truth table:
Clock D Q
0
1
x
x
1
0
1
0
x
x
0
1
0
0
x
x
1
1
1
1
0
0
1
1
1
1
1
0
1
1
or 1
or 1
0
X
The symbol means a leading edge, or
latch, it would be the level 1.
transition as the clock input to the flip-flop. For a D
The JK flip-flop
The JK flip-flop is the most versatile flip-flop, and the most commonly used flip-flop when
discrete devices are used to implement arbitrary state machines. Like the RS flip-flop, it has two
data inputs, J and K, and a clock input. It has no undefined states or race condition, however. It
is always edge triggered; normally on the falling edge. (some JK flip-flops; e.g., 74109, trigger
on the positive edge.)
The JK flip-flop has the following characteristics:
1. If one input (J or K) is at logic 0, and the other is at logic 1, then the output is set or reset
(by J and K respectively), just like the RS flip-flop, but on the (falling) clock edge.
2. If both inputs are 0, then it remains in the same state as it was before the clock pulse
occurred; again like the RS flip-flop.
3. If both inputs are high, however the flip-flop changes state whenever the (falling) edge
of a clock pulse occurs; i.e., the clock pulse toggles the flip-flop.
There are two basic types of JK flip-flops. The first type is basically an RS flip-flop with its
outputs Q and Q ANDed together with J and K respectively. This type of JK flip-flop has no
special name. Note that the connection between the outputs and the inputs to the AND gates
determines the input conditions to R and S when J = K = 1. This connection is what causes the
toggling, and eliminates the invalid condition which occurs in the RS flip-flop. A simplified
form of this flip-flop is shown in Figure 2.9 (a).
The second type of JK flip-flop is called a master-slave flip-flop. This consists of two RS flipflops arranged so that when the clock pulse enables the first, or master, latch, it disables the
second, or slave, latch. When the clock changes state again (i.e., on its falling edge) the output
of the master latch is transferred to the slave latch. Again, toggling is accomplished by the
connection of the output with the input AND gates. An example of this type of flip-flop is
shown in Figure 2.9 (b). Figure 2.9 (c) shows the circuit symbol for a JK flip-flop.
Figure 2.9: JK flip-flop
The JK flip-flop is a very versatile device, and is probably the most commonly used form of
flip-flop in digital electronic and control circuits. The fact that it has two inputs often means that
it is simpler to design the control logic required to ensure that it changes state properly in a
circuit.
The T flip-flop
This type of flip-flop is a simplified version of the JK flip-flop. It is not usually found as an IC
chip by itself, but is used in many kinds of circuits, especially counter and dividers. Its only
function is that it toggles itself with every clock pulse (on either the leading edge, on the trailing
edge) it can be constructed from the RS flip-flop as shown in Figure 2.10 (a).
Figure 2.10: The T flip-flop
This flip-flop is normally set, or ``loaded'' with the preset and clear inputs. It can be used to
obtain an output pulse train with a frequency of half that of the clock pulse train, as seen from
the timing diagram, Figure 2.10 (b). In this example, the T flip-flop is triggered on the falling
edge of the clock pulse.
Several T flip-flops are often connected together in a simple IC to form a ``divide by N'' counter,
where N is usually 5, 10, 12 or a power of 2.




Data registers:
Shift registers
Counters - weighted coding of binary numbers
Synchronous counters
Data registers:
The simplest type of register is a data register, which is used for the temporary storage of
a ``word'' of data. In its simplest form, it consists of a set of N D flip-flops, all sharing a
common clock. All of the digits in the N bit data word are connected to the data register
by an N line ``data bus''. Figure 2.11 shows a four bit data register, implemented with
four D flip-flops.
Figure 2.11: 4-bit D register
The data register is said to be a synchronous device, because all the flip-flops change
state at the same time.
Shift registers
Another common form of register used in computers and in many other types of logic
circuits is a shift register. It is simply a set of flip-flops (usually D latches or RS flipflops) connected together so that the output of one becomes the input of the next, and so
on in series. It is called a shift register because the data is shifted through the register by
one bit position on each clock pulse. Figure 2.12 shows a four bit shift register,
implemented with D flip-flops.
Figure 2.12: 4-bit serial-in serial-out shift register
On the leading edge of the first clock pulse, the signal on the DATA input is latched in
the first flip-flop. On the leading edge of the next clock pulse, the contents of the first
flip-flop is stored in the second flip-flop, and the signal which is present at the DATA
input is stored is the first flip-flop, etc. Because the data is entered one bit at a time, this
called a serial-in shift register. Since there is only one output, and data leaves the shift
register one bit at a time, then it is also a serial out shift register. (Shift registers are
named by their method of input and output; either serial or parallel.) Parallel input can be
provided through the use of the preset and clear inputs to the flip-flop. The parallel
loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or
asynchronous (independent of the clock pulse) depending on the design of the shift
register. Parallel output can be obtained from the outputs of each flip-flop as shown in
Figure 2.13.
Figure 2.13: 4-bit serial-in parallel-out shift register
Communication between a computer and a peripheral device is usually done serially,
while computation in the computer itself is usually performed with parallel logic
circuitry. A shift register can be used to convert information from serial form to parallel
form, and vice versa. Many different kinds of shift registers are available, depending
upon the degree of sophistication required.
Counters - weighted coding of binary numbers
In a sense, a shift register can be considered a counter based on the unary number system.
Unfortunately, a unary counter would require a flip-flop for each number in the counting
range. A binary weighted counter, however, requires only
flip-flops to count to N.
A simple binary weighted counter can be made using T flip-flops. The flip-flops are
attached to each other in a way so that the output of one acts as the clock for the next, and
so on. In this case, the position of the flip-flop in the chain determines its weight; i.e., for
a binary counter, the ``power of two'' it corresponds to. A 3-bit (modulo 8) binary counter
could be configured with T flip-flops as shown in Figure 2.14.
Figure 2.14: A 3-bit binary counter
A timing diagram corresponding to this circuit is shown in Figure 2.15.
Figure 2.15: 3 bit counter timing diagram
Note that a set of lights attached to
, , would display the numbers of full clock
pulses which had been completed, in binary (modulo 8) from the first pulse. As many T
flip-flops as required could be combined to make a counter with a large number of digits.
Note that is this counter, each flip-flops changes state on the falling edge of the pulse
from the previous flip-flop. Therefore there will be a slight time delay, due to the
propagation delay of the flip-flops between the time one flip-flop changes state and the
time the next one changes state. i.e., the change of state ripples through the counter, and
these counters are therefore called ripple counters. As in the case of a ripple carry adder,
the propagation delay can become significant for large counters.
It is possible to make, or buy in a single chip, counters which will count up, count down,
and which can be preset to any desired number. Counters can also be constructed which
count in BCD and base 12 or any other number base.
A count down counter can be made by connecting the output to the clock input in the
previous counter. By the use of preset and clear inputs, and by gating the output of each T
flip-flop with another logic level, using AND gates (say logic 0 for counting down, logic
1 for counting up) then a presetable up-down binary counter can be constructed.
Figure 2.16 shows an up-down counter, without preset or clear.
Figure 2.16: Programmable up/down counter
Synchronous counters
The counters shown previously have been ``asynchronous counters''; so called because
the flip-flops do not all change state at the same time, but change as a result of a previous
output. The output of one flip-flop is the input to the next; the state changes consequently
``ripple through'' the flip-flops, requiring a time proportional to the length of the counter.
It is possible to design synchronous counters, using JK flip-flops, where all flip-flops
change state at the same time; i.e., the clock pulse is presented to each JK flip-flop at the
same time. This can be easily done by noting that, for a binary counter, any given digit
changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a
value of 1. Figure 2.17 shows an example of a 4-bit binary synchronous counter. A count
down timer can be made by connecting the output to the J and K, through the AND
gates. Preset and clear could also be provided, and the counter could be made
``programmable'' as in the previous case.
Figure 2.17: 4-bit synchronous counter
The timing diagram is similar to that shown for the asynchronous (ripple) counters,
except that the ripple time is now zero; all counters clock at the same time. It is common
for synchronous counters to trigger on the positive edge of the clock, rather than the
trailing edge.