ECE 3714- Spring 2002
Test #3A
Name____________________
1. (8 pts) Draw an equivalent circuit to the one below using a decoder and
tri-state buffers.
2. (6 pts) Show how to construct a 3-bit wide 2/1 mux from 1-bit wide 2/1
muxes.
A(2)
Y(2)
B(2)
A(1)
Y(1)
B(1)
A(0)
Y(0)
B(0)
SEL
3. (6 pts) Shown below is a D flip flop built using two D latches. The latches
are in a master/slave configuration.
a. Which latch is the master?
A
b. Is this a rising edge triggered or falling edge triggered D flip flop?
Falling
4. (10 pts) Complete the timing diagram for the following circuit by drawing
the diagrams for Qa and Qb.
C
D
Qa
Qb
5. (10 pts) Give the state tables and characteristic equations for each flip flop
or latch using the following:
Remains the same (Q(t))
Resets to zero (0)
Sets to one (1)
Toggles (Q’(t))
a)
b) an S-R latch
6. (8 points)The SR latch below has unpredictable results if S = R = 1 and then both
inputs simultaneously go to zero. One way to solve this problem is to create a setdominant SR latch so that when S = R =1, the latch is set to 1. Design a set-dominant SR
latch by adding logic gates to the circuit below.
7. (6 pts) Draw a schematic for a 1 bit register using a D flip flop and a mux.
(Make sure to include all necessary inputs)
8. (9 pts) Answer the following questions about the operation of the counter
shown below.
a. Let LD = 1, EN = 0, DIN = $A2, ACLR = 0, DOUT = $55. On the next
rising clock edge, what will be the value on DOUT?
$A2
b. Let LD = 0, EN = 1, DIN = $A2, ACLR = 0, DOUT = $55. On the next
rising clock edge, what will be the value on DOUT?
$56
c. Let LD = 0, EN = 0, DIN = $A2, ACLR = 0, DOUT = $55. On the next
rising clock edge, what will be the value on DOUT?
$55
9. (6 pts) Answer the following questions about the schematic below.
a. Is the schematic of a 4 bit combinational left shifter or 4 bit combinational
right shifter?
Left Shifter
b. Let D = 1101, SI = 0, and EN = 1. What is the value of Y?
1010
10. (15 pts) Shown below is one implementation for a 4 bit shift register.
Complete the timing diagram to illustrate the behavior of this shift register
by showing the values of Dout.
11. (16 pts) Circle the correct answer in each statement.
a. With asynchronous inputs, output changes (dependent / independent ) of
the clock.
b. On a D flip flop, the D input is ( synchronous / asynchronous ) .
c. Setup time is the amount of time the synchronous inputs must be stable
(before / after ) the active edge of the clock.
d. Hold time is the amount of time the synchronous inputs must be stable
(before / after ) the active edge of the clock.
e. A ( combinational / sequential ) system is a system whose outputs
depends only upon its current inputs.
f. A ( register / counter / shift register ) is used for serial to parallel,
parallel to serial data conversion.
g. S in the diagram below represents the clock ( period / frequency / duty
cycle / pulse width)
h. In the diagram below, the frequency of B is ( half / twice ) the frequency
of A.