ECE3724 Summer 2003
Take Home Test #3
Name__Solutions___
From Chapter 7, Self-test and Analysis and Design (page 405 Uffenbeck), work the
following problems:
1. Calculate the access time provided by a 486 processors with a 60MHz bus
frequency.
Taccess = (1/60)(10-6)(1.5) = 25nsec
2. Why is the access time of a processor important? What does it mean?
The processor access time is the “window of opportunity”; memory chips
must be able to output valid data within this amount of time, in order to
avoid having wait states. The processor access time is how much time the
processor allows for memory chips to respond.
3. Repeat question 1, assuming two wait states are added.
Taccess = (1/60)(10-6)(1.5) = 25nsec + 2(1/60)(10-6) = 58.33 nsec
******* was missing a 2 in 3-2-2-2 ********
4. An asynchronous SRAM performs 3-2-2-2 burst cycles. How many total wait
states are required per burst cycle assuming 2-1-1-1 processor burst cycles.
The SRAM requires 9 clock cycles to complete the burst transfer – Since
the processor can normally handle it with 5 clock cycles, 4 wait states are
required.
5. Why is a burst cycle faster than a conventional memory bus cycle?
Burst cycles allow bursts of data to be transferred to the processor cache
without requiring extra clock cycles to transfer the addresses.
*******BE3’ should have been written rather than BE1’*******
6. A 486 processor is accessing a memory word at address 00000036h. Determine
the logic levels required on the processor’s A31-A2 address pins and the 4-byte
enables BE3’ – BE0’ (note that the byte enables are active-low).
Each of the hex digits of the address is 4 bits. Looking at each of the address pins
below shows the values. Note that the 486 does not have pins A1 and A0. Pins BE3
through BE0 are used instead. A word is to be accessed so locations 36 and 37 must
be accessed.
31
30
29
28
27 26 25 24
23 22 21 20
19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
1
1
0
1
BE3
BE2
BE1
BE0
0
0
1
1
0
0
7. Draw a diagram similar to Figure 7-26 using 128k x8 SRAMS instead of the
64kx8 shown. Show the decoder required to map your circuit to the address range
40000-7FFFFh.
See attachment
8. Refer to the 8088 memory map shown in Figure 7-63. Draw the schematic of the
required memory interface similar to Figure 7-38. If you had Digital Devices
here, what is a PAL?
See attachment
From Chapter 11 Analysis and Design,
9. Match the support chips for the PC/XT with the following numbers: (8087, 8237,
8255A, 8259A, 8284, 8288)
a.
b.
c.
d.
e.
f.
Interrupt Controller
Clock generator
Math coprocessor
Memory refresh, disk drive data transfers
System configuration, keyboard access, speaker control
Bus controller
8259
8284
8087
8237
8255
8288
PIC
clock
Coprocessor
DMA control
PPI
From Chapter 8 Self test
10. Work problems 2, 5, 14, 15.
2. When M/IO’ is low and W/R’ is high, what type of bus cycle is occurring?
(d)I/O write
5. In the polling routine shown below, the BUSY/READY status bit is ______
when the printer is busy, and is input as bit __6______ of port _5___.
14. Each counter in the 8254 can be operated with a different clock signal.
True
15. To produce a single active-low pulse 10 clock pulses after an active-high
clock signal is applied, program the 8254 for mode __5__.
11. Explain polling.
With polling, the processor waits for the peripheral to be READY so that
more information can be sent. An inefficient way of utilizing the
processor.
From Chapter 8 Analysis and Design Questions (page 461)
12. Work problem 8.4 parts a-e
a) memory mapped
b) 8 bits
c) output port
d) Any memory address between 80000000h and
FFFFFFFFh; 2 G ports
e) Mov [80000000], AL
From Chapter 9 Self-Test (page 507)
13. Work problems 1-7, 10, 12, 14
1. The 80x86 processors can receive interrupts from three different sources. List
these.
a. Internal ( due to a fault)
b. Software (INTn)
c. Hardware (NMI, INTR, etc…)
2. The 80x86 processors have two general-purpose hardware interrupts, called
_NMI_______ and __INTR_. Of these, interrupts on __INTR____ can be
blocked by giving the ___CLI_ instruction.
3. Simultaneous interrupts occur in INTR and NMI. Which one will the 80x86
processors respond to first?
NMI, it has the highest priority
4. Assume a peripheral has an interrupt service routine stored at 0783:0010h.
Determine the contents and location of the interrupt vector if type number
20010 is used.
The vector 10 00 83 07 is stored beginning at 320h (20010 x 4 = 80010 = 320h)
5. What type of interrupt causes an interrupt acknowledge cycle to be run? What
is the purpose of this cycle?
Only interrupts on INTR cause interrupt acknowledge cycles. These
cycles are used to input the type number from the interrupts device.
6. Under what conditions can an interrupt on INTR interrupt an ISR currently
running?
If the currently running ISR sets the interrupt flag (STI), then other
interrupt requests will be able to interrupt this routine.
7. How does the 8259A PIC indicate interrupts that are currently in service?
The corresponding IS bit is set.
10. To program PIC input IR5 to produce a type number of 75h, the base address
__70h___ should be written to __ICW2___.
12. During DMA cycles, the processor __open___ __circuits_______ its data,
address, and control buses.
14.If the processor receives simultaneous HOLD and NMI requests, which input
will be serviced first?
HOLD has the highest priority
From Chapter 10 Self-Test (page 576)
14. Work problems 1-3
1. Calculate the character rate for a serial port programmed for 9600 bps, 8 data
bits, 1 start bit, and 1 stop bit.
9600bits per sec/10 bits per char = 960 chars/sec
2. Assume COM2 is to be programmed as described in Question 1. Give the
DOS mode command required.
MODE COM2: 96,n,8,1
;n => no parity
3. Asynchronous serial data is said to be self-synchronizing. Explain.
Because each character begins with a start bit, the receiver can
resynchronize itself to the incoming data.
Problem #7
Problem #8