RESOLUTION
Reconfigurable Systems for Mobile Local Communication and Positioning
RESOLUTION Project
IST - 026851
Assembling of ASIC and FPGAs on BB board [D8]
Document Information
Title
D8 – Assembling of ASIC and FPGAs on BB board
Workpackage
WP5 – Baseband
Responsible
Due Date
Project Month 15 (April 2007)
Type
Report
Status
Version 1.4
Security
Public
Authors
D. Doumenis
Project URL
http://www.ife.ee.ethz.ch/RESOLUTION/
D8 – Assembling of ASIC and FPGAs on BB Board
Page 2
Table of contents
TABLE OF CONTENTS .............................................................................................. 2
1
INTRODUCTION ................................................................................................. 3
1.1
SCOPE .............................................................................................................. 3
1.2
METHODOLOGY ................................................................................................... 3
2
SYSTEM DEVELOPMENT ..................................................................................... 6
2.1
FPGA SELECTION ............................................................................................... 7
2.2
DATA CONVERTERS .............................................................................................. 9
2.2.1
ANALOG TO DIGITAL CONVERTERS (A/D) ................................................................... 9
2.2.2
DIGITAL TO ANALOG CONVERTERS (D/A) ................................................................. 15
2.3
BOOT ROM ..................................................................................................... 16
2.4
EXTERNAL RAM ................................................................................................ 18
2.5
INTERFACING WITH WIRELESS LAN...................................................................... 20
2.6
INTERFACING WITH THE ANALOG FRONT-END ......................................................... 22
3
TEST SETUP ..................................................................................................... 25
3.1
THE PROTOTYPING BOARD .................................................................................. 25
3.2
THE ANALOG FRONT-END .................................................................................... 28
4
BILL OF MATERIALS .......................................... ERROR! BOOKMARK NOT DEFINED.
5
IMPLEMENTATION ........................................................................................... 30
6
CONCLUSIONS ................................................................................................. 32
7
REFERENCES .................................................................................................... 32
8
APPENDIX I: FPGA SCHEMATICS ..................................................................... 33
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 3
1 Introduction
This report elaborates on the baseband hardware details of the RESOLUTION positioning
system. Every effort has been made to produce a hardware design which is both, flexible and
upgradeable, as well as capable of being integrated into larger systems as the range of
applications is very broad. The baseband board will be able to integrate a wide range of FPGAs
having the same footprint, from medium sized to very large ones, as well as a number of analog
channels for communicating with the antennae. Any type of system will be able to be
implemented in this reconfigurable architecture, ranging from simple single antenna cheap PDA
implementations to MIMO-type complex systems running on a laptop PC.
1.1 Scope
A number of system architectures were considered before reaching the proposed one where a
reconfigurable system will be developed having the resources to interface to single or multiantennae systems by downloading different VHDL codes on smaller or larger FPGAs which can
be assembled on exactly the same Printed Circuit Board (PCB). The system will also have the
ability to interface with WLAN subsystems where such infrastructure is not already built-in, as
well as a number of A/D and D/A channels for interfacing with the outside world.
1.2 Methodology
The methodology for producing a reconfigurable baseband board, required the assembly of a
prototype system using off-the-shelf modules (e.g. A/D evaluations board, FPGA development
board, prototyping area etc) which gave an insight on the requirements of a compact (in size), yet
powerful architecture combining analog and digital subsystems, having low power consumption.
The range of system applications, call for designs of varying complexity, size, cost and power
consumption. As seen in Table 1, the main applications categories (as shown in more detail in
Deliverable D2), require a varying degree of system complexity, from low cost, simple PDAbased systems for interactive guiding to more complex customer-specific hardware as in the case
of Automated Guided Vehicles (AGVs)
In Deliverable D4 (“Definition of architecture, link budget and specifications for the
components”), it was further shown what the possible hardware platforms for the two main
applications should be, as shown in Table 2. Based on this information, one could provide two
basic system architectures. A simple, low cost solution, interfacing to printed antennae (see
Deliverable D3) implemented in a PDA platform for interactive guiding and a more involving
and expensive one with interfaces to multiple antennae and a larger FPGA for AGV applications.
The AGV solution would have to be implemented in a PC-Card format which can interface
directly to a laptop PC, whereas the PDA solutions would have to be substantially smaller, such
as a compact flash (CF) or secure digital (SD) card. However, a CF or SD implementation can
use a PC-Card adapter to interface to a laptop, whereas the opposite is not possible due to size
constraints. Please refer to Fig. 1.1 for an approximate scale model of most necessary
components conducted during the preparation of Deliverable D4 and placed in the three possible
PCB sizes (PC-Card, CF, SD).
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 4
Application
Short description
Potential customers
Location
accuracy/
Range
Data volume
Equipment
Building type
Number of
concurrent
users
AGVs
Control of automated vehicles
Logistics Companies
5cm/<500m
Medium
(text,photos)
Customer-specific
Factory halls
<5
Interactive
guiding
application
Real-time active mapping and guiding for
advanced sightseeing
Museums, art galleries,
archaeological
sites,
botanical gardens, zoos,
exhibitions, etc.
30cm/<50m
Large
(text,
photographs,
video, 3D, etc)
Specialized
hand-held
device (PDA-like)
Numerous
rooms,
different room
sizes
30–50 (visitors)
Table 1: Main application categories from the marketing report (Deliverable D2)
AGV vehicle guidance
Accuracy
[m]
0.05
Service
Area [m2]
500 x 500
position
update
rate
10ms
System
Operational
modes
FDD
Communication
Data Transfer
Volume & Speed
„high“
Environment
Indoor
2D vs
3D
2D
Location-Based
information
resides with
mobile unit (m.u.)
Dynamic
Range
n/a
Mobiles
batteryoperated?
No
Smart (museum) guiding
0.3
500 x 500
~10
seconds
TDD, FDD
High, MB/s
Indoor
2D
fixed infrastructure
(f.i.)
2-50m
Yes, ~3
hours
Application
AGV vehicle guidance
Market
Industry
Smart (museum) guiding
Consumer
Application
Interface requirements
mobile unit
Design Objectives
Proprietary / tbd
Accuracy, Performance
SDIO, CF, PCMCIA
Look, size, cost
Number of mobile
units in service area
1-2
Ratio of
BS/mobiles
>1
Indoor Propagation Channel shorttime quasi-static ?
Potentially yes
50-200
<< 1
Probably not (people)
Table 2: Some technical requirements of the two main target applications (Deliverable D4)
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 5
Figure 1: Indicative dimensions of main components in PC-Card, Compact Flash and Secure Digital card
(1 square mm grid)
A PC-Card implementation would have to be 54mm wide by a minimum of 85.6mm long which
is more than enough space to place and route all the necessary components as one can see on the
top part of Figure 1. A very powerful FPGA and multi-channel ADCs and DACs could be
employed for even the most demanding AGV application employing multi-antenna systems.
Next in size is the Compact Flash type card which has to be 43mm wide by a minimum of 36mm
long. The length can be more than 36mm and this is usually the case in PDA cards, where part of
the card is protruding from the PDA surface, incorporating connectors, antennae etc. In the case
of a TYPE I CF card, the thickness of the card can be up to 3.3mm and for a TYPE II CF card, it
can be up to 5mm thick. Both thicknesses provide enough headroom for all the necessary
components with a good compromise between small size and flexibility, as a CF card can be
connected to a laptop PC-Card slot, through inexpensive adaptors (see Figure 2).
The smallest of the 3 possible implementations is the Secure Digital Input/Output (SDIO) card
which must have a width of 24mm and a length of at least 32mm. The red boundary in the
bottom right part of Fig.1 shows the actual SDIO card dimensions, whereas the blue boundary
indicates the extended length (a minimum of 21mm) that the card must have in order to fit the
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 6
basic components. Another limitation of the SDIO architecture is the maximum thickness of
2.1mm that such a card must have. Such a thickness constraint will force the use of very exotic
low-profile FPGA, data converter and memory packages which will increase the cost, or force
most of the components to be placed outside the slot (by increasing the “blue” area), making the
design much prone to breakages, as the stresses and strains to the connector will increase due to
the sheer weight of the components.
Figure 2: Compact Flash to PC-Card adaptor
To avoid having to develop 2 separate systems (AGV and cultural guiding), a single
reconfigurable CF system with standard CF interface was envisaged having the necessary
infrastructure to implement either of the two scenarios. This approach would allow standard
PDA and PC applications to be developed in order to interface with the CF card which will
behave to the “outside world” as a simple memory card updating some memory locations
containing the distances from the mobile station to each of the basestations. These distances can
then be displayed, or use the PDA or PC to perform triangulation and obtain the x,y,z coordinates
of the mobile station.
For a comparative description of the sizes and speeds of the three card architectures (Secure
Digital, Compact Flash and PC-Card), please refer to Table 3.
SD
Length*width
Thickness
Connector
Transfer Speed
24x32mm2
2.1mm
9 pins
<100Mb/s
I/O Voltages
2,0..3,6 V
Compact Flash
Type I
Type II
36.4x42.8 mm2
3.3mm
5.0mm
50 pins
16 MB/s .. 66 MB/s
166 MB/s (Ultra DMA)
PCMCIA
Type I
Type II
Type III
54x85.6 mm2
3.3mm
5.0mm
10,5mm
68 pins
16b I/O Transfer: 3.9/7.8MB/s
16b Mem Transfer: 10/20MB/s
CardBus (32b bursts): 33/66MB/s
3V3 (100mA) or
5V0 (75mA)
Table 3: Comparative dimensions and speeds of the 3 interfaces
2 System development
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 7
2.1 FPGA Selection
Initially, a series of time-critical VHDL codes were developed and simulations were run to
validate their operation and performance. The main purpose of this exercise was to get a rough
estimate for the required gate-count that the FPGA must employ. The main FPGA manufacturers
having the lion’s share of the global market are Altera (www.altera.com) and Xilinx
(www.xilinx.com). Due to more recent exposure to Xilinx design flows and the availability of
inexpensive evaluation boards as well as free (or cheap) software, it was decided that the
development should be done using Xilinx tools and hardware. Another advantage of the Xilinx
architecture is the fact that it allows dynamic reconfiguration in the field, so that the binary file
implementing the FPGA architecture can be altered at runtime, or various different such codes
can be stored in the same ROM and selected during operation. From these initial investigations
(as detailed in the WP5 annual report), it was shown that an FPGA with at least 500K gates
would be adequate for implementing most subsystems excluding the Adaptive Antenna
Combining (AAC) algorithms. The more relevant Xilinx FPGA families for implementing such
designs are the following:
Spartan-3: Low cost alternative to small ASIC designs with the ability to implement DSP
functions. The Spartan-3 family suffers from limited routing capabilities compared to the Virtex
families to keep manufacturing costs down.
Virtex-4: Long established high-end family with strong DSP support and some family members
offer embedded Power-PC microprocessors or synthesizable soft-core MicroBlaze processors.
Virtex-5: More recent, 65nm technology FPGAs with superior routing and speed improvements.
A good compromise between the two ends would be the Virtex-4 family which offers more
routing capabilities (required for a small-sized PCB) without the extreme packages offered by
the Virtex-5 propositions. In Figure 3, one can observe the available packages existing for a
Virtex-4 LX FPGA. There also exist, the SX and FX families giving a greater choice of
application optimised devices.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 8
Figure 3: Choosing the most flexible Virtex-4 package
Choosing the FF668 Ball Grid Array (BGA) package, one can have the following options
without changing footprint (see Table 4):
Type
FX12
LX15
LX25
SX25
SX35
LX40
LX60
Logic Cells RAM (Kb) PowerPC
12312
648
1
13824
864
N/A
24192
1296
N/A
23040
2304
N/A
34560
3456
N/A
41472
1728
N/A
59904
2880
N/A
DCMs
4
4
8
4
8
8
8
Table 4: Resources of footprint-compatible devices
Hence, there will be a very wide choice of gate-counts with or without a PowerPC hard core.
Soft MicroBlaze processor cores can be implemented using standard logic and about 2000 Logic
Cells for each core. The downside of such flexibility is that the FF668 package is physically
larger than the SF363 that was originally considered in Figure 1. For a comparison between the
two packages, consider the fact that the SF363 is 17mm by 17mm, whereas the FF668 is 27mm
by 27mm. This is a 2.5 times increase in area, but gives a whole range of different
implementable architectures, that the SF363 package cannot match. The SF363 supports devices
up to LX25 (24192 Logic Cells) and the FF668 goes all the way up to LX60 (59904 Logic
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 9
Cells). Hence a 2.5 times increase in area, gives almost 2.5 times more resources for high-end
applications. It is like designing a multi-chip system, only with much easier overall routing and
communication between the constituent FPGAs.
For an overview of how the FPGA pins, divided into banks are connected to the rest of the
peripherals, please consult Appendix I.
2.2 Data Converters
2.2.1
Analog to Digital Converters (A/D)
As presented in Deliverable D3 (“Characterisation and Modelling of Radio
Channel”), a radio channel exhibiting multipath phenomena exists in the
measurement sites. To combat such multipath effects, one can consider multiple
antennae with a clever Adaptive Antenna Combining (AAC) algorithm to improve
the performance of the system. Hence, the single reconfigurable baseband system
must be able to combine inputs from a number of Intermediate Frequency (IF)
channels which are being fed by separate antennae. The general idea behind the AAC
and the need for multiple A/D channels is shown in Figure 4.
Figure 4: AAC and the need for multiple A/D channels
Trying to implement a large number of A/Ds in the limited space offered by a compact
flash design is a conflicting requirement. It was decided (in the Athens meeting, Dec 8th
2006 in the premises of RESIT/AIT) to have the infrastructure for interfacing with 6 A/D
channels. Such channels should have a resolution of 14-bits (as required by Siemens) and
therefore, if such an A/D existed with parallel outputs, it would sport at least
6 X 14 = 84 pins for the digital data alone
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 10
Adding ground pins etc, it would be a very large data converter with a lot of interference
due to many data lines switching together. Alternatively, more twin or quad A/D
converters could be used, taking precious PCB real estate. A more suitable choice would
be an octal A/D converter with serial differential outputs for improved noise immunity.
Such a converter is the AD9252 from Analog Devices, having 8 channels with 14-bit
resolutions and a maximum sampling rate of 50 MSPS. The AD9252, instead of
providing separate data buses for each converter, uses serial LVDS outputs where each
bit is serially transmitted (signal D) and a sampling clock (DCO) is generated from the
converter to sample the data on its rising and falling edges. Another signal (FCO)
indicates the start of each new 14-bit word. For a more detailed description of the
relevant signals, please consult Figure 5 where the A/D sampling clock (CLK) is also
shown.
Figure 5: AD9252 serial differential output signals
The mode of operation is as follows. A 14-bit shift register is fed with bits from “D”
sampled at the rising and falling edge of “DCO”. At the rising edge of “FCO”, the bits
stored within the shift register are unloaded in parallel to a bus Din[13..0] which feeds a
4096 position buffer collecting data for the FFT operation. When 4096 such word are
collected (i.e. after 14*4096=57344 edges of the “DCO” signal) the FFT has enough data
to perform its operation and then extract the peak location etc. In the meantime, the shift
register is collecting the next batch of data and so on. Please note that the “DCO” clock is
14 times higher than the A/D sampling clock. Hence as the A/D input will be a sinewave
whose frequency will vary from 500 Hz to almost 5 MHZ, the sampling clock will be of
the order of 10 MHz and the DCO clock will be 14x10=140 Mbit. This clock can
eventually be the only clock going to the FPGA, as it will be used to format all incoming
data into parallel words and batches. From then on, the data can be calculated in batch
mode, producing input peak locations (and corresponding distance measures) for every
4096-word batch, producing a theoretical update rate of:
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 11
10x10^6/4096=2441 distance measures per second
There will of course be more than one distance measure necessary for triangulation
(producing the mobile station’s x,y,z coordinates), so the above update rate will be
reduced. It was shown in previous WP5 progress reports, that a minimum of 4 basestation
distance measures are necessary for accurate positioning, so the update rate will be
reduced by at least a factor of 4, namely 2441/4=610 updates per second peak. This
reasoning requires the calculation of the distance measure to be completed in less time
than it is required for the buffer to fill with the next 4096 14-bit words. Presently, the
peak location calculation takes less than 3000 A/D sampling intervals (with a maximum
target of 4096), so the measurements can be sustained at the full rate described above. If
the required clock cycles to process a 4096 point batch become greater than 4096, then
one will have to process only odd-numbered batches, ignoring the even numbered ones,
reducing the update rate to half.
In order to simplify the demonstration setup and defer the testing of the serial to parallel
data conversion until the card has been manufactured, a similar A/D converter with
parallel outputs has been considered. This converter is the AD9248, also from Analog
Devices which is a dual 14-bit converter with parallel outputs and maximum sampling
rate of 65 MSPS. In Figure 6 one can observe the evaluation boards for the 8-channel
AD9252 and the dual channel AD9248. Notice the digital output connector on the right
hand side of each board, where the AD9252 has much fewer lines (appropriate for a
compact flash sized card) whereas the AD9248 has much more lines (appropriate for
system development and debugging).
Figure 6: Boards for 8-ch AD9252 (left) and 2-ch AD9248 (right)
In Figure 7 one can compare the enormous area savings made possible with the utilisation
of the AD9252. Both chips have almost the same area, but in order to implement 6 A/D
channels using AD9248s, a total of 3 chips would be required, whereas a single AD9252
includes 8 channels. The design of the AD9252 Evaluation Board, gave a lot of insight on
the approach that had to be taken when the analog and digital subsystems had to co-exist
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 12
(signal tracks, ground planes, routing “tricks” etc). However, the code was being
continuously developed, so the debugging flexibility of the AD9248 was very beneficial.
Figure 7: Space savings using the octal AD9252
In Figure 8, the schematic for connecting the AD9252 to the board is shown. Notice the
use of “only” six analog channels, out of eight for interfacing with the analog front-end
and being able to implement a series of Adaptive Antenna Combining algorithms, using
up to six antennae depending on the application.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 13
Figure 8: AD9252 Schematic
Another important consideration for the optimum operation of the A/D converter is the
following. For best signal to noise ratio and interference rejection, the analog input at the
ADC has to be 1 or 2 Volts peak to peak (depending on the mode of operation). For best
performance, a 2 V ptp input is required giving a resolution of:
2/(2^14)=122 microVolts per LSB
Any input which is less than 2V ptp, would reduce the Effective Number Of Bits (ENOB)
accordingly and hence the accuracy of the operations that follow.
Unfortunately, the signal provided by the analog front-end (LNA+MIXER) is only
120mV ptp. Feeding this signal to the converter directly would give less than 10-bits
accuracy out of a 14-bit converter. Hence, this signal had to be amplified by a factor of
17 (2/0.120) using a Variable Gain Amplifier (VGA). Performing this amplification for
the 6 ADC channels without claiming a lot of board real-estate, was also a difficult task.
The Analog Devices AD8334 (Quad VGA) and its little sibling, the AD8332 (Dual
VGA) were originally considered as reliable choices with excellent noise performance
and relatively small footprint. After an original design (see Figure 9) using the Analog
Devices VGAs, we came across a limitation due to the power supplies needed.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 14
Figure 9: Voltage Gain Using Variable Gain Amplifier
Please note that the AD8334 and the AD8332, require a single 5V power supply. The
Compact Flash specification, states that the CF host can provide either a 3.3V, or a 5V
supply, but the CF card must be able to operate in either environment. Recent CF hosts,
such as Personal Digital Assistants (PDAs), tend to become 3.3V only devices, in which
case, the VGAs would not work. There is always the solution of a DC-DC converter,
from 3.3V to 5V, but this would introduce current wastage and noise, in a system with
already limited available current to operate. Therefore, a more straightforward,
operational amplifier solution was adopted, as shown in Figure 10.
Figure 10: Voltage Gain using Operational Amplifiers
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
2.2.2
Page 15
Digital to Analog Converters (D/A)
The need for implementing a dual channel D/A converter on the baseband card was
trigered by the work of RESIT/AIT on Electronically Steerable Passive Antenna
Radiator (ESPAR) antennae. The idea behind ESPAR antennae is that one can control
the lobe of our antennae electronically and therefore “steer” the antenna towards the
required basestation as the mobile station moves. The steering is not physical (i.e.
adjusting the azimuth and elevation), but electronic (increasing the sensitivity of the
antenna towards some direction). The requirements imposed on the D/A converters
were similar to the ones for the A/D converters regarding sampling rate and
resolution, but only 2 channels were required. This prompted the selection of the
AD9767 from Analog Devices which is a dual 14-bit converter with a maximum
sampling rate of 125MSPS. Figure 11 shows the AD9767 footprint.
Figure 11: AD9767 D/A Converter footprint
In Figure 12, one can observe the connection of the two digital channels of the D/A
converter, to the “outside world”. Notice that the AD9767, is a current output converter,
with a full scale current drive capability of 20 mA. A 50 Ohm resistor and a 10pF
capacitor were employed according to the manufacturer’s recommendations for providing
a 2 V ptp analog output. An RF transformer such as the Mini-Circuits® T1-1T provides
excellent common-mode distortion rejection (i.e. even-order harmonics), as well as noise
reduction over a wide frequency range. For proper source termination, in cases where the
output of the transformer is connected to the load via a passive reconstruction filter, or
cable, an optional resistor is connected across the two current outputs (see also Figure
13).
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 16
Figure 12: Connecting the D/A Converter
Figure 13: Optional resistor when the load is directly connecter to the
transformer
2.3 Boot ROM
Due to the wide range of FPGAs that the compact flash card will be able to
accommodate, the boot ROM size, should be enough to contain code for the largest one,
namely the LX60. In Table 5, one can see all the FPGAs that will be compatible with the
compact flash PCB (circled in red) as well as the corresponding ROM required to
program each one of them. The smallest memory capable of programming the full range
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 17
of devices that the card will support is the XCF32P. This device can support up to 32Mbit
files, whereas the LX60 requires an almost 17Mbit configuration file.
Table 5: Boot ROM compatibilities and sizes
The circuit for programming the FPGA using either a standard JTAG port, or the
XCF32P ROM is shown in Figure 14 with LED for device programming and operation.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 18
Figure 14: Programming using JTAG port
A JTAG download cable, such as the Parallel cable IV, can be used to program the boot
memory a maximum of 20,000 times without having to remove it from the PCB which
gives great flexibility for subsequent standalone operation.
2.4 External RAM
In order to access more memory than the amount already embedded on the FPGA, some
external RAM chip was required. This is a static RAM from Samsung and it can be
arranged as 512K by 36-bits, or 1M by 18-bits or 2M by 9-bits. In Figure 15, we show
the circuit for interfacing with the Samsung K7R160982B QDR-II RAM chip which is
2,097,152 words by 9-bits.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 19
Figure 15: Interfacing with external RAM
The Samsung RAM chip comes in a space saving 165-ball FBGA package, having
dimensions of 13mm by 15mm and a 1mm pitch as shown in more detail in Figure 16. It
is evident, that to meet the very stringent requirements with respect to PCB area
utilisation, some more non-standard packages had to be found even for RAM chips,
which in a larger card could be much bigger in size.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 20
Figure 16: SRAM package dimensions
2.5 Interfacing with Wireless LAN
A number of different system topologies were proposed as shown in Figure 17. This was
due to marketing conclusions and results from the antennas and propagation studies which
led to a few changes in the hardware partitioning of the RESOLUTION system. These
changes were summarized in the half-year report on page 20 and are reproduced here. The
four basic hardware components are the mobile unit for both applications (“A”, an FDD
system), the HPLS receiver, or basestation (“B”), the low-cost TDD alternative to “A” for
smart guiding applications (“C”), which will be considered later, and the commercially
available WLAN access points “D”, to be procured for this project. The proposed compact
flash implementation can encompass all these different applications through software
updates. The radar will be able to either utilise an external WLAN module for
communications, or take advantage of the built-in wireless LAN radio that most modern
PDAs and laptops already possess. More details on how this is done are shown in the next
paragraphs.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 21
A
B
C
D
Figure 17: Interfacing with the Wireless LAN
Depending on whether the mobile station has a built-in WLAN radio or not, a different
architecture can be envisaged. Such an open reconfigurable design should call for the
integration of a WLAN module with the radar, or the use of the client’s embedded
WLAN module if available. Hence, an SDIO slot (see Figure 18) will be incorporated in
the compact flash card, where an 802.11 type WLAN system can be connected. As
wireless LAN standards evolve at a very rapid pace, it was thought that integrating a
WLAN ASIC at the PCB level would not prove future-proof. However, integrating a
complete SDIO WLAN module to the system, would allow us to use the most current
technology, without committing the end-user to a certain standard (e.g. 802.11g) as newer
(e.g. 802.11n etc) are continuously being developed.
Figure 18: Socket for connecting SDIO cards
For a selection of SDIO 802.11 wireless LAN cards available in the market, please see
Figure 19. As newer WLAN standards evolve, newer such cards will become available,
making the RESOLUTION PCB future-proof. Alternatively, the system will be able to
utilise the PDA’s (or laptop’s) built-in WLAN module (if available), through software to
exchange content with the WLAN basestation. The general idea is that the FPGA will
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 22
calculate the distances to each of the basestations and then, depending on the application
and cost (cheaper or more expensive FPGA and peripherals), will perform the
triangulation to extract the x,y,z coordinates of the mobile station. Alternatively, the
triangulation will be done in software (e.g. PDA application) to off-load the FPGA of
having to solve systems of linear equations. After having extracted the coordinates, we
can request through the WLAN a webpage of the form:
http://x_y_z
where the basestation will recognise the x,y,z coordinates and fetch the required webpage
pertaining to these coordinates (e.g. the picture of a museum exhibit at coordinates x,y,z).
Figure 19: A selection of SDIO 802.11 WLAN cards
Integrating the SDIO socket into the PCB design is shown in Figure 20.
Figure 20: Connecting the SDIO socket to the FPGA
2.6 Interfacing with the Analog Front-End
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 23
The FPGA will need to interface with the analog front-end (LNA, mixer etc) through an
analog connection feeding the input(s) to the A/Ds, as well as a series of control
signals as shown in Figure 21. For this purpose a total of 40 general purpose I/O pins
were reserved in the FPGA and are going to be routed to an expansion header.
Figure 21: Control signals to the analog front-end
To make sure that the track lines from the FPGA to the header were as short as
possible to facilitate the routing and to have enough pins in both 1.8V and 3.3V levels,
it was decided to have the following arrangement:
20 I/O pins at 1.8V in BANK7
20 I/O pins at 3.3V in BANK8
Different banks were configured for different voltage levels, making sure that BANK9
and BANK10 are not used to ensure pin compatibility with smaller devices of the same
package, such as FX12. The bank layout of the FF668 package is shown in Figure 22.
Figure 22: FPGA bank layout
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 24
For more details on the expansion header pin locations, please consult the
corresponding BANK7 and BANK8 schematics, found in APPENDIX I.
For the most demanding AGV application, the interconnection between the
RESOLUTION RF chip and the FPGA card, will look like that of Figure 23, where the
FPGA, through the control lines mentioned earlier, will configure the RF chip.
RESOLUTION RF-CHIP
FPGA
mixer
switch
AGC
FPGA
control
switch
LNA
ADC
Synthesizer
passive
loop filter
PA
FPGA
control
FPGA
control
VCO
CP
FFT/ Signal-processing
hardware-control/
timing/
Interface
HPLS protocol
PD
control
Synthesizer division control
MMD
MASH 1-1-1
DS-Modulator
BGR
regulator
WLAN
Frontend &
baseband
diplexer
Interface
TCXO
802.11
PHY-MAC
WLAN
HPLS
PC
PC /PDA
Figure 23: Frontend Architecture for AGV mobile stations
The architecture for smart guiding applications may be the same as that for AGVs if a CF
interface is available on a PDA that lacks WLAN connectivity and radiolocation
capabilities.
If a CF interface is available and the PDA does already host WLAN connectivity, the radar
hardware is that of Figure 23.
ALPR reflector
Forb.systems
with SDIO only, or when power constraints are severe, radiolocation will be
done with the power-saving active reflector according to Figure 24.
Pulse
requency
+
Amp
Δ
Figure 24: Frontend architecture for smart guiding mobile stations
The equivalent radiolocation hardware for mobile stations is shown in Figure 25.
One can easily observe that the scalability, reconfigurability and abundance of FPGA to
analog control lines in the PCB design, allow for the implementation of all the above layouts
in the same hardware.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 25
RESOLUTION RF-CHIP
FPGA
mixer
switch
AGC
FPGA
control
switch
LNA
ADC
Synthesizer
passive
loop filter
PA
FPGA
control
FPGA
control
VCO
CP
FFT/ Signal-processing
hardware-control/
timing/
Interface
HPLS protocol
PD
control
Synthesizer division control
MMD
MASH 1-1-1
DS-Modulator
BGR
regulator
PC /PDA
TCXO
Figure 25: Radiolocation hardware for fixed receiver units
3 Test Setup
In order to have a working real-time prototype, even with limited functionality, a testbench
had to be created using some of the modules presented so far. These off-the-shelf modules,
with some modifications and tuning, would be connected to a prototyping board for realtime algorithm testing and optimisation.
3.1 The Prototyping Board
The prototyping board used to interface all the necessary components is the Flite ETS7000 Analogue and Digital Lab shown in Figure 26. It contains a number of useful features
in a space-saving implementation. These features include:
(1) +5V power supply at 1A
(2) -5V power supply at 300mA
(3) Variable 0V to 15V and 0V to -15V power supplies at 500mA each
(4) Eight toggle switches
(5) Two debounced push-buttons
(6) Eight LEDs
(7) Two seven-segment displays (with Binary Coded Decimal inputs)
(8) Speaker
(9) Large Breadboard prototyping area
(10) Function generator from 1Hz to 100kHz producing sine, triangular and square wave
outputs
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 26
Figure 26: Prototyping board with its main features
After having developed part of the time-critical algorithm subsystems in VHDL, it was
time to test their functionality as a complete system with live data from the A/D
converter. The interested reader can refer to the WorkPackage 5, 4th Quarterly Report
(WP5Q4) for a description of the underlying algorithms. In a nutshell, one is performing
an FFT type operation on an input sinewave (coming through the A/D) and by accurately
detecting the frequency of the sinewave (using interpolations etc), can convert that
frequency into distance between the transmitter (basestation) and the receiver (mobile
station).
The quadratic interpolation used for obtaining a better estimate of the FFT peak location,
requires a multi-bit division operation as explained in WP5Q4. The accuracy of this
division can be controlled by the user (using VHDL generics) and at the moment is 70bits long with a 60-bit integer part and a 10-bit fractional part. The integer part will be
identical to the location detected from the FFT peak detector (e.g. FFT frequency bin),
whereas the fractional part will provide a correction on the actual frequency (and hence
distance to the basestation) giving the actual position between two adjacent bins. So as
the FFT alone can detect peaks between integer frequency bins (e.g. from 55 to 56), the
interpolation with its 10 bit fractional part can produce accuracy of 0.5^10=0.000976.
Hence, there is a much greater resolution in displaying peaks in between two integer bins.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 27
Using the two seven-segment displays (eight bits) for the integer part and the eight LEDs
for the fractional part, one can display the peak location detected in real time as the
frequency of the input sinewave to the A/D is varied from the function generator.
Therefore, very small changes in the input frequency will at least alter some of the
fractional bits giving rise to a very accurate frequency detection. The preliminary realtime setup for testing the VHDL code (detecting sinewaves using FFT and improving on
the estimate using quadratic interpolation) is shown in Figure 27. In this setup, one can
see the A/D converter, FPGA board, prototyping board, JTAG download cable etc.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 28
Figure 27: Real-time prototype
The prototyping board, provides all the power lines to the A/D converter card (mainly 3V)
as well as the sampling clock (shown in the top-left part of the white prototyping area). A
variable frequency sinewave from the proto-board is fed to the analog input of the A/D
and its digital output bits are fed through a flat cable to the FPGA board. The FPGA board,
runs the VHDL code accurately detecting the position (frequency) of the sinewave
(through FFT, peak extraction and quadratic interpolation) and then through another flat
cable goes to the top of the proto-board where it is subsequently routed to the sevensegment displays and LEDs. Hence as the sinewave frequency is being swept, the sevensegment (coarse) and LEDs (fine) readings are updated.
3.2 The Analog Front-end
To interface with a number of analog channels and provide adaptive antenna combining with
the FPGA evaluation board, a system whose general operating principle is shown in Figure
28 was designed. This frontend board operates with an external 5.8GHz synthesizer and
provides four digitized IF signals to the FPGA. Beam steering will be possible in RX direction
only. Combining and phase shifting of the four signals will be done in the digital domain by
the FPGA.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
IF-amp
LNA
Page 29
14-bit
ADC
IF-amp
LNA
Antenna
port
LNA
14-bit
ADC
IF-amp
PA
LNA
IF-amp
PA
FPGA
14-bit
ADC
14-bit
ADC
Virtex 4
Eval board
PA
PA
Multichannel frontend board
VCO board
Figure 28: 4-channel frontend board principle
Special care was taken regarding the number of available I/O pins of the Virtex-4
ML401/2/3 evaluation board. A VCO board (comprising a Direct Digital Synthesizer and a
PLL) is developed in parallel. This VCO board will also be controlled by the FPGA and feeds a
5.8 GHz CW, FMCW or FSK signal into the LO ports of the multichannel board. By control of
the RF switch, the FPGA has the possibility to select between TX and RX mode. The board
schematic is shown in Figure 29.
Figure 29: Multi-channel frontend board schematic
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 30
In Figure 30 the PCB board layout is shown with the four antenna ports, the LO port and the
sockets to the FPGA board. The auxiliary socket pins are connected to unused FPGA I/Os.
LO/VCO in
Port
Connector to VCO-board
Sockets to Virtex4 board
Antenna
Port 1
Antenna
Port 2
Antenna
Port 3
Antenna
Port 4
Auxilary socket
Figure 30: Multichannel board PCB
4 Implementation
Instead of developing two lines of hardware, one for PDAs (e.g. museums, hospitals etc) and one
for laptops (e.g. AGVs), it was thought that a single reconfigurable hardware platform could fit
both scenarios. The same compact flash card with a smaller FPGA could fit the PDA
applications, while the same card with a bigger FPGA in the same package could be used in a
laptop, using a PC-Card adaptor as discussed in Figure 2.
Putting all the board subsystems together, namely A/D converter, FPGA, compact flash, RAM,
ROM, D/A converter and SD looks something like Figure 31. One can notice the 6 analog
connectors feeding the A/D converter, the 2 analog outputs from the D/A converter, as well as
most connections between the card’s subsystems.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 31
Figure 31: Top-level hierarchical schematic
For a more analytic description of the FPGA pinout, the interested reader can refer to
APPENDIX I where all the FPGA banks and their peripheral connections are shown.
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 32
5 Conclusions
This report outlined the design of a printed circuit board, able to accommodate 6 analog input
channels and 2 analog output channels. It can be configured as anything from a cheap and simple
standard compact flash PDA card, utilising the power of the mobile station’s user interface, up to
a full blown (and more expensive) platform for operation in a laptop. The integration of a
WLAN radio can be done either in software, using a built-in module or by interfacing to a
WLAN SD card available in the market to make the whole approach more future-proof.
Interfacing with a four-channel analog frontend was also carried out. The whole design was
based in prototyping the VHDL code using off-the-shelf components to assess the system
complexity and pinout requirements. The scalability of the design ensures that even if additional
functionality is required in the future, it can be met by employing a larger compatible FPGA.
6 References
[1] RESOLUTION Project, Deliverable D2
[2] RESOLUTION Project, Deliverable D3
[3] RESOLUTION Project, Deliverable D4
[4] Xilinx Virtex-4 User Guide (http://direct.xilinx.com/bvdocs/userguides/ug070.pdf)
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 33
7 APPENDIX I: FPGA Schematics
Figure 32: RAM, D/A and SD connections
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 34
Figure 33: CF, A/D connections and 1.8V expansion header
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 35
Figure 34: JTAG, grounds and power pins
RESOLUTION
3/7/2016
D8 – Assembling of ASIC and FPGAs on BB Board
Page 36
Figure 35: 3.3V expansion header
RESOLUTION
3/7/2016