Laboratory 2:
Amplitude Modulation (AM) Implementation
I. Introduction
In the present project, students are required to implement and simulate a simple
amplitude modulated (AM) circuit in the Simulink environment (DSPBuilder), using two
methodologies to build the cos() function: a hard-coded look-up table and the NumericalControlled Oscillator (NCO) Altera IP core. The design has to be downloaded to the
FPGA device on the Stratix II EP2S60 DSP development board to perform hardware
simulation and verification.
II. Theory
Amplitude Modulation or AM involves the encoding of a carrier signal by variation of its
amplitude in accordance with an input signal.
In Amplitude Modulation (AM) the carrier signal cos(c n) is modulated by an input
signal x(n) (which typically has at least 10 times lower frequency than the carrier
signal), as follows:
y(n)  cos(c n) x(n)
(1)
where  c is the carrier angular frequency with 0  c   .
Some efficient approaches for the computation of the cos() function are:



To use a hard-coded look-up table for the cos() function, where the index of the
table is the input of the function and the values inside the table are the possible
outputs
To use an external oscillator (digital or analog)
To use a simple recursive approach for the computation of the cos() function, for
example with the form yn  cos(c n) yn  1  yn  2 (digital oscillator).
In the present project, we will use the first two approaches to implement the cosine
function. For the second method, the NCO IP core from Altera will be used to generate
the required carrier signal.
III. Background about DSP Builder and the Altera EP2S60 DSP development board
Capabilities of DSP Builder and Simulink were introduced with an example design in the
Tutorial: “A/D and D/A Conversion on Altera Stratix II EP2S60 Development Board
using Simulink and DSP Builder” [1], which contain a design targeting the 12-bit
125MHz A/D and 14-bit 165 MHz D/A converters onboard. For further information
about the Stratix II EP2S60 DSP development board, the student is referred to [2],[3] and
[4].
IP cores are megafunctions that are already tested and optimized for specific platforms, in
this case, Altera FPGAs. They avoid building functions from scratch, reducing design
and test time. In the laboratory, we have several evaluation-version IP cores. They can be
parameterized, simulated and downloaded to hardware. For more information about
Altera IP cores, the student is referred to [5],[6]. In the present lab, students will
implement the required cos() function using the Numerically Controlled Oscillator
(NCO) IP core v6.1.
NOTE: previous IP core versions are not guaranteed to work with the installed Matlab
and Quartus II versions.
IV. Requirements
For this laboratory, students are required to accomplish the next requirements:

Implement an AM circuit by applying Equation (1) from Section II. The cosine
function must be implemented using a hard-coded look-up table, where the index
of the table is the input of the function and the values inside the table are the
possible outputs.
The input signal must be acquired through the A/D converter onboard, and then
multiplied with the generated cosine function. The resultant modulated signal
must be converted back to analog through the D/A converter. You can use the
design given in the Tutorial [1] as a template. Place SignalTap II nodes at the
output of the AM modulator and at the output of the cosine function to acquire the
modulated and carrier signals, respectively (see Figure 1, Tutorial [1]).

To implement the cosine function use Counter, ROM EAB and Pattern blocks
from the DSPBuilder library, following the same approach given in [7, section
SineWave_Generator] to design the look-up table approach.
Note that a Pattern block is used here to divide the frequency of the on-board
clock, and it supplies the divided frequency to the Counter. For example, if we
assign a value “1000” to the Pattern block, then the output frequency will be
100MHz/4 = 25 MHz; if we assign a value “10000” to the Pattern block, then the
output frequency will be 100MHz/5 = 20 MHz.
The ROM EAB block points to the hex file containing the points of the desired
cosine function. The student must determine the values and required number of
points for the cosine function, and implement the hex file.
Follow the next specifications:
Look-up table cosine function:
Precision:
16 bits
Cosine frequency:
750kHz
On-board clock frequency: 100MHz
Max. number of points in the look-up table:
20
NOTE: the number of points in the look-up table must be chosen to maximize the
approximation to the required cosine frequency.
Some hint for cos( ) function generation:
In the end, the number of points in the look-up table and the 100 MHz clock
division factor (value to be used in the Pattern block) will both be integer values.
The divided clock rate is given by:
divided clock rate = 100 MHz / (clock division factor).
The inverse of that divided clock rate becomes the sample period between
samples of the cosine signal to be generated:
sample period = 1 / divided clock rate = clock division factor / 100 MHz
Finally, the cosine period value is given by the sample period times the number of
points in a cycle of the cosine wave (i.e. the look-up table number of points):
cosine period = sample period * look-up table number of points
and the cosine frequency is just the inverse of the cosine period:
cosine frequency = 1/ cosine period
= 1 / (sample period * look-up table number of points)
= 100 MHz / (clock division factor * look-up table number of points)
From the last equation, we see that the design problem is simply to find integer
values of the "clock division factor" and the "look-up table number of points", so
that the result is close to the target cosine frequency of 750 kHz (under the
constraint that the maximum of points in the lookup table is 20).
Once that "clock division factor" and "look-up table number of points" have been
chosen, then in Matlab you can calculate the look-up table values as
n=0:1:(nb_values-1);
x=cos(2*pi/nb_values*n);
% between -1 and 1
where "nb_values" is the look-up table number of points.
Once the points have been determined, implement the hex file. You can use
Quartus II to do so. However, it is necessary that the points have the appropriate
format. Hex files built by using Quartus II require numbers in unsigned decimal
format. Thus, first convert the values of a cosine function into unsigned fixedpoint decimal values as follows:
values = floor(x* (2^( Var-1)-0.5) ); % -32768 to +32767
q = quantizer('fixed',[Var 0]);
LUT=num2hex(q,values);
LUT=hex2dec(LUT)
% 0 to 65535
where Var =16 contains the number of bits to use, as described in the
specifications, and x is a cosine signal between -1 and 1. These commands first
convert the cosine signal to the scale -32768 to +32767 (same as signed integer
format), then build a 16 bits fixed point quantizer, then the values are converted to
an hexadecimal format, and finally to the required unsigned decimal format.
Afterwards, you can create the hex file in Quartus II with the obtained points.
Open Quartus II, File > New… and select Other Files in the pop-up window.
Select Hexadecimal (Intel-format) File from the list, and click OK. A new
window opens and asks for number of words and word size. Type 16 in the ‘Word
size’ field (following the look-up table specifications), and type the determined
number of points from your previous analysis in the ‘Number of words’ field. A
table is created. Now fill the table with the point values for the cosine function.
Save the file in the same directory where your Simulink design is located, and
close Quartus II.
Finally, specify the recently created hex file in the ROM EAB Block in your
design in Simulink. Double click in the ROM EAB icon, and fill the ‘Input Hex
File’ field with the name of the hex file.

Simulate your circuit in Simulink for different input sinusoidal signals from
20kHz to 5MHz, observing the modulation behavior. Use the Product or
Multiplier block for the modulation, and use the Binary Point Casting block to
adapt the product value to 14 bits:
What happens if the input signal frequency is close to the carrier frequency?
The second part of the project involves the implementation of the cosine function but
this time using the NCO IP core.

Add to your AM circuit an additional cosine function. This new cosine function
must be implemented using the NCO Altera IP core.
From the Megacore Functions in the Altera DSPBuilder library, drag and place
into your design the nco_v6_1 block. Double click the block to visualize the NCO
Compiler v6.1. A menu with several options is available. If you click on
Documentation, a pop-up window will appear with information concerning to the
IP core. The student is encouraged to review the NCO User Guide v6.1.
To parameterize the IP core, click on the ‘Step1: Parameterize’ button in the NCO
Compiler window. The student will select the required options to achieve the
next specifications:
Architecture:
Accumulator precision:
Angular precision:
Cosine magnitude:
Cosine frequency:
Sampling frequency:
multiplier-based using the multipliers embedded in
the FPGA.
32 bits
13 bits
16 bits
750kHz
100MHz
Apply Phase Dithering to have a minimum attenuation of 90dB. What is the
required dither level to achieve so?
How many FPGA resources are estimated to be consumed by the NCO?
Once parameterized, click on Finish, and click the ‘Step2: Generate’ button in the
NCO Compiler to compile and generate the IP core. Once done, the NCO block
updates automatically, and is ready to interconnect to your circuit. The following
figure is from a design with NCO, take reference on how to make connections for
it:

Place a SignalTap II node at the output of the NCO to acquire the carrier signal
during hardware tests later.

Simulate your circuit in Simulink using the NCO as cosine generator with
different input sinusoidal signals from 20 kHz to 5MHz, observing the modulation
behavior.

You final design must permit the user to select in real-time which cosine
generator is going to use at a time: the look-up table based or the NCO-based
method. To do so, use one of the push-buttons provided onboard.

Download your design to the Stratix II EP2S60 DSP development board and test
it by using a signal generator and oscilloscope. Observe the effect of the
modulation with sine waves from 20kHz to 5MHz. What range of frequencies
works appropriately with the AM circuit?
NOTE: because of the IP core, the Signal Compiler will call the Quartus II
Programmer during programming. The next message will appear, specifying that
once the programmer is disconnected the FPGA will be erased:
Click OK, and then program the device through the next screen:
Check the box below the column ‘Program/Configure’, and click the ‘Start’
button on the left to download the program to the FPGA. The next window will
appear:
Your program will run onboard until you click on Cancel and close the Quartus II
Programmer window, or until you disconnect the PC from the board (because of a
restriction with the current IPcore version available in the lab, if the connection is
terminated, the IPcore software is deleted from the FGPA).

While the program is running onboard, capture and analyze the data using
SignalTap II Analysis. Also, using the data acquired through SignalTap II, show
the frequency content for several input signals in the range from 20kHz to 5MHz.
NOTE: you can use similar commands to those given in the Tutorial [1],
“Importing the data acquired from the board in Matlab workspace”, step2.
What differences can be found between the approach using NCO with multipliers
and the look-up table? Make a list with at least 3 reasons to justify why one of the
approaches is superior to the other in your design.
V. Submission
You must submit:
 The Simulink model (.mdl) developed using DSP Builder blocks with two
approaches to implement the cosine function: hard-coded look-up table and
multiplier-based NCO.
 A report describing the general procedure to accomplish the project
requirements, and answering questions regarding modulation techniques. The
report must contain graphs showing the modulated and carrier signals, and
frequency content for different inputs.
VI. References
[1] Tutorial: “A/D and D/A Conversion on Altera Stratix II EP2S60 Development Board
using Simulink and DSP Builder”.
[2] DSP Builder User Guide, ver. 5.1.0,
c:\altera\61\DSPBuilder\Doc\ug_dspbuilder.pdf
Altera,
2005.
Local
copy
at:
[3] Stratix II EP2S60 DSP Development Board Data Sheet, Altera. Available online at:
www.altera.com/literature/ds/ds_stratixII_dsp_dev_board.pdf
[4] DSP Development Kit Stratix II Edition (Getting Started User Guide), 1.1.0. v.,
Altera, 2005. Available online at:
www.altera.com/literature/ug/ug_stratixII_dsp_dev_kit.pdf
[5] IP MegaStore, Altera. Available online at: http://www.altera.com/products/ip/ipmindex.html
[6] "Intellectual Property (IP)", Altera. Available online at:
http://www.altera.com/products/ip/ipm-index.html
[7] Sample design "SignalTap II Filtering Lab with DAC to ADC Loopback". A local
copy is available at:
C:\altera\61\DSPBuilder\DesignExamples\Demos\Filters\FilteringLab\Stap\
StFilteringLab.mdl. This sample design is referred to on page A-8 of the manual "DSP
Builder Reference Manual" available online at:
http://www.altera.com/literature/manual/mnl_dsp_builder.pdf
and with a local copy at: c:\altera\61\DSPBuilder\Doc\mnl_dspbuilder.pdf