Guide to Operating Systems 4th edition
Chapter 3
Operating System Hardware Components
At a Glance
Instructor’s Manual Table of Contents

Overview

Objectives

Teaching Tips

Quick Quizzes

Class Discussion Topics

Additional Projects

Additional Resources

Key Terms
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Lecture Notes
Overview
This chapter teaches students about various CPU designs and details some popular CPU types
across different brands. It will also explain typical hardware specifications with processors that
affect OS choice and performance.
Objectives

Explain operating system hardware components, which will include design type, speed,
cache, address bus, data bus, control bus, and CPU scheduling

Describe the basic features and system architecture of popular PC processors

Understand how hardware components interact with operating systems
Teaching Tips
Understanding CPUs
1. Describe the CPU, and its role in determining hardware requirements. CPU choice is
often dependent on architecture.
2. Discuss the hardware elements by which a CPU can be classified:
a. Design type
b. Speed
c. Cache
d. Address Bus
e. Data bus
f. Control bus
g. CPU scheduling
Design Type
1. Explain to students the two different kinds of CPU designs:
a. Complex Instruction Set Computing
b. Reduced Instruction Set Computing
2. Define what an instruction set is, and how it changes under CISC or RISC.
3. Students should be aware of the differences between how CISC and RISC processors
process data. They should be able to understand the advantages and disadvantages of
either design.
4. Discuss the Explicitly Parallel Instruction Computing (EPIC) design, and explain what
it can do for RISC based processors. Students should be aware that the Intel Itanium
processor makes use of the EPIC design.
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Teaching
Tip
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Many believed that RISC was the future of computing, and in many ways, they
were right. The use of mobile devices (Android, iPhone, iPad) using RISC basedARM processors has risen considerably.
Speed
1. Explore how the speed of a CPU is measured, such as by internal clock speed. The
concept of a tick should be discussed as well, and how those ticks translate into clock
speed.
2. Explain how external clock speed dictates the communication with the rest of the
computer and its hardware.
Cache
1. Explain the need for cache as a means for a CPU to quickly pull information without
having to rely on memory (which is slower).
2. List the different levels of cache and their locations:
a. Level 1 (L1) cache
b. Level 2 (L2) cache
c. Level 3 (L3) cache
3. Students should be made aware of the cache controller, which predicts the data needed
by a CPU at any given moment, and makes attempts to retrieve it ahead of time.
Address Bus
1. Explain the address bus as communication pathway used for reading and writing to
memory.
a. Typically runs at the external clock speed of the CPU
Data Bus
1. Explain to students that the data bus is a pathway for computer components to share
information between each other, such as between a CPU and display adapter.
2. 64-bit processors can make use of a 64-bit data bus, but only with an operating system
that supports 64-bit.
Control Bus
1. Discuss the information carried by the control bus, which is used to keep the CPU
informed of device status and resources connected to the computer. IRQs should be
defined and explained as well, as the control bus transports this information as well.
CPU Scheduling
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1. Give students an idea of how early operating systems handled scheduling processes, and
explain how threads of execution worked prior to multi-threaded applications and
processors.
Quick Quiz 1
1. Select the technique below that allows a RISC CPU to operate on an instruction while
fetching additional instructions.
a. Threading
b. Pipelining
c. Multithreading
d. EPIC
Answer: B
2. A CISC based processor can do five multiplications in 1 tick, whereas a RISC-based
EPIC processor would need at least 20 ticks.
a. True
b. False
Answer: B
3. ______ describes the clock speed at which the CPU operates within itself.
a. External tick speed
b. Internal tick speed
c. External clock speed
d. Internal clock speed
Answer: D
4. A ______ predicts what data will be needed, and makes it available before it is needed.
Answer: cache controller
5. A 64-bit data bus does not require a 64-bit compatible operating system to make full use
of the data path.
a. True
b. False
Answer: B
Popular PC Processors
Intel
1. Give a brief history of the Intel processor line, beginning with the 8088. List some of
the more important achievements across this line, such as the Multimedia Extension
(MMX) feature or hyper-threading (the ability to make one processor look like two)
feature.
2. Special detail should be given to the more popular processors commonly seen on Intel
platforms, such as the Pentium 4 line. Students might also be interested in the Pentium
D, Intel’s first consumer line dual core processor.
3. Explain the Itanium architecture as a RISC based EPIC processor designed to be 64-bit
capable. Itanium should be described as a processor made for large environments,
running under certain conditions.
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4. The Xeon line should be discussed as Intel’s main server line of processors, designed to
meet the needs of organizations of all sizes. It is important to note that Xeons are
largely the same processors available to consumers under different names, but with
special features enabled for server environments, or with specifications tweaked to be
more suited to servers.
5. The Intel Core 2 Duo / Quad processors should be noted as a significant departure from
previous lines. The introduction of the Core Duo was a considerable improvement in
performance over previous generations of processors.
6. The Core i* processors, Intel’s newest line, are of special interest as they provide even
more speed enhancements over the Core Duo line.
Teaching
Tip
The Core i processors are the first Intel processors to abandon the traditional
Front Side Bus (FSB) design for a more efficient design, called Quick Path
Interconnect (QPI). As such, the numbers used to measure bus speed are not in
MHz, but in GT/s (Gigatransfers per second).
AMD
1. Discuss the history of the AMD processor line and list some Intel comparisons for each
processor.
2. Pay special attention to the more popular and recent AMD processors, such as the
Athlon XP (competing with the Pentium 4) and the Phenom / Phenom II (competing
with Intel Core 2)
Teaching
Tip
AMD eliminated the FSB before Intel did, and early processors such as the
Athlon 64 used what AMD calls HyperTransport to replace it.
Other Processors
1. Discuss Motorola’s CPU options and where they were commonly found (older
Macintosh computers).
2. PowerPC should be mentioned as the former main processor type of more recent Apple
machines.
3. Discuss the SPARC processor, created by Sun Microsystems.
4. Explain the Alpha processor, originally designed by Digital Equipment Corporation
(DEC), and discuss where it could most commonly be found.
Quick Quiz 2
1. Intel Itanium and Itanium 2 processors are built on the RISC-based architecture.
a. True
b. False
Answer: A
2. Which AMD processor line competes with Intel’s Xeon line?
a. Athlon XP
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b. Phenom
c. Opteron
d. Duron
Answer: C
3. The ______ was the first Intel CPU to have a 16-bit data path.
Answer: 8086
4. The Pentium Pro added the _____________ instructions to aid with handling
multimedia and large amounts of data.
a. Threading
b. Streaming SIMD
c. Hyper-threading
d. Multimedia Extension
Answer: D
5. The first Intel processor to make hyper-threading available to consumers was the
_________
a. Pentium
b. Pentium II
c. Pentium III
d. Pentium 4
Answer: D
Class Discussion Topics
1. Get students to discuss the more common processors they’ve seen. Quite a few people
will have seen the Pentium 4 processor despite its age, simply because it was a very
popular processor.
2. Suggest that students discuss where CISC vs RISC processors might be used, and come
up with environments where one processor would outperform the other.
Additional Projects
1. Have students research other means for measuring processor speed rather than just
clock speed. Some measurements aren’t even valid measurements, such as the ones that
the Linux kernel makes, called Bogomips (bogus + MIPS).
2. Students should research more RISC based devices that they most likely use, and don’t
realize are RISC based.
Additional Resources
1. http://www.intel.com/technology/quickpath/
2. http://www.hypertransport.org/default.cfm?page=technology
3. http://en.wikipedia.org/wiki/RISC#RISC_success_stories
Key Terms
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address bus An internal communications pathway inside a computer that specifies the source and target
address for memory reads and writes. The address bus is measured by the number of bits of information it
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can carry. The wider the address bus (the more bits it moves at a time), the more memory available to the
computer that uses it.
backward compatibility A significant number of features from an older chip can function on a newer
chip.
bus A path or channel between a computer’s CPU and the devices it manages, such as memory and disk
storage.
cache controller Internal computer hardware that manages the data going into and loaded from the
computer’s cache memory.
cache memory Special computer memory that temporarily stores data used by the CPU. Cache memory
is physically close to the CPU, and is faster than standard system memory, enabling faster retrieval and
processing time.
Complex Instruction Set Computing (CISC) A computer CPU architecture in which processor
components are reconfigured to conduct different operations as required. Such computer designs require
any instructions and more complex instructions than other designs. Compare to Reduced Instruction Set
Computing (RISC).
control bus An internal communications pathway that keeps the CPU informed of the status of particular
computer resources and devices, such as memory and disk drives.
core The part of a processor used to read and execute instructions.
data bus An internal communications pathway that allows computer components, such as the CPU,
display adapter, and main memory, to share information. Early personal computers used an 8-bit data bus.
More modern computers use 32- or 64-bit data buses.
 execution-based cache First-level cache in a XEON CPU that stores decoded
instructions and delivers them to the processor at high speed.
 Explicitly Parallel Instruction Computing (EPIC) A computer CPU architecture that
grew out of the RISC-based architecture, and enables the processor to work faster by
performing several operations at once, predicting and speculating about operations that
will come next (so that they are even completed before requested). EPIC uses larger and
more work area registers than CISC or traditional RISC-based CPU architectures. See
Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing
(RISC).
 external clock speed The speed at which the processor communicates with the memory
and other devices in the computer; usually one-fourth to one-half the internal clock
speed.
 hyper-threading (HT) An Intel multithreading technology that enables a single
processor to appear to the operating system as two separate processors, in which
multiple threads of software applications are run simultaneously on one processor.
 instruction set In a computer CPU, the group of commands (instructions) the processor
recognizes. These instructions are used to conduct the operations required of the CPU
by the operating system and application software.
 internal clock speed The speed at which the CPU executes internal commands,
measured in megahertz (millions of clock ticks per second) or gigahertz (billions of
clock ticks per second). Internal clock speeds can be as low as 1 MHz and as high as
more than 3 GHz.
 interrupt request (IRQ) A request to the processor so that a currently operating
process, such as a read from a disk drive, can be interrupted by another process, such as
a write into memory.
 level 1 (L1) cache Cache memory that is part of the CPU hardware. See cache memory.
 level 2 (L2) cache Cache memory that, in most computer CPU designs, is located on
hardware separate from, but close to, the CPU.
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 level 3 (L3) cache Cache memory that is located on a chip, which is separate from, but
close to the CPU, when L1 and L2 cache are both already built into the CPU.
 math coprocessor A module optimized to perform complex math calculations. Early
system architectures have a processor and an optional slot for a math coprocessor.
Modern system architectures have a CPU with one or more built-in math=coprocessors.
 Multimedia Extension (MMX) A CPU design that permits the processor to manage
certain multimedia operations—graphics, for example—faster and more directly. MMX
technology improves computer performance when running software that requires
multimedia operations.
 multiprocessor computer A computer that uses more than one CPU.
 multithreading Running several program processes or parts (threads) at the same time.
 pipelining A CPU design that permits the processor to operate on one instruction at the
same time it is fetching one or more subsequent instructions from the operating system
or application.
 Reduced Instruction Set Computing (RISC) A computer CPU design that dedicates
processor hardware components to certain functions. This design reduces the number
and complexity of required instructions and, in many cases, results in faster
performance than CISC CPUs. Compare to Complex Instruction Set Computing
(CISC).
 single-processor computer A computer capable of supporting only a single CPU.
 Streaming SIMD Extensions Single-instruction, multiple-data stream processing for
enhanced multimedia.
 system architecture The computer hardware design that includes the processor (CPU),
and communication routes between the CPU and the hardware it manages, such as
memory and disk storage.
 word Used to hold data or programming code in a computer. The size of a word varies
among computers. 16-bit computers have a word of 16 bits and a 64-bit computer has a
word of 64 bits.