CST-162 LAB 6 (FALL 2009)
DIGITAL LOGIC CIRCUITS
Introduction to Hardware Design Language (HDL) for
Logic Design with PLDs
I.
OBJECTIVES:
1. Introduction to fundamental concepts of Hardware Design Language (HDL). .
2. Introduction to an adder design
II.
EQUIPMENT and PARTS:
None
III.
INTRODUCTION:
In the previous laboratory, we had used Schematic Capture. Now, the powerful concept of designing by
coding using a Hardware Design Language (HDL) is introduced. The language is ABEL here; however, the
student need not worry about learning ABEL at all. The program is given so it can be entered directly without
any knowledge of ABEL. The HDL that will be taught later on will be Verilog in the next lab. ABEL is used
here only to show that there are several HDL’s. The student will see that she/he no longer need to drag gates
onto a “sheet” at all but rather simply write a few instructions (program) and have the tool do the rest of the
work. Of course, knowledge of the design is still required to write the code and test to see if the result of your
code indeed satisfies the design specifications. In this lab, we’ll design an adder that will add two 4-bit
numbers.
Asides from using HDL, the students will be introduced to how a PLD is incorporated into logic design.
In this lab, the design will be for a PLD. Details of this PLD will be given in class lectures.
NOTE: the following section is a basic development and introduction provided for those who want to
explore some details of ABEL. It can be skipped. Again, the student is not required to know ABEL. In the
procedure section, the ABEL program is provided so that it can be typed directly in without any knowledge of
ABEL. However, for those with enquiring minds, you can read the rest of this Introduction section. If not,
proceed directly to the procedure section.
The first part of the Lab starts with the design of a One Bit Full Adder (FA) with two Inputs (A1, B1)
and a Carry-In (CIN). These inputs are used to generate a One-Bit Output Sum (SOUT) and a Carry-Out
(COUT) for the addition carry function. The truth table for the one bit adder is given below:
CIN B1
A1
SOUT COUT
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
The equations for the two outputs can be derived using Karnaugh Maps and are given below:
1. SOUT = A1  B1  CIN
2. COUT = (A1  B1) + (A1  CIN) + (CIN  B1)
These two equations can be implemented in either a graphic design file (schematic) or a HDL file. In this Lab
we will design the basic Full Adder using Boolean Equations in an ABEL-HDL File. This Lab will just be a
design and simulate only (no compile or fit)
The next portion of the lab will then expand on the concept of a One Bit FA to a Four Bit Binary Adder.
The classic approach to this would involve cascading 4-Single Bit FA’s together and then design a Look Ahead
Carryout Circuit. This is quite a long and tedious process (but a good design exercise) and can take a good deal
of time. In this Lab we will expand the equations of the FA and just cascade the Carry Out from one stage to
the Carry In of the next (this is a ripple carry).
The Four Bit Adder will be used to add two Four Bit Numbers together (plus a CIN) to produce a Five
Bit Output (Four Bit Sum and a COUT). We could represent each input and output as a single bit variable (AI1,
AI2…BI4) but this is awkward and very time consuming. Instead we shall represent each four bit input as a
Bus [A3..A0] and [B3..B0], then do the same for the Five Bit Output [COUT, S3..S0]. The basic format for the
signal declaration is given below:
[A3..A0]
pin;
[B3..B0]
pin;
CIN
pin;
[S3..S0]
pin istype ‘com’;
COUT
pin istype ‘com’;
[C2..C0]
node istype ‘com’;
A = [A3..A0];
B = [B3..B0];
S = [S3..S0];
Note that in this declaration set we have used an internal Node (NODE ) instead of Pin for the intermediate
carry signals (we do not need an actual output they are fed back internally).
The basic operation to be performed is [COUT, S] = A + B + CIN using a Four Bit Parallel Adder. This
can be implemented with basic Boolean Logic Operators (!, $, &, #) as we had done in earlier labs or we can
use arithmetic operators (+ or -). Both types will require the Pin declarations as shown above but the equation
section will be different. You will find that in most HDL Systems they are numerous ways to implement a
Logic Function. Some will be more efficient than others, for instance a 16 Bit Adder would be easier to
implement with Boolean Equations than a Truth Table (an array of 33 X 17). The first method uses Boolean
Equations such as:
Equations
S0 = A0 $ B0 $ CIN;
C0 = CIN & (A0 $ B0) # (A0 & B0);
S1 = A1 $ B1 $ C0;
C1 = C0 & (A1 $ B1) # (A1 & B1);
And so on for the remaining equations in the ABEL File in Figure 6.2. The other method uses the Arithmetic
Operator + and the Bus Set notation for the signals such as:
Equations
[C0, S0] = [X, A0] + [X, B0] + [0, CIN];
[C1, S1] = [X, A1] + [X, B1] + [0, C0];
and so on for the remaining equations. Note that in each Equation the Sum Terms must be two bits to match the
Output Set Size. When using ABEL you must take care to match bus widths or suffer compile errors.
IV.
HDL (ABEL) DESIGN ENTRY AND COMPILE (4 Bit Adder):
1. Open the Lattice ispLever Classic Tools and Create a Folder called CS162L6 under folder Lab6 in your Z
drive.
2. Create a Project called CS162L6 and give it the Title CS162L6 with Type Schematic/ABEL then set the
Device to GAL20V8B, 10nS and 24PDIP this time.
3. Select SOURCE|NEW and Select ABEL-HDL MODULE. Label the File Name and Module name both
add4bit (remember it must match the module name in the ABEL Text File). Give it the title Lab 6 Four
Bit Adder and click on OK.
4. This should open a Text Edit Window with the Module, Title and End already in the text. Start entering
the Text as shown in Figure 6.1 (at least a few lines)
5. Refer to the ABEL Text file in Figure 6.1 and finish adding the remaining text (the Equations for S3 S0
and C0  COUT). When finished select FILE|SAVE AS and be sure the name is add4bit. This creates
two files (one Text, one for Test Vectors).
6. Click on ADD4BIT.ABL in the Source Window and then Select COMPILE-LOGIC in the Process
Window. Select PROCESS|START and check for any errors.
7. Click on add4bit-vectors in the Sources Window to open new Processes. Double Click on Functional
Simulation to Compile the Vectors and open the Simulator Control Panel.
8. In the Simulator Control Panel select SIMULATE|SETTINGS and change the Step Size to 2000 X
100pS and OK. This sets the duration of each vector to 200nS (default is 100nS). You will be prompted
to restart the simulator engine select Yes.
9. Select SIMULATE|RUN to run the simulator. If a waveform window does not open use VIEW and check
on Waveforms. Does the Output Waveform for the SUM and Carry match the Expected outputs given in
the test vectors (they should)?
10. Close the Simulator Control Panel and Waveform windows.
11. After the functional simulation is complete we need to “compile” and “fit” to generate the JEDEC Fuse
Map we would need to program a device.
12. In the Sources window click on the Device Part Number (GAL20V8B). In the Process Window click on
FIT DESIGN to select it to begin the Compile Process.
13. Select PROCESS|PROPERTIES (or click on Properties Button) to open the Compile/Fit Properties Box.
14. This box is used to create the setup to instruct the Design Tools on how to Reduce and Fit the ABEL
Design to the specific Device Architecture.
15. Check to see that the Properties are set to:
FIT DESIGN = TRUE
DESIGN RED ALGOR = By Pin/Choose
Q-M RED = FALSE
MERGE = FALSE
P TERM LIMIT = 8
(Refer to On-Line Help for Details)
PIN ASSIGN = TRY
NORM DES = TRUE
REMOVE NODES = TRUE
NODE COLLAPSE = ALL
16. Close the Properties Box and Select PROCESS|START to start the Compile and Fit Process. This should
generate four output files. Right Click on Post Fit Equations, then click on View. Print this page and note
the output equations.
17. Double click on the Fitter Report to view the report and use it to correct any errors flagged. View it and
note Pin Numbers Assigned.
18. Now in the Process Box (device is still selected in Source) Select the Create Fuse Map to map the device
equations into the AND/OR SOP Array and generate the JEDEC File that can be used to Program a
Device.
19. Select PROCESS|PROPERTIES to open the Fuse Map Properties Dialog Box.
20. Check to see that the Properties are set as follows:
Output File = Brief
Checksum = Full
Chip Report = Brief
PLCC = False
Blow Unused Fuses = True
Program Turbo Bit = True
Program Miser Bit = True
Program Sec. = False
Values for DC = 0
21. Close the Properties Box to accept the settings. Select PROCESS|START to start the Fuse-Map Process.
This should create two more Files.
22. Double Click on the Chip Report to open it (or Right Click/View) and Print it out. Note the Output
Equations. (Have they changed from the Post Fit Report?)____________
23. Select the JEDEC File and view how the Product terms were used for the four output functions.
24. In the sources box click on add4bit-vectors and then in the Process Box double click on Simulate Jedec
File. This will create a Jedec Simulation File, click on it and view the file. Correct Logic or Vectors if
there are errors. Then click on the JEDEC Simulation Waveform and Select View to open the window.
25. If any signals are visible in this window click on them and use EDIT|HIDE to remove. In the next few
steps you will group the signals as three busses (SUM, AIN, and BIN).
26. Click on EDIT|SHOW and the Click on BUS to open the Show waveforms and Bus dialog box. In the
show window Select Nets S0, S1, S2, and S3 (Click and drag).
27. In the Bus window half select New Bus and enter the bus name SUM and then press Add Nets to transfer
S0 – S3 (they are in reverse order) to the BUS SUM.
28. In the bus signal window select S3 only and press Move Up to move it to the top. Repeat this process for
both S2, S1 and then S0. (or use REVERSE for all).
29. Select SAVE BUS to move SUM to the Net Name Window and then Press SHOW to place it on the
waveform page as a 4 Bit Hex Bus.
30. Select New Bus again and repeat this process for AIN = A0..A3 and then BIN = B0..B3. Remember to
reverse order of signals. (You want the bits to be shown in MSB->LSB order; i.e. 1010b is not the same as
0101b.) Finally, add CIN and COUT as Signals.
31. In the Sources Box of the Navigator select the Simulator File add4bit-vectors. This file will be used to
simulate the JEDEC File. In the Process Box Double Click TIMING SIMULATION. This should open
the Simulator Control Panel.
32. Select SIMULATE|SETTINGS and set for Max Delay and Transport. Then Select SIMULATE|RUN
to run the timing simulation.
33. When complete select VIEW|WAVEFORMS to view the output/input waveforms. Arrange signals as
Busses (Step 25-30). Print Out a copy and Compare these to the Original Simulation Waveforms. Are
there any glitches in the output waveforms?_______________________
FIGURE 6.1 PROGRAM LISTING FOR ADD4BIT
module add4bit
title ‘Lab 6 Four Bit Adder’
// Enter Your Name //
// Enter Course Number, Time and Date //
// Pin Declarations //
a3..a0
pin;
b3..b0
pin ;
cin
pin ;
s3..s0
pin
istype ‘com’;
cout
pin
istype ‘com’;
// declaring an output as combinational functions //
c2..c0
node istype ‘com’;
// declaring internal nodes to be used for staged ripple carry levels //
// Aliasing Signal States //
H, L, X = 1,0, .x. ;
a = [a3..a0];
b = [b3..b0];
s = [s3..s0];
//Logic Design section using Boolean equations //
equations
s0 = a0 $ b0 $ cin;
c0 = cin & (a0 $ b0) # (a0 & b0);
s1 = a1 $ b1 $ c0;
c1 = c0 & (a1 $ b1) # (a1 & b1);
s2 = a2 $ b2 $ c1;
c2 = c1 & (a2 $ b2) # (a2 & b2);
s3 = a3 $ b3 $ c2;
cout = c2 & (a3 $ b3) # (a3 & b3);
//Logic Simulation and Verification Section //
test_vectors([
a,
b, cin ] -> [
s, cout ])
[ ^h01, ^h01, 0 ] -> [ ^h02, 0 ];
[ ^h01, ^h01, 1 ] -> [ ^h03, 0 ];
[ ^h0A, ^h05, 0 ] -> [ ^h0F, 0 ];
[ ^h0A, ^h05, 1 ] -> [ ^h00, 1 ];
[ ^h06, ^h02, 0 ] -> [ ^h08, 0 ];
[ ^h06, ^h02, 1 ] -> [ ^h09, 0 ];
[ ^h07, ^h00, 1 ] -> [ ^h08, 0 ];
[ ^h09, ^h06, 0 ] -> [ ^h0F, 0 ];
[ ^h09, ^h06, 1 ] -> [ ^h00, 1 ];
end
NAME:_______________________
CHECK OFF AND QUESTIONS
CST162, LAB#6
Detach this sheet from the rest of the lab handout. Hand in this sheet plus any supporting material only.
LATTICE SIMULATION:
When completed with the Lattice simulation, have the instructor check your work in Lattice. Be prepared to
answer questions. Have she/he sign below.
SIGNATURE: _____________________________
Now answer the following question:
1. Did you observe any glitches in the 4-Bit Adder Outputs and if so how could the design be improved?
2. Hand in the printed out Chip Report by attaching it to this report, with the other print outs asked for
above.