Digital Logic for Computers
(ACOE161)
Experiment #1
Basic Logic Gates – Pre-Lab Report
Student’s Name:
Reg. no.:
Semester: Spring 2016
Date: 07 March 2016
Assessment:
Assessment Point
Weight
Grade
Methodology and correctness of results
Discussion of results
Participation
Assessment Points’ Grade:
Comments:
© Konstantinos Tatas
Page 1 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
Experiment #1:
Basic Logic Gates
Objectives:
The objectives of this experiment are to:
1. Introduce students in the tools, facilities and components needed for the
experiments in digital electronics,
2. Relate voltage levels and electrical connections to digital logic levels, and
3. Verify the operation of the basic logic gates.
Discussion:
Digital electronics are built using logic gates. Each logic gate implements a logic
function such as the NOT (also known as the inverter), the AND, the OR and the
Exclusive OR (also known as the EX-OR gate). In some cases the output of a gate is
internally inverted. The AND gate with the output inverted is called the NAND gate.
The OR gate with the output inverted is called the NOR gate. The EX-OR gate with
the output inverted is called the EX-NOR gate.
(i)
(ii)
NOT
A
AND
X
A
B
OR
X
(iii)
X=A
X=AB
(iv)
A X
0 1
1 0
A
0
0
1
1
B
0
1
0
1
X
0
0
0
1
EX-OR
A
B
X
X=A+B
A
0
0
1
1
B
0
1
0
1
X
0
1
1
1
A
B
NAND
X
X=A+B
A
0
0
1
1
B
0
1
0
1
X
0
1
1
0
A
B
NOR
X
X=AB
A
0
0
1
1
B
0
1
0
1
X
1
1
1
0
A
B
X
X=A+B
A
0
0
1
1
B
0
1
0
1
X
1
0
0
0
Figure 1. Basic Logic Gates.
Figure 1 shows the basic logic gates. Row (i) shows the name of the gate, row (ii)
shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows
the truth table. A truth table is a table showing all possible values at the inputs of a
digital circuit and the corresponding value of the output.
Procedure:
Use MULTISIM or Electronics Workbench (EWB) to solve the following exercises.
© Konstantinos Tatas
Page 2 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
Exercise 1:
(a) Open MULTISIM or Electronics Workbench (EWB) and place the AND gate
component by clicking on the corresponding gate icon as shown in Figure 2.
Figure 2. Multisim: Placing an AND Gate.
(b) Use the Word Generator and Logic Analyzer instruments to complete Table 1, as
shown in Figure 3.
Figure 3. Word Generator and Logic Analyzer Configuration.
© Konstantinos Tatas
Page 3 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
Table 1. AND Truth Table.
A
B
A AND B
0
0
0
1
1
0
1
1
(c) In MULTISIM or EWB and place the NOT gate component and use the Word
Generator and Logic Analyzer instruments to complete Figure 4 and Table 2.
[Insert Multisim circuit here]
[Insert Multisim logic analyzer screen here]
Figure 4. NOT Gate Circuit and Logic Analyzer Output.
Table 2. NOT Truth Table.
A
NOT A
0
1
© Konstantinos Tatas
Page 4 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
(d) In MULTISIM or EWB and place the OR gate component and use the Word
Generator and Logic Analyzer instruments to complete Figure 5 and Table 3.
[Insert Multisim circuit here]
[Insert Multisim logic analyzer screen here]
Figure 5. OR Gate Circuit and Logic Analyzer Output.
Table 3. OR Truth Table.
A
B
A OR B
© Konstantinos Tatas
0
0
0
1
1
0
1
1
Page 5 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
(e) In MULTISIM or EWB and place the XOR gate component and use the Word
Generator and Logic Analyzer instruments to complete Figure 6 and Table 4.
[Insert Multisim circuit here]
[Insert Multisim logic analyzer screen here]
Figure 6. XOR Gate Circuit and Logic Analyzer Output.
Table 4. XOR Truth Table.
A
B
A XOR B
© Konstantinos Tatas
0
0
0
1
1
0
1
1
Page 6 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
(f) In MULTISIM or EWB and place the NAND gate component and use the Word
Generator and Logic Analyzer instruments to complete Figure 7 and Table 5.
[Insert Multisim circuit here]
[Insert Multisim logic analyzer screen here]
Figure 7. NAND Gate Circuit and Logic Analyzer Output.
Table 5. NAND Truth Table.
A
B
A NAND B
© Konstantinos Tatas
0
0
0
1
1
0
1
1
Page 7 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
(g) In MULTISIM or EWB and place the NOR gate component and use the Word
Generator and Logic Analyzer instruments to complete Figure 8 and Table 6.
[Insert Multisim circuit here]
[Insert Multisim logic analyzer screen here]
Figure 8. NOR Gate Circuit and Logic Analyzer Output.
Table 6. NOR Truth Table.
A
B
A NOR B
© Konstantinos Tatas
0
0
0
1
1
0
1
1
Page 8 of 9
ACOE161:
Digital Logic for Computers – Pre-Lab Report
Experiment # 1
(h) In MULTISIM or EWB and place the XNOR gate component and use the Word
Generator and Logic Analyzer instruments to complete Figure 9 and Table 7.
[Insert Multisim circuit here]
[Insert Multisim logic analyzer screen here]
Figure 9. XNOR Gate Circuit and Logic Analyzer Output.
Table 7. XNOR Truth Table.
A
B
A XNOR B
© Konstantinos Tatas
0
0
0
1
1
0
1
1
Page 9 of 9