EE 446
LABORATORY
MANUAL
EE-446 LABORATORY REGULATIONS ................................................................................................................ 3
EXPERIMENT 1 ...................................................................................................................................................... 4
EXPERIMENT 2 .................................................................................................................................................... 15
EXPERIMENT 3 .................................................................................................................................................... 19
EXPERIMENT 4 .................................................................................................................................................... 36
EXPERIMENT 5 .................................................................................................................................................... 50
EXPERIMENT 6 .................................................................................................................................................... 60
EXPERIMENT 7 .................................................................................................................................................... 65
APPENDIX ............................................................................................................................................................ 76
2
EE-446 LABORATORY REGULATIONS
1. Preliminary work: You will not be admitted to the lab session without a
preliminary work. In case of cheating, the preliminary works of both parties
will be graded by 0. Cheating includes partial plagiarism and cooperation.
Siblings, home/room mates and couples are NOT exempt from this rule.
2. Qualification: Before each lab session, there will be a quiz. To qualify for the
session, you should get at least 5 out of 10. If 3 ≤ quiz grade < 5, you still
will not be admitted to the session, however, will be able to perform the
experiment in make-ups. If your quiz grade is less than 3, your preliminary
work will not be graded.
3. Make-ups:
a. 3 ≤ quiz grade < 5: Only 2 make-ups are granted, i.e., scoring 3 or
more times between 3 and 5 will get you only 2 make-ups.
b. Legal excuse: Legal excuses include medical excuses and concurrent
exams. As long as officially documented, a make-up is guaranteed, no
matter how many times these cases occur. For concurrent exams, one
should bring a signed document from the lecturer of the course, stating
that the student attended the examination. For medical excuses, only
valid document is a medical report prepared by METU Health and
Counseling Center (MEDIKO). Failing to get up on time, whatever the
reason, is not a legal excuse.
4. Experiments will be performed INDIVIDUALLY.
5. Attendence: Students who miss 3 lab sessions without a legal excuse will be
graded by 0 for their laboratory work. Students who miss 4 or more lab
sessions without a legal excuse will be get an FF/FD grade from EE-446.
Missing a lab means failing to take the quiz for any reason, including being
late.
6. Morning session quizzes will start at 9:00, and afternoon session quizzes will
start at 14:00. The duration is usually 10 minutes. No latecomers are allowed
after the end of the quiz.
7. This document supersedes any previous regulations.
3
EXPERIMENT 1
ASYNCHRONOUS SEQUENTIAL CIRCUITS
1. THEORETICAL BACKGROUND
1.1 GENERAL
Asynchronous circuits do not necessitate clock pulses; they are faster and
cheaper than synchronous ones. However the design procedure is more complicated.
Design procedures for asynchronous and synchronous sequential networks are
similar in many respects. The procedure is as follows:
 Convert the word specification of a desired network to a state transition table
which is also known as a primitive flow table.
 Detect and eliminate equivalent states.
 Merge the rows of the primitive flow table. This new step can be used to
minimize the number of states to ultimately be realized or endow the final
network with other desirable properties.
 Encode the state table in such a way not to have critical races. This step
influences the speed of the network at which it operates, as well as its cost.
 Write the excitation equations for the state variables and output equations for
the encoded state transition table.
(a) If a gate network is to be constructed, the excitation and output equations
must be free of hazards.
(b) If asynchronous flip-flops are used for the state variables, then flip-flop
input equations must be derived and made free of certain hazards.
 Use available technology to implement the excitation or flip-flop input
equations and the output variable equations, but avoid reintroducing hazards.
1.2 AN ASYNCHRONOUS SYNCHRONIZER (AS AN EXAMPLE)
a
T
b a c
d
e
f
e
a
b
a
b g
h
i
k
a
c
Fig.1
S
Z
4
A periodic clock signal T is used to synchronize a synchronous system. For
purposes of testing and maintaining that system, a network is required to generate a
single, complete positive portion of T each time a switch S is closed.
Figure 1 illustrates a typical input-output sequence for the derived network.
Note that only one pulse should be emitted even if the switch S is closed for
thousands of periods of T, and that a complete pulse is to be emitted even if S is
closed in the middle of a T pulse.
1.2.1 CONSTRUCTION OF THE PRIMITIVE FLOW TABLE
A primitive flow table is a flow table with only one stable state in each
row. During these steps of the design procedure, it is more convenient to name the
states by letter symbols.
We begin to obtain a state transition table model of a desired network by
specifying a “first stable state”. Here, for example, we might begin by naming as
state a when (S,T)=(0,0). We know that only one output symbol is to accompany
this input symbol. We summarize our specification of a first state in the manner of
Fig. 2.a. The values following the commas denote the output of the system for the
given state and input combinations.
00
ST
01
a,0
a)
11
10
00
ST
01
00
ST
01
a,0
b,-
a,0
b,-
a,-
b,0
a,-
b,0
b)
11
10
11
10
c,-
d,-
c,0
d,1
e,-
a,-
f,-
e,0
a,-
f,0
e,-
c)
Fig.2.
Now we assume that the machine is in this first state and that the input
symbol changes, and ask how the machine is to respond. Suppose ST is changed
from 00 to 01. The machine must attain another stable state. We specify this
transition by placing an uncircled b in the first row and the ST=01 column, and a
circled b in that column and a new, second row. Each new stable state will be
allocated a row in the primitive flow table. Note that if T returns to 0 before S
changes, we may think that the machine returns to state a, since it is not necessary
to “remember” this situation.
To obtain z=1, ST must change from 00 to 10 to 11. The corresponding state
sequence includes state d, as shown in figure 2.c. When T returns to 0, a complete
5
pulse has been emitted and the machine must attain state e rather than returning to
state c. Otherwise, T would eventually be 1 again and if S=1 is maintained the
machine would go to state d and emit another pulse. Such activity would satisfy the
given specifications.
Several other entries may be placed in the primitive flow table. Again suppose
that the machine is in state a, but that S and T simultaneously take the value 1. The
specifications do not say what the machine should do, but indicate that this and all
other double-variable, input symbol changes will never occur. As designers, we gain
freedom by interpreting this specification to mean that the next state is a “don’t
care”. The resulting primitive flow table is illustrated in figure 3.
Don’t care state transitions and output symbols may appear in a primitive flow
table. Such entries require the generalization of the definition of equivalent states,
and procedure for finding them.
1.2.2 REDUCTION OF EQUIVALENT STATES
We will say that two stable states in the same column of a flow table are
equivalent, if:
 Identical output symbols are associated with the states, and
 In every column of the rows of the two stable states
(a) identical or equivalent state names appear, or
(b) two don’t care entries appear.
Note that this definition is recursive. State a is the only stable entry in the first
column of figure 2.c and hence can be equivalent to no other state. In the second
column, states b and k are not equivalent because different output symbols are
associated with them. In the third column, state pairs (d,f), (d,g), (f,i), (g,i) are not
equivalent for the same reason. However, (d,i) and (f,g) cannot be ruled out as
equivalent yet. Examination of the states that follow d and i reveals identical entries
in the first and second columns. In the fourth column, state d is followed by state e,
while state i is followed by state j. If we can show that states e and j are equivalent,
then states d and i are equivalent. We call this situation as “(d,i) implies (e,j)”.
Similarly, the equivalence of f and g implies the equivalence of e and h. States e and
h are not equivalent because states f and i are not. States e and j have the same
output symbol and identical next state entries. Hence, they are equivalent; as a
result d and i are also equivalent. This brings the equivalence of states c and h, as
well. Thus, three pairs of equivalent states (e,j), (d,i), (c,h) exist in the primitive
flow table of figure 3. Figure 4 shows the flow table after the reduction of the
equivalent states. Note that new state names are assigned in this new table.
1.2.3 MERGING OF THE FLOW TABLE
Merging is the process of combining compatible states to reduce the number of
states in the flow table. The procedure that must be followed when merging the flow
table is as follows:
6
 Determine all compatible pairs,
 Find the maximal compatibles using a merger diagram,
 Find a maximal collection of compatibles covering all the states and is closed.
00
ST
01
11
10
a,0
b,-
-,-
c,-
a,-
b,0
g,-
-,-
a,-
-,-
d,-
c,0
-,-
k,-
d,1
e,-
a,-
-,-
f,-
e,0
-,-
b,-
f,0
e,-
-,-
b,-
g,0
h,-
a,-
-,-
i,-
h,0
-,-
k,-
i,1
j,-
a,-
-,-
f,-
j,0
a,-
k,1
d,-
-,-
00
ST
01
11
10
a,0
b,-
-,-
c,-
a,-
b,0
g,-
-,-
a,-
-,-
d,-
c,0
-,-
h,-
d,1
e,-
a,-
-,-
f,-
e,0
-,-
b,-
f,0
e,-
-,-
b,-
g,0
c,-
a,-
h,1
d,-
-,-
Fig.4. Equivalent States have been removed
A pair of rows is said to be
compatible if in each column of the
rows identical or compatible state entries (stable or not, including don’t cares) and
output symbols (whenever specified) appear. Note that, don’t care entries may be
adjusted to fit any condition.
Fig.3. Completed Primitive Flow Table
In our example, from the flow table of figure 4, the rows (a,b), (a,c), (a,g),
(b,g), (c,h), (d,h), (e,f) are directly seen to be compatible, without implying any
other compatible pairs. From a more elaborate analysis, no other candidate pairs
come out to be compatible, since their implied pairs are not.
7
a
Fig.5.
Mergerb Diagram
h
c
g
d
f
e
Having found all the compatible pairs, the next step is to find maximal
compatible sets from the merger diagram of figure 5. For the purposes of more
examples, we shall use the partition
{a,c} , {b,g} , {d,h} , {e,f}
although it is no better or worse than other 4-block partitions. At this point, care
must be taken to ensure that the partition covers all the states, and it is closed.
Here, closure means that there are no implied pairs corresponding to any set of the
partition, or all such implied sets are included within the partition. In our example,
since there are no implied pairs belonging to any compatible pair, we are free to
choose any partition that covers all the states.
To illustrate the closure property, suppose for a moment that the compatibility
of the pair (a,c) depended on (i.e., implied) that of the pair (a,b). In that case, we
would have to include the set {a,b} to our partition in order to preserve the closure
of the partition.
To merge rows of a and c of figure 4, we alter row a to
a,0
b,-
d,-
c,0
Employing the merger partition selected, figure 4 merges to the table of figure
6.a. Figure 6.b shows an equivalent flow table using a more convenient format.
1.2.4 CRITICAL RACE FREE STATE ASSIGNMENT
Merging has eliminated all don’t care state transitions in the example. We now
see that if the machine is in state a and ST change simultaneously to 11, state 1 will
be followed by a state c and a pulse emitted (assuming no function hazard
interferes). The absolute minimum number of state variables that may be used to
realize an r- row state table is
Pmin = ┌ log 2 r ┐
8
00
01
11
10
Present
State
00
Next State
ST
01
11
a,0
b,-
d,-
c,0
a
a,0
b,-
c,-
a,0
a,-
b,0
g,0
c,-
b
a,-
b,0
b,0
a,-
a,-
h,1
d,1
e,-
c
a,-
c,1
c,1
d,-
a,-
b,-
f,0
e,0
d
a,-
b,-
d,0
d,0
ST
(a)
10
(b)
Fig.6. Merged State Transition Table
where ┌ . ┐ denotes the nearest integer greater than or equal to log 2 r. Often P>Pmin
state variables must be used in the realization of asynchronous machines to avoid
critical races.
(b)
(a)
(c)
a
Four rows appear in figure 6.b, thus, at least two state
variables must be used. Figure 7.a shows abbreviated state
diagram for this machine. All transitions are shown but their
direction and labels are omitted. If a critical race is to be
avoided, states a and b, a and d, c and d, b and d must be
Transition
Diagrams.
assigned
adjacent
p-tuples
(codewords) (why?).
b Fig.7.
b
acd
It is not
possible to assign
2-tuples to the four states so that all of these requirements are satisfied. Triangular
patterns appear in figure 7.a. We cannot encode the vertices of odd-sided polygons
so as to satisfy “Hamming distance requirements”. In general, the state diagram and
table must be altered so that odd-sided polygons do not appear. This kind of
alterations usually results in a need for more than the absolute minimum number of
state variables.
d
c
In a normal state table, all unstable conditions lead directly to stable states.
The state table of figure 6 is a normal one; no uncircled entry points to another
uncircled entry. We shall not treat this point and the state assignment problem. For
now, we can and will encode the example machine with two state variables and still
avoid critical races. Only a’s appear in the first column of the state table. Thus, a
race when ST=00 cannot be critical, and any state assignment will be satisfactory as
far as the first column is concerned (why?). We must avoid an assignment that
9
would cause the machine to cycle endlessly between unstable states, of course. If
the transitions are specified in the first column, the STD reduces to figure 7.b, which
can be encoded with 2-tuples. Any of eight possible labelings of figure 7.c will
produce an acceptable code, and each such code will lead to a slightly different
network. For purposes of example, we will arbitrarily choose the following
straightforward assignment.
Present
State
y1 y2
Next State (y1' , y2')
ST
00
01
11
10
a=
00
00,0
01,-
10,-
00,0
b=
01
00,-
01,0
01,0
00,-
d=
11
01,-
01,-
11,0
11,0
c=
10
00,-
10,1
10,1
11,-
Fig.8. Enhanced State Transition Table
Additional attention may be directed to the first column of the encoded STT.
All entries in that column will be 00, the encoding for state a. A noncritical race
would then accomplish the transition from state d to state a. If this race is felt to be
undesirable, it may be avoided by making the state table abnormal. The transition
from state d to state a may be performed indirectly by passing through state b.
Figure 8 illustrates the encoding of this column so that the machine changes state as
ddba when ST changes from 10 to 00. This will surely increase the transition
time. Excitation equations for the state variables may be written directly from the
encoded STT. However, separate Karnaugh maps for y1 and y 2 are shown in figure
9 to facilitate writing the following hazard-free state transition equations. See figure
10.a.
y1 = S.y1 + T.y1. y 2 + S.T. y 2
y 2 = S.T’.y1 + y1.y2 + T.y2 + S’.T. y1
Asynchronous NAND latches may be used to store state variables in much the
same fashion as flip-flops were used in synchronous networks.
Latch input equations are derived from an encoded STT as follows:
S1 = S.T. y 2
R1 = S’.T’ + S’.y2
S2 = S’.T. y1 + S.T’.y1
R2 = T’. y1
10
If NAND latches are to be used, the complements of these variables must be
realized.
y2
y1
S
S
1
y1
1
1 1
y1 1 1 1 1 y2
1
T
1 1 y2
1 1 1
T
Fig.9. Karnaugh maps for the State Transition Equations
Output symbols are associated only with the stable entries in the merged STT.
The output symbol to be generated when the machine is in an unstable condition
remains to be determined. If the original and final stable states of a temporary false
values on the output lines are avoided by associating the same output symbol with
intermediate unstable entries in the STT. However, if different output symbols are
associated with the original and final stable states, the symbol of either state may be
associated with intermediate output unstable states.
Figure 10.a shows the known output symbols for the example machine. Figure
10.b shows the output symbol assignment that results in the widest possible output
pulses. Figure 10.c shows the assignment that results in minimum output logic.
z = y1 y 2 T
S
0
0
0 0
y1
0 0 y2
1 1
T
z = y1 y 2 + ST y 2
S
0 0 1 0
0 0 0 0
y1 0 0 0 0 y2
1 1 1 1
T
z = y1 y 2
S
0 0 0 0
0 0 0 0
y1 0 0 0 0 y2
1 1 1 1
T
(a)
(b)
(c)
Fig.10. Karnaugh Maps for Output Symbol Logic
11
2.
PRELIMINARY WORK
2.1.
Consider the network given in Fig. 11.
2.1.1. Using the “fundamental model” find the state transition table for the circuit.
2.1.2. In which cases “critical races” occur? Explain in detail.
2.1.3. Rearrange the state transition (flow) table to avoid critical races and
implement the new equivalent circuitry associated with the new SST. You may
assume that multiple input changes do not occur.
X
1
1
2
74LS00
X
2
47
1
51
1
3
9
10
Z
1
6
12
21
12
13
74LS10
31
81
4
1
21
74LS04
11
Z
2
31
Fig.11.
2.2. A simple optical sensing system which is connected to the shaft of an electric
motor and generating digital symbols specifying the position of the rotor. A disk
having concentric slots as shown in below is mounted on the shaft giving the proper
codes to determine the direction of rotation and the position of the shaft
12
01
10
Actual Disk
11
Encoding Schema
If the rotation is in the clockwise direction, then the codes generated are,
X1X2
00
01
11
10
If the rotation is in the counter-clockwise direction, then the codes will be,
00
10
11
01
2.2.1. Design an asynchronous sequential circuit giving an output indicating the
direction of rotation. The output will be high if the rotation is clockwise, and low in
counter clockwise direction
x1
ASC
x2
The circuitry should be designed such that the largest output pulse will be produced.
2.2.2. Is it possible to divide the disk into three partitions? If so, how should it be
coded? Implement the circuit for this case.
13
3.
EXPERIMENTAL WORK
3.1. Construct the asynchronous synchronizer designed in theoretical part with
NAND-latches and verify the operation.
3.2. Construct the circuit given in Fig. 11.
3.2.1 Verify the state transition table you found theoretically in preliminary work
2.1.1 by making and breaking the feedback paths.
3.2.2 Connect two cascaded inverters to the output of the NAND gate
a) generating z1
b) generating z2
Explain the differences between the operations of circuits.
3.2.3. Construct the race-free circuit you found in preliminary part. Compare the
performance of circuitry with those of the previous ones.
3.3. Construct the circuit designed for the shaft encoder and verify the operation.
Parts List
7400
7404
7410
7420
7430
14
EXPERIMENT 2
REGISTER TO REGISTER DATA TRANSFER
PURPOSE: Parallel and serial register to register data transfer will be studied
1. BACKGROUND INFORMATION
Serial data transfer is frequently used in slow and inexpensive computers.
Operation is usually synchronous, i.e. one bit is transferred at each clock pulse, and
the operation continues until the contents of one shift register are transferred to the
other.
In larger computers, parallel data transfer permits the simultaneous transfer
of all the bits of a source register to another register. Parallel data transfer is faster,
but operation may only be synchronous, in which case the flip-flops transfer data in
response to a clock pulse at their clock inputs. Alternatively, the operation may be
asynchronous, in which case the data transfer takes place in response to some
control signal. Most of the time only direct flip-flop inputs are used for synchronous
transfer.
Data transfer can also be a combination of serial and parallel operations. For
example, the contents of an 8-bit register may be moved by two successive 4-bit
parallel transfer operations.
15
2. PRELIMINARY WORK
2.1 PARALLEL TRANSFER
2.1.1. Design a circuit in accordance with the following specifications, using two
7495 shift registers, NAND gates and inverters. Data is to be transferred in parallel
between two 2-bit storage registers A and B. There will be two parallel data input
lines D0 and D, three control signals X, Y, Z, and a clock (Use separate shift register
chips for registers A and B).
A
B
X,Y,Z
D
0
1
Circuit Operation:
a. When X=0
if Y=1
if Y=0 the contents of register A is transferred to
register B
if Y=1 and Z=0 B is cleared to ZEROs
and Z=1 A is cleared to ZEROs
b. When X=1
if Y=0 any ONEs in register B are transferred to the corresponding stages of
A.
if Y=1 any ONEs on data inputs (D0D1) are transferred to the corresponding
stages of A.
Register contents can change only when the appropriate control signals are
present. If no changes are desired, the clock signal must be masked. Changes in
register contents should occur only when the clock signal comes.
2.1.2 Assume that the contents of both registers are unknown. Write the sequence
of logic levels required on the data and control lines to place 10 in A0A1 and 01 in
B0B1. List the state of each data and control line for each step in the sequence. If an
input may be either of the levels, list it as “don’t care” (X).
16
2.2 SERIAL TRANSFER
2.2.1 Using two 7495 4-bit shift registers A and B, design a circuit satisfying the
following specifications using 7495 4-bit shift registers, NAND gates and inverters.
Here are four data inputs D0, D1, D2, D3, two control lines X, Y and a clock.
Circuit Operation
When X=0, Y=0
When X=0, Y=1
When X=1, Y=0
When X=1, Y=1
the contents of register B are shifted right and the leftmost bit is
cleared.
the contents of register A are shifted right circularly and the
contents of register B are shifted right by taking serial data from
the rightmost bit of A, one bit at each clock period .
the data on lines D0D1D2D3 are loaded to register A.
the contents of register A are shifted right by taking serial data
from the leftmost bit of B, while the contents of register B are
shifted left circularly, one bit for each clock period
2.2.2 Write the sequence of control signals XY such that register B will contain the
reverse of the input data , i.e., if D0D1D2D3= d0d1d2d3, then register B will contain
d0d1d2d3. Show how the contents of register A are affected at each step.
2.2.3 Find the shortest sequence of control signals required to multiply the data on
D0D1D2D3 by 2 and store the result in register A. Show how the register contents are
affected at each step (Assume that D0D1D2D3=0101. Also assume that D0 will always
be 0).
XY Register A
Register B
Shift right (B0←0)
00 No change
01 Shift right circularly Shift right (B0←A3)
2.3 Using two 4bit shift registers
10 A←D (parallel load) No change
A and B, design a 11 Shift right (B0←A0) Shift left circularly circuit to permit
operations
specified below.
There are four data inputs D0, D1, D2, D3, three control inputs X, Y, Z and a clock.
a. When X=0, any ONES on D0D1D2D3 are transferred to A0A1A2A3 respectively
b. When X=1 and Y=0
if Z=0 the contents of A are shifted serially to B one bit at each clock period.
As data is shifted out of A, it is replaced by ZEROs.
if Z=1 the data in B circulates right.
c. When X=1 and Y=1
if Z=0 the data in B is shifted serially to A. As data is shifted out of B, it is
replaced by ZEROs.
if Z=1 the data in A circulates right.
17
3. EXPERIMENTAL PROCEDURE
1. Build and test the circuit you designed in preliminary work part 1.1. Apply the
sequence of inputs to perform the data transfer specified in preliminary work part 1.2
2. Build and test the circuit you designed in preliminary work part 2.1. Apply the
sequence of inputs to perform the data transfer in preliminary work part 2.2.
Haluk Ural
Parts List
2x7495 4-bit shift register
2x7400 Quad 2-input NAND gate
2x7410 Triple 3-input NAND gate
2x7404 Hex inverter
18
EXPERIMENT 3
ALGORITHMIC STATE MACHINES (ASM)
PURPOSE: Getting acquainted with ASM charts
1. BACKGROUND INFORMATION:
An Algorithmic State Machine (ASM) chart is a special type of flowchart
developed to define digital hardware algorithms.
It has three main elements:
State box
Name
indicates a state in the control
Binary
codesequence. It is given a symbolic
Error!
name and a unique binary code
Decision
to test a condition and the Error!
flow accordingly. Condition may
0
1
Conditionbe the state of an element or a
signal from outside
Conditional
expresses register operation or Error!
box
outputs. Must be found at the exit
Reg. opr.
or of decision boxes.
path
Reg. opr. Or
box
output is used
output
A state box with all the decisions and conditional boxes connected to its exit
path are called and ASM block. All the operations in an ASM block are carried out
simultaneously within one clock cycle. Here, this is the most important point to pay
attention. The operations are not handled one by one as in the usual flowchart
process; the operations take place in the same time period.
1.1 DESIGN PROCEDURE
Data processor design:
The elements needed to design the data processor are directly seen from the
state and conditional boxes.
Control circuit design:
The control logic is determined from the decision boxes and required state
transitions. For 2n states in ASM chart, we need n ff’s in control circuit. First a state
table is constructed depending upon the ASM chart. Then some different techniques
may be used:
19
1) With the JK ff’s: Looking at the sequence of states we implement that
sequence by determining the necessary values for J and K inputs of ff’s.
From the outputs of ff’s, the binary states are supplied.
2) With D ff’s: Same operations done by D ff’s. In both JK and D cases, we
may insert a decoder at the output of ff’s, to obtain the binary states (T0
T1, etc.).
3) One ff/state: Here, we spend more ff’s but the design is straight-forward
by looking at the ASM chart.
4) With MUX: Implementation with MUX brings a more systematic solution to
the problem. Here there are levels, the MUX level determines the next
state, the register level (may be implemented by ff’s) holds the present
state and the decoder provides the binary states.
Example: (Mano, “Digital Design”, Question 8.12 )
Design a digital system with three 4-bit registers, A, B, and C, to perform the
following operations:
1.
2.
3.
4.
Available
-
Transfer two binary numbers to A and B when a start signal (S) is enabled.
If A<B, shift-left the contents of A and transfer the result to register C.
If A>B, shift-right the contents of B and transfer the result to register C.
If A=B, transfer the number to register C unchanged.
Hardware:
one 4-bit register with shift-left, output-enable, and load inputs.
one 4-bit register with shift-right, output-enable, and load inputs.
one 4-bit register with load input.
one 4-bit comparator.
one 2x1 4-bit MUX.
Solution:
Sm means A<B
L means A>B
LOADA = T0S OEA = T2
LOADB = T0S OEB = T3
SHLA = T1Sm
SHRB = T1Sm*L
LOADC = T2 + T3
SEL = T3
20
Present
State
Name
T0
T0
T1
T2
T1
T3
T0
0
S
1
LOAD A
LOAD B
condition
G1G2
00
00
01
10
01
11
S
0
1
-
Sm
1
0
-
L
-
G1G2
00
01
10
00
11
00
Next
State
Name
T0
T1
T2
T0
T3
T0
T1
1
0
Sm
0
L
SHL A
1
C←A
T2
SHR B
C→B
T3
Data Processor:
4 bits
4 bits
A - REG
B - REG
LOAD B
LOAD A
SHL A
Sm
SHR B
L
COMPARATOR
0
SEL
1
MUX
4 bits
LOAD C
C - REG
Control implementation:
1) with JK ff’s:
21
S
0
1
-
Sm
1
0
-
JG1 = G2
JG2 = G1’S
L
-
G1G2 G1G2 JG1 KG1 JG2 KG2
00
00
0
X
0
X
00
01
0
X
1
X
01
10
1
X
X
1
10
00
X
1
0
X
01
11
1
X
X
0
11
00
X
1
X
1
KG1=1
KG2= G1+ G2Sm
J
SET
Q
x1
+5V
K
J
CLR
SET
Q
f(x1...xn)
u1
2x4 u2
Decoder
x2
u3
u4
T0
T1
T2
T3
Q
S
K
CLR
Q
Sm
2) with D ff’s:
DG1 = G2G1’
DG2 = SG1’G2’+ Sm’G1’G2
3) one ff/state:
DT0= T0S’+ T3 + T2
DT1= T0S
DT2= T1Sm
DT3= T1Sm’
4) with MUX & decoder:
22
G1 G2
0
1
0
0
4x1 MUX
0
1
DFF’s
2
DG Q
1
SET
x1
3
CLR
Q
x2
CLR
S
Sm’
0
0
u1
2x4 u2
Decoder
SET
DG Q
2
G1 G2
f(x1...xn)
Q
u3
u4
T0
T1
T2
T3
4x1 MUX
0
1
2
CLOCK
3
Error!
T0 (00)
S=0
S=1
T1 (10)
T0 (00)
T1 (01)
Sm = 0
T1 (01)
T0 (00)
Sm = 1
T3 (11)
T2 (10)
T3 (11)
T0 (00)
23
2. PRELIMINARY WORK:
PART 1
A system which tests 4-input NAND gates is to be designed. There is a
START signal which should appear as a pulse. There will be two outputs, OK
and FAULT, to display whether the tested gate operates well or not.
The system operation will be as follows:
1. Wait for the START signal to go high.
2. Wait for the start signal to go low after high (i.e. complete the pulse);
initialize the OK and FAULT ff’s to zero.
3. Test the connected NAND gate, and turn on the OK ff if the gate
operates well. If not then turn on the FAULT ff.
4. Go to step 1.
The test (step 3) will take place as follows:
All 16-input combinations will be generated by a 4-bit counter (74161), and
applied to the gate to be tested. These input combinations will be applied to a
reference NAND gate at the same time. The outputs of these two gates will be
compared by using an equivalence gate which generates a signal called SAME.
It is seen that the SAME signal will be high if the response of the tested NAND
gate to an input is true, low otherwise. After all the combinations are tested, if
all 16 combinations have worked well, the OK ff will be set. During the trial of
input combinations, if a fault occurs (i.e. the SAME signal is low) the FAULT ff is
immediately set and the control returns to the initial state (step 1) without
trying the rest of the input combinations.
The block structure of the system will be as follows:
CLK
CLK
CLEAR
START
CONTROLLER
ENDCNT
COUNT
CONTROLLER
Reference
NAND
T0 T1 T2
NAND gate
to be tested
SAME
J-OK
OK
J
SET
Q
CLK
K-OK
J-FAULT
FAULT
SET
J
Q
CLK
K
CLR
Q
K-FAULT
K
CLR
Q
DATA
PROCESSOR
The functions of the signals are as follows:
CLK: The system clock.
24
START: The signal to start the test procedure. It should go high and then low
to start the procedure.
CLEAR: To set the counter to zero. (active low)
COUNT: To advance the counter, i.e. pass to a new input combination. (This
signal can be connected to one of the ENABLE inputs of the counter.)
ENDONT: To indicate that all input combinations are applied. (The CARRYOUTPUT of the counter may be used for this purpose.)
J, K-OK,
J,K-FAULT: To set and reset the OK and FAULT outputs when
necessary.
SAME : High when the outputs of the test gate and the reference gate are
same, low otherwise.
IMPORTANT NOTICES!


The system may be implemented in three states. Your design should not
exceed four states.
The control circuits should be designed by using a MUX and a decoder.
Your MUX will be 74153. It is a dual 4-to-1 MUX with common select
signals. Decoder will be 74138. Although it is a 3-to-8 decoder, you will
use it as a 2-to-4 decoder. Please have a look at the catalog for them.
25
Part 2
PREPARED BY: Aslı Burcu ÜÇOK
PURPOSE: Getting acquainted with ASM charts by learning the state editor
of Xilinx Foundation F1.5.
In this preliminary work, you will test both the system described in the
BACKGROUND INFORMATION part of EXPERIMENT 3 and the 4-input NAND
gate tester described in the first part of the PRELIMINARY WORK by using
the state editor of Xilinx Foundation F1.5.
State Editor is a tool designed for graphical editing of state machine
diagrams. Drawing a state diagram is an alternative approach to the modeling
of a sequential device. The modeling of a sequential device can be done by
either entering the schematic of the device by using the well-known
components, like flip-flops and various gates or by writing the Hardware
Description Language (HDL) code by yourself. An HDL is the hardware
counterpart of the high-level languages like C++ or Pascal, and it defines the
netlist of the hardware of the system it describes. Instead of writing the HDL
code, we will enter the description of the control unit of our system as a
graphical diagram using the State Editor. Next, the editor will automatically
generate the HDL code based on the entered graphical description. Then, we
will generate the macro of the control unit, and use it in designing the whole
system in the Schematic Editor of Xilinx Foundation F1.5 with data and
control units. After finishing the design in schematic editor, the simulation of
the whole system will be done using the Logic Simulator.
SECTION 1:
You will enter the control unit of the system, which generates the signals TO,
Tl, T2, and T3, described in the BACKGROUND INFORMATION part of
EXPERIMENT 3 (Mano, "Digital Design", question 8.12) using the State
Editor. Then, in step 22, you will generate the HDL code based on the
entered graphical description. After generating the macro of the control unit
in step 25, we will use it in designing the whole system with data and
control units in the Schematic Editor of Xilinx Foundation F1.5, and
simulate the system using the Logic Simulator.
Step by Step in Xilinx Foundation F1.5 State Editor:
1. Create a directory named exp3 in the f:\ drive.
2. Open the Xilinx Foundation project manager by using the icon on the
desktop.
3. Create a new project in your home directory
named exp3pre1.
Name: exp3prel
Directory: F:\exp3\
Type: Foundation Series vl.5
Flow: Schematic, XC4000XL, 4010XLPC84, 3
4. Click Tools→Design Entry→State Editor or click on the ASM chart figure
in the Design Entry
rectangle.
5. On the incoming window, select the "Use HDL Design Wizard" to create a
new document. Click
on OK.
26
6. Click on Next.
7. Select ABEL as your HDL, and click on Next.
8. Write the name of the file in which your design will be saved as prel,
and click on Next. It is important that you give a different name to this
file other than the name of the project.
9. Now, you will create the input and output pins of the system. Click on the
New button and start to enter the input and output pins as:
Table 1: Input and output pins of the system
Pin Name Pin Type Pin Name Pin Type
RST
Input
T0
Output
S
Input
Tl
Output
Sm
Input
T2
Output
L
Input
T3
Output
Here, RST will be used as the reset signal to start the system from the
desired state. Click on Next.
10. The Design Wizard will ask you whether you want to add a clock port
named CLK, or not. Click on yes as answer to this question.
11. Select One as the number of machines. Click on Finish.
12. Now, you can see the state editor having the input and output ports
together with the clock signal shown on top of the state editor page.
13. Select View→Toolbars→Default Position in order to see all the toolbars
including Main, FSM, and Draw.
14. By selecting FSM→State (or directly clicking on the State icon -2nd iconon the FSM toolbar),
put four states in the state editor page. Then, by double clicking on the
names of the states, change the names as shown in Figure 1.
Figure 1: The states of the system after placed on the state editor page.
27
15. Now, it is time to enter the state actions. Let's enter the state action for
state SO. The state action is T0 signal being set to 1. Select
FSM→Action→State (or directly click on the State Action icon
-6th icon- on the FSM toolbar), and click on the SO state circle making sure
that the contact point is inside the state circle area. The syntax for this
state action in ABEL HDL is:
T0=l;
This syntax is used both for the state actions and for the transition
actions (In this experiment we will not use any transition action).
16. Now let's draw the transitions between the states. As an example, let's
draw the transition from S0 to S1. Select FSM→Transition (or directly
click on the Transition icon -3rd icon- on the FSM toolbar), then draw the
transition line from S0 state circle to S1 state circle. Be sure that the ends
of the transition line are connected to the corresponding state circles.
17. The condition for transition from S0 to S1 is S being 1. The syntax for this
transition condition is written as:
S
Syntax of some other transition conditions are "!signal" for "signal=0",
"signall & signal2" for "signall=l AND signal2=l", etc.
To enter the transition condition, select FSM→Condition (or directly
click on the Condition icon -4th icon- on the FSM toolbar), then click on
the transition line. Figure 2 shows the state diagram of the system after
this step.
Figure 2: The state diagram of the system showing how the state actions and transition
conditions are entered.
18. Obeying the syntax rules, all the other state actions and transition
conditions are entered as shown in Figure 3.
28
!S
Figure 3: The state diagram of the system after all the state actions and transition
conditions are entered.
Note that, if Sm=0, the system will have a transition from state S1 to
state S3 regardless of the value of signal L, but the two transitions from
S1 to S3 in this ASM chart do not cause any problem. The advantage of
this configuration is that the macro of the control unit, which will be
created from this ASM chart, will have signal L as one of its inputs.
Also note that the system will transit to state T0, the reset state, when the
reset condition is true. Here, we will take the transition to the reset state
as asynchronous, so right click on the triangle reset symbol with the
mouse and choose Asynchronous.
19. We can declare output ports either as combinatorial or registered. The
difference between a registered and combinatorial port lies in the way
in which signal assignments to such ports are coded in the generated
HDL. Now, we will declare the output ports as combinatorial. Right click
on the output ports on the upper part of the state editor page, and select
Properties→Combinatorial→Apply Now for all the output ports if
they are not already set so.
20. Now, it is time for synthesis of the ASM.
language is ABEL.
First be sure that your HDL
(Synthesis→Configuration→Language=ABEL)
(Synthesis→Configuration→Tools=XABEL(Xilinx))
29
21. Make sure that Separate window for DOS tasks icon is checked in
Project Manager's
File→Preferences→Configuration window.
22. Select Synthesis→HDL Code Generation. Click on Yes to the incoming box
in order to view the generated code.
23. In the incoming HDL Editor, select Synthesis→Check syntax in order to
check the syntax of the generated ABEL code. If Errors found message
is displayed, check the syntax of the state actions, transition conditions,
and the input and output pin names. These are the only possible
error sources in your code. After closing the HDL Editor, return to the
State Editor and correct the syntax error, then return to step 22.
24. Close the HDL Editor.
25. In order to synthesize the generated ABEL code and create a macro of the
ASM system to be used in the Schematic Editor, select Project→Create
Macro in the State Editor window (If you encounter a problem, try
opening a command prompt from the Start menu of the computer and
writing:
C:\fndtn\bin\nt\abI2edif -a XC4000EX -o f:\exp3\exp3prel\prel.edn
-s mod f:\exp3\exp3prel\prel.abl
in order to synthesize the generated ABEL code. After seeing that abl2edif
has succeeded, return to the State Editor window, then select
Project→Create Macro to create a macro of the system.)
(Make sure that Separate window for DOS tasks icon is checke d in
Project Manager's File→Preferences→Configuration window.)
26. Observe that symbol "PRE1" is successfully created. Now, you have
the control unit of the ASM system as a macro symbol, which can be
used in designs entered in the Schematic Editor.
27. Open the Schematic Editor.
28. In the page setup menu, choose A4-297x210mm.
29. From the previous courses, you know the Schematic Editor very well, so
now by using the macro symbol of the ASM system (open the SC
symbols window by selecting Mode→Symbols) it is desired that you
design the whole system with control and data processor units.
PRE1
SM
30
Figure 4: The schematic for testing the created control
unit.
Hints:
•
It is better that you first check that the created macro works
correctly. Test the created control unit by simulating the schematic of
Figure 4.
On a new sheet, draw the whole system with control and data
processor units. Obtain the signals used in the data processor unit.
LoadA =T0.S
LoadB = T0.S
ShlA=Tl.Sm
ShrB=Tl.Sm'.L
LoadC =T2+T3
Sel =T3
OEA =T2
OEB =T3
•
You can use SR4CLE as the shift register. Note that SR4CLE is a little
bit different from the required register configuration of the preliminary
work, so if you want, you can also design and use a register that
exactly fits the requirements.
•
If you are using SR4CLE, note that you will have to obtain the CE (Clock
Enable) signal from the existing signals.
•
Although implementation of the system will not be done in the lab, it is
better that you don't forget to put input and output buffers just
after and before the input and output pins, respectively. Be sure
that the buffer you choose for the clock input is BUFG, not the usual
IBUF.
• You can use M2_1E, 2-to-l multiplexers and the FD4CE 4-bit data
register in your design.
•
Consider also using the negative edge of the CLK.
•
If you need the signals 1 (HIGH) or 0 (LOW), use the power symbol
button to enter those signals in your schematic.
•
You can use the XACT Libraries Guide found in the EA Computer
Laboratory if you need more information about the design elements.
•
Write your name, date, laboratory group, experiment and preliminary
work question number to the schematic information table by selecting
File→Table setup.
•
After completing the schematic of the whole system with control and
data processor units, take a print-out of the schematic. Be sure that
it is large enough to fit the page, and the connections can be seen
well. Make sure that A4-297x210mm, frame on, and ruler metric
options are selected in the page setup menu, and A4 and
corresponding paper orientation are chosen in the printer
setup→options menu. If the schematic is too large to fit in new page
31
size, move the components in the schematic to fit all the schematic in
one page. In the print menu select the current sheet, and fit to page
options.
30. After completing the schematic of the system, by using the Logic
Simulator, simulate the whole system with control and data processor
units. Hints:
For the CLK signal, click the last (rightmost) yellow diode in the row
marked Bc in the Stimulator Selection window to define clock
stimulator.
•
• It is advised that you define the keyboard stimulator for the input
signals RST, S, Sm, and L.
•
For the data inputs of A and B registers, you can use either the
keyboard stimulator, or you can assign constant 0 or 1 values to
these signals. Here, it is important that you select the signals such
that one can observe the SHL A, SHR B, LOAD C WITH A, and LOAD
C WITH B operations easily from the simulated signals. For example,
do not give both of the register data inputs as all 0's or all l's!)
•
Together with the input and output signals of the system, remember to
add the state signals in order to observe the state flow during
simulation. Click on Signal→Add Signals, and in the incoming
Component Selection for Waveform Viewer window select Chip
Selection→PRE1, and then select T0, Tl, T2, and T3 from Pins
for PRE1. Close the window.
• From Option→Preferences→Simulation, change the B0 period of
the Clock as 1us.
•
In Option→Preferences→Power On, make sure that the Global
Reset option is not selected, and the pulse global reset net is
disabled.
•
The simulation will be done in the timing simulation mode. Select the
Timing option from the simulation mode combo-box in the
Simulator toolbar.
•
It is better that you combine the data input pins of registers A and B,
and the data output pins of register C as buses for easier track of the
signals by using the simulator's Bus→Combine option.
•
Verify that the system works correctly, and take a print-out of the
simulation that shows all the states working correctly. It is advised
that you choose the orientation of the page as landscape in the print
setup menu. In the page setup menu, choose every n page option.
•
On the print-out of the simulation, mark the changes in the control
signals, and state which action is done as a result of that change of
those signals.
32
SECTION 2:
Now, design the 4-input NAND gate tester described in the first part of
the PRELIMINARY WORK by using the state editor, schematic editor, and
simulator of Xilinx Foundation F1.5.
Take the print-outs of the
a) ASM chart of the control unit drawn using the State Editor. In the
page setup menu, choose portrait and A4. In the print setup menu, do
not forget to choose A4 and portrait as the paper size.
b) ABEL code of the ASM system after checking the syntax of the generated
code.
c) The two schematics of the whole system with control and data processor
units, one corresponding to a correctly working NAND gate as the test
element, and the other corresponding to a faulty NAND gate as the test
structure. Be sure that the schematics are large enough to fit the pages,
and the connections can be seen well. Make sure that A4-297x210mm,
frame on, and ruler metric options are selected in the page setup
menu, and A4 and corresponding paper orientation are chosen in the
printer setup→options menu. If the schematic is too large to fit in new
page size, move the components in the schematic to fit all the schematic
in one page. In the print menu select the current sheet, and fit to page
option
d) The simulation results of both of the circuits showing that all the states
are working correctly. Choose the orientations of the pages as
landscape in the printer setup menu. In the page setup menu, choose
every n page option.
Hints:
•
As the 4-input NAND gate tester circuitry, you will prepare two
schematics. One will be the one with a 4-input NAND gate as the test
element (which will correspond to a NAND gate working correctly), and
the other one will have a 4-input NOR gate as the test element
(which will correspond to a faulty NAND gate).
•
For the CLK signal, click the last (rightmost) yellow diode in the row
marked Be in the Stimulator Selection window to define clock stimulator.
•
Change the BO period of the Clock as lµs.
• Make sure that the Global Reset option is not selected, and pulse global
reset net is disabled.
•
The simulation will be done in the timing simulation mode.
•
Together with the input and output signals of the whole system,
remember to add the state signals in order to observe the state flow
during simulation. Also add the COUNT, CLEAR, SAME, ENDCNT
signals, and the data output pins of the counter.
•
On the print-out of the simulation, mark the changes in the control
signals, and state which action is done as a result of that change of those
signals. Also show clearly which signal corresponds to COUNT, SAME,
etc.
33
YOU'RE WELCOME TO ASK ANY PROBLEMS YOU ENCOUNTER
WHILE DOING THE PRELIMINARY WORK.
Acknowledgement: Thanks to S. Sermet Akbay for sharing his expertise in
Xilinx Foundation F1.5 in preparing this preliminary work.
34
3. EXPERIMENTAL PROCEDURE:
1. Construct and test only the control circuit for your design by supplying the
necessary signals manually.
2. Construct the data processor, too, and test the system as a whole.
Parts List:
- 74153
- 74138
- 74161
- 7474
- 7476
- 7404, 7400, 7410, 7420, 7486
VERY IMPORTANT NOTICE!!!
PLEASE COME AND ASK ANYTHING YOU DIDN’T UNDERSTAND ABOUT THE
EXPERIMENT.
Levent OZAS – Orkun EKİNCİ
35
EXPERIMENT 4
CPU ORGANIZATION AND MACHINE CODE PROGRAMMING
Purpose: Organization of a simple CPU model and machine code
programming will be discussed.
1. BACKGROUND INFORMATION
Central processing unit (CPU) consists of a control unit, an
arithmetic&logic unit (ALU) and some registers. In this experiment, only ALU
and general purpose registers part of an elementary CPU model will be
implemented. Block diagram of the interconnection between ALU and
registers is given in Fig. 1
DATA INPUT
MUX
R1
R0
R2
R3
MUX
B
A
ALU
F
Figure 4.1 Block Diagram of Interconnection Between ALU and Registers (All data paths are
4-bit)
ALU is capable of doing some arithmetic and logic operations such as
addition, subtraction, logical OR, AND on 4-bit words coming through A and B
inputs. There are four 4-bit registers R0, R1, R2, and R3. There exists a data
path between F output of ALU and register inputs. So, it is possible to select
one of these registers to store the result of the operation performed by ALU.
R0 has a special property that it can also load 4-bit input data coming through
an external device (e.g. switches). B input of ALU directly comes from R0,
however, A input can be supplied by either R1, or R2, or R3. Thus, it is
possible to make a selection among these registers for data manipulation on
ALU.
36
The operation of ALU (add, subtract, etc), source registers and
destination registers can be selected with a set of control signals supplied
externally. This set of control signals is called an “instruction”. Instructions
will be supplied by an external circuitry (Instruction Sequencer) according to
the timing and status signal such as CLOCK, RESET, and CARRY, as shown in
Figure 4.2.
INSTRUCTION
4-BIT
CLOCK
RESET
CLOCK,
I1
–DATA
I12
RESET,
INPUT
CARRY
PROGRAM
Figure
4.2
Connection
to Instruction Sequencer
INSTRUCTION
ALU
MEMORY
&
SEQUENCER
REGISTERS
Instruction is an information
which consists of 12
bits. It determines
the operation which
will be performed among registers R0, R1, R2, and R3. Sequence of
instructions (a program) are stored in the program memory, beginning from
memory location 0. After RESET, Instruction Sequencer gives the instruction
at memory location 0. It increments the Program Counter (PC) and gives the
next instruction in the memory in the next clock cycle. This process continues
by incrementing PC at each clock cycle. However, there are two special
instructions (to be discussed later) which may change the value of PC
arbitrarily. Circuit diagram, showing ALU and registers, is given in Figure 4.3.
MUX (74157) selects either data input or ALU output F, and transmits it
to register R0. This information is stored in R0 if MODE input of 7495[1] is
high.
74170 is four 4-bit register file. One of these registers is not used, the
others are used as R1, R2, R3. ALU output can be stored to one of these
registers by controlling WRITE SELECT inputs of 74170 (WA,WB). READ
SELECT inputs (RA,RB) permit direct reading of data stored in any of three
registers R1, R2, R3. Q4-Q1 outputs of 74170 should be connected to pull-up
resistors, since they are “open collector”. 7495[2] is used to eliminate some
problems arised since the WRITE ENABLE input of 74170 is level-sensitive,
not edge. You may assume that 74170 outputs are directly connected to A
inputs of ALU, to prevent some details. ALU (74181) is the most important
component in the circuitry. It performs arithmetic and logic operations on two
4-bit data coming into the A and B inputs. Its operation can be selected by
using M, Cn, S3, S2, S1, S0 inputs as shown in the appendix.
For example, if M=L, Cn=H, S3=H, S2=L, S1=L, S0=H, ALU performs
“A PLUS B” operation. Note that, “+” sign is used for logical OR, “PLUS” and
“MINUS” are used for arithmetic addition and subtraction respectively. Cn+4 is
37
the carry output that takes a value according to the operation being
performed. This signal is connected to the Instruction Sequencer to give an
information about the result of the operation. When subtraction operation
(F=A MINUS B) is selected, Cn+4 is activated if A is not zero.
1.1
INSTRUCTIONS
There are four types of instructions:
1. Arithmetic/Logic and Data Transfer Instructions (ALDT)
2. Input Instructions (INP)
3. Jump Instructions (JMP)
4. Conditional Jump (Jump-If-Carry) Instructions (JIC)
38
1.1.1. ARITHMETIC/LOGIC & DATA TRANSFER INSTRUCTIONS
(ALDT)
Format is as follows:
16
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
M
Cn
S3
S2
S1
S0
ALU Operation
4
3
SRC
REG
Operat
01:ion
R1
10: R2
11: R3
2
1
DST
REG
Operat
00:ion
R0
01: R1
10: R2
11: R3
I10-5: Determines the ALU operation
I4-3: Selects one of 74170 registers R1, R2, or R3 which will be supplied to A
input of ALU.
01: R1 – 10: R2 – 11: R3
I2-1: Selects the destination register (R0, R1, R2, or R3) which the result of
the operation will be stored on. For example, the code of the instruction
which stores the addition of R0 and R1 to R2 is as follows:
00 011001 01 10
F = A PLUS B
R1 R2
If we use hexadecimal notation rather than binary then, the code of
this instruction is 0196. Note that, hex notation will be used in the rest of the
text. Writing programs by numbers is not meaningful to a human in contrast
to a
machine. So, usually symbolic representations (mnemonics) are
used when writing programs. The previous add instruction can be written as:
ADD R0,R1;R2
operation
destination register
source registers
A small subset of ALDT instructions and their codes are listed below:
Instruction
SUB R1,R0;R2
OR
R1,R0;R1
AND R3,R0;R2
MOVE R0;R1
INC R1
DEC R2
CLR R3
SET R1
Code (hex)
066
2E5
2BE
2A1
005
1FA
23F
2C5
Function
R1 MINUS R0 -> R2
R1 + R0 -> R1
R3 . R0 -> R2
R0 -> R1
R1 PLUS 1 -> R1
R2 MINUS 1 -> R2
0 -> R3
F -> R1
39
1.1.2. INPUT INSTRUCTIONS (INP)
Format is as follows:
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
0
0
This instruction loads the R0 with the data coming through input data
lines. It may be used to get information from external peripherals. If we take
the don’t cares as 0, then the code of INP instruction becomes 0400.
1.1.3. JUMP INSTRUCTION (JMP)
Format is as follows:
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
J
J
J
J
J
J
0
0
0
0
Jump Address
ALDT instructions and INP instruction do not affect the sequence of the
execution of the instructions. That is, Instruction Sequencer supplies the next
instruction in the memory by incrementing PC at each clock cycle. However,
sometimes it is necessary to control the execution sequence of instructions.
JMP instruction does not affect the status of he registers. But Instruction
Sequencer updates the program counter (PC) with the jump address and
gives the instruction code at this address at the next clock cycle.
Assume that, there exists “JMP 7” (code is $0870) instruction at
location 3. After the execution of JMP instruction, PC will be 7 instead of 4.
1.1.4. CONDITIONAL JUMP INSTRUCTION (JIC)
Format is as follows:
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
J
J
J
J
J
J
0
0
0
0
Jump Address
This instruction is very similar to JMP instruction. Instruction sequencer
handles it and the instruction does not affect the register contents. If the
preceding instruction has generated a carry, PC is loaded with the jump
address; otherwise PC is incremented (no operation).
JIC instruction is generally used after DEC Rn instruction. Such a usage
of JIC means “jump if Rn is not F (binary 1111)” or equivalently “jump if Rn is
not 0 before the execution of DEC instruction”. If JIC is used after SUB Rn,
R0:Rm then, it means “Jump if Rn is greater than or equal to R0”.
40
Label can be used as jump address instead of numeric values.
Example:
.
.
LOOP: DEC R2
JIC LOOP
.
.
Address
.
.
5:
6:
.
.
Code
.
.
01FA
0C50 // JIC to location 5
.
.
1.2. SAMPLE PROGRAMS
We will us register R0 as output by connecting it to the LEDs. For that
reason all of the following programs store their results into register R0.
SP1: Following program takes 1’s complement of the input data
INP
COM RO;RO
END*
0:0400
1:0250
2:F0F0
*END instruction ends the operation.
SP2: Following program takes two input data and adds them.
INP
MOVE R0;R1
INP
ADD R1,R0;R0
END
0:0400
1:02A1
2:0400
3:0194
4:F0F0
SP3: Following program finds the greater of two input data.
TRA:
INP
MOVE R0;R1
INP
SUB R1,R0;R2
JIC TRA
END
MOVE R1;R0
END
0:0400
1:02A1
2:0400
3:0066
4:0C60
5:F000
6:0104
7:F0F0
41
SP4: Following program makes logical OR operation on four successive input
data.
CLR R3
0:023F
INC R3
1:000F
INC R3
2:000F
INP
3:0400
MOVE R0;R1
4:02A1
LOOP:
INP
5:0400
OR R1,R0;R1
6:02E5
DEC R3
7:01FF
JIC LOOP
8:0C50
MOVE R1;R0
9:0104
END
A:F0F0
SP5: Following program takes 1’s complement of the input data continuously
with about 1Hz frequency (assuming 1 KHz clock).
AGAIN:
LOOP1:
LOOP2:
INP
COM R0;R0
SET R1
SET R2
DEC R2
JIC LOOP2
DEC R1
JIC LOOP1
JMP AGAIN
42
NECESSARY CONNECTION BETWEEN YOUR CIRCUIT AND
68HC11EVBU
In this experiment to test our programs we need an Instruction
Sequencer and Program Memory. We will be using MC6811 for this job. The
program codes will be written to the memory locations starting from $8500.
So the sample program 1 will lie in memory:
Memory Address
INP
0:0400
$8500, $8501 (two
bytes)
COM RO;RO
1:0250
$8502, $8503
END*
2:F0F0
$8504, $8505
So the in the memory locations
43
$8500:
$8501:
$8502:
$8503:
$8504:
$8505:
04
00
02
50
F0
F0
After writing your program to the memory you should make the
necessary connections between your circuit and MC6811. For this purpose we
need both input and output ports. (Actually we need 12 output ports for 12
instruction bits and 3 input bits for CARRY, RESET and CLOCK).
We have prepared an Instruction Sequencer program which will do the
memory and I/O operation in MC6811. In other words Instruction Sequencer
can understand our generic instruction code-words. Before starting this
program you should map the necessary memory locations as INPUT or
OUTPUT ports. These locations are the location the Instruction Sequencer
code will read and write data. These locations are shown in the figure.
Now you are ready to start the Instruction Sequencer. The program is
ready in your computers. Load the code and enter “G 8000”
If you examine the instruction sequencer code given in the appendix,
you will better understand the structure.
44
2. PRELIMINARY WORK
2.1. Find the codes of the following instructions
AND R3,R0;R3
NOR R2,R0;R2
XOR R1,R0;R2
XNOR R2,R0,R3
SHFL R2
(exclusive OR)
(exclusive OR)
(shift left)
2.2. Convert sample program SP5 into machine code.
2.3. Write a program which calculates the square of the input number.
2.4. Write a program which calculates the square of the sum n+(n-1)+…+0 if
the input is “n”.
2.5 Write a program which multiplies two input numbers.
2.6. Write a program which calculates the integer division of the input
numbers.
45
3. EXPERIMENTAL WORK
3.1. Construct the data port
3.2. Construct the circuit give in figure 3. Connect DATA INPUTS to the
switches and outputs of registers R0 (7495[1]) to the LEDs. Use push-button
switch for CLOCK. Use a switch for RESET.
MC6811 and BUFFALO platform will be used to emulate the Instruction
Sequencer and program memory. Make necessary connection between your
circuit and MC6811 as explained above.
3.3. Run the sample programs SP1, SP2, SP3 and SP4 giving various input
values. Observe the results and trace your algorithm using the BUFFALO
interface.
3.4. Run sample program SP5 with 1 KHz clock.
3.5. Test the programs written in Preliminary parts 2.3 and 2.4 with 1 KHz
clock.
3.6. Test the programs written in Preliminary parts 2.5 and 2.6 with manual
clock.
Prepared by: Levent ÖZAª
December 1987
Adapted to 68HC11 by:
Mehmet Nazir KAÇAR
Alper BEREKETLİ
Instruction Sequencer Code by:
Mehmet Nazir KAÇAR
Hardware by:
Neslihan YALÇIN
Algan USKARCI
Documented by:
Erdem AKAGÜNDÜZ
Evren İMRE
Supervised by:
Prof. Hasan GÜRAN
Asst. Prof. Cüneyt F. BAZLAMAÇCI
April 2003
46
APPENDIX
* EE446 EXPERIMENT 4 - INSTRUCTION SEQUENCER CODE
* FOR 68HC11 EVALUATION BOARDS - M.N.KACAR 2003
org $0100
PC
FDB $0000
CARRY FCB $00
PORTD EQU $1008
PORT2 EQU $4000
PRGADDR EQU $8500
* PORT CONNECTIONS BTW 68HC11EVBU AND CADET
* DATA PORT AT 4000: D7 D6 D5 D4 D3 D2 D1 D0
*
I8 I7 I6 I5 I4 I3 I2 I1
*
* PORTD AT 1008:
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
*
- I12 I11 I10 I9
*
*
*
*
*
ORG $8000
LDAA #$88
STAA $1026
LDAA #$3F
;DDRD is set to 1, i.e. all pins output
STAA $1009
CLR PORT2
;clear PORT2
CLR PORTD
;clear PORTD
LDX #PRGADDR
STX $PC
FETCH
LDX $PC
LDAA $00,X
CMPA #$F0
BNE CONT
LDX #MSG15
JSR $FFC7
JSR $FF7C
CONT
ANDA #$0C
BNE OTHERS
JMP ALDTINS
OTHERS LDAA $00,X
ANDA #$08
BNE OTHERS2
JMP INPINS
OTHERS2 LDAA $00,X
ANDA #$04
BNE JICINS
JMP JMPINS
JICINS
LDX #MSG7
JSR $FFC7
LDAA #$30
STAA PORTD
CLR PORT2
LDAA $CARRY
BEQ ZERO
LDX $PC
LDAA $00,X
INX
LDAB $00,X
ASLA
ASLA
ASLA
ASLA
ASLA
ASRB
ASRB
ASRB
ANDB #$1E
ANDA #$60
ABA
TAB
LDX #PRGADDR
;LOOK FOR 12 AND 11 TH BITS
;LOOK FOR 12TH BIT ONLY
;LOOK FOR 11 TH BIT ONLY
;SET I12, I11 AND CLEAR I4 I3 I2 I1 SO THAT THE REGISTER
;CONTENTS DO NOT CHANGE
;IF CARRY IS 0 THEN DO NOT JUMP
;WE NEED
;TO MULTIPLY THE GIVEN ADDRESS BY TWO.
47
ZERO
ABX
DEX
DEX
STX
LDX
JSR
JMP
$PC
#MSG8
$FFC7
CLKCHK
JMPINS LDX #MSG5
JSR $FFC7
LDAA #$20
STAA PORTD
CLR PORT2
LDX $PC
LDAA $00,X
INX
LDAB $00,X
ASLA
ASLA
ASLA
ASLA
ASLA
ASRB
ASRB
ASRB
ANDB #$1E
ANDA #$60
ABA
TAB
LDX #PRGADDR
ABX
DEX
DEX
STX $PC
LDX #MSG6
JSR $FFC7
JMP CLKCHK
ALDTINS LDX #MSG1
JSR $FFC7
LDX $PC
LDAA $00,X
ASLA
ASLA
STAA PORTD
INX
LDAB $00,X
STAB PORT2
LDX #MSG2
JSR $FFC7
JMP CLKCHK
INPINS LDX #MSG3
JSR $FFC7
LDAA #$10
STAA PORTD
CLR PORT2
LDX #MSG4
JSR $FFC7
JMP CLKCHK
CLKCHK LDX #MSG9
JSR $FFC7
CLKC
LDAA $1000
ANDA #$01
BEQ CLKC2
JMP CLKC
CLKC2 LDAA $1000
ANDA #$01
BNE TOCARRY
JMP CLKC2
TOCARRY LDX #MSG10
JSR $FFC7
CLR $CARRY
LDAA $1000
ANDA #$04
;SET I11, CLEAR I10 AND CLEAR I4 I3 I2 I1 SO THAT THE REGISTER
;CONTENTS DO NOT CHANGE
;WE NEED
;TO MULTIPLY THE GIVEN ADDRESS BY TWO.
;TWO BIT SHIFT LEFT AND SEND TO PORTD
;SEND THE REST TO DATA PORT DIRECTLY
;SET I11 AND CLEAR OTHERS
;LOOK FOR CLOCK INPUT ONLY TO SEE 0
;LOOK FOR CLOCK INPUT ONLY TO SEE 1
;LOOK FOR CARRY
48
BEQ TORESET
LDAA #$FF
STAA $CARRY
LDX #MSG14
JSR $FFC7
TORESET LDAA $1000
ANDA #$02
BEQ TOFETCH
LDX #PRGADDR
STX $PC
LDX #MSG11
JSR $FFC7
JMP FETCH
TOFETCH LDX $PC
INX
INX
STX $PC
LDX #MSG12
JSR $FFC7
JMP FETCH
MSG1
MSG2
MSG3
MSG4
MSG5
MSG6
MSG7
MSG8
MSG9
MSG10
MSG11
MSG12
MSG13
MSG14
MSG15
;LOOK FOR RESET
ORG $8300
FCC "--ALDT COMMAND FETCHED."
FCB $04
FCC "--ALDT COMMAND EXECUTED."
FCB $04
FCC "--INP COMMAND FETCHED."
FCB $04
FCC "--INP COMMAND EXECUTED."
FCB $04
FCC "--JMP COMMAND FETCHED."
FCB $04
FCC "--JMP COMMAND EXECUTED."
FCB $04
FCC "--JIC COMMAND FETCHED."
FCB $04
FCC "--JIC COMMAND EXECUTED."
FCB $04
FCC "WAITING FOR CLK..."
FCB $04
FCC "CLK ENCOUNTERED."
FCB $04
FCC "RESET ENCOUNTERED."
FCB $04
FCC "NO RESET, CONTINUING..."
FCB $04
FCC "NO CARRY!"
FCB $04
FCC "THERE IS A CARRY!"
FCB $04
FCC "THE END!"
FCB $04
49
EXPERIMENT 5
ARITHMETIC PROCESSOR UNIT ORGANIZATION
Purpose: The implementation of a simple arithmetic processor unit and its
control unit will be discussed.
1. BACKGROUND INFORMATION
Every microprocessor has an arithmetic unit to perform various
arithmetic and logic operations on input data. This unit consists of a
computation unit, a control unit and necessary registers to hold data and/or
the result.
The computation unit is capable of performing addition, subtraction,
multiplication, division and various logical operations on the input data. The
necessary control signals throughout the computation are supplied by the
control unit. This is normally achieved through microprogramming using a
sequencer.
In this experiment, the computation unit (AU) will be implemented in
hardware and the control unit will be the MC68HC11 EVBU. The MC6811
(CPU) can be thought of as the sequencer and the machine code program
written for it as the microprogram. The microprogram is responsible for
generating the necessary control signals during the computation, and the
sequencer manages this task (Figure 5.1).
A0-3
CLK
B0-3
PARALLEL/SERIAL’
AU
PORT
MC68HC11 EVBU
Program
Memory of
MC68HC11
EVBU
LOADA’
ADD’/SUBTRACT
Q0-3
Bs
START
F0
F1
Figure 5.1 The experimental setup
The experimental arithmetic unit (AU) is capable of performing 4 bit
signed-magnitude addition, subtraction and 8-bit multiplication. The control
50
signals and data will be supplied via the parallel port added to the control unit
(see Connection diagram between MC69HC11 and AU topic):
A3/ Q3
A2/ Q2
A1/ Q1
A0 / Q0
LOADA’/ Bs
ADD’-SUB/ F0
PAR-SER’/ F1
CLK/ START
From Computer Side
The hardware diagram of the AU is given in Figure 5.2.
2. THE HARDWARE
AU is capable of adding and subtracting the contents of A and B, and
of multiplying the contents of B and Q.
The START signal must make a transition from high to low in order to
start the computation. Before this transition, the B input and its sign B s, and
the function (determined by F0 and F1) must be set accordingly. The function
table is given below.
F0
F1
Operation
0
0
Addition
0
1
Subtraction
1
0
Multiplication
1
1
Invalid Operation
51
In order to do addition or subtraction, register A must be loaded first.
For this, the sequencer must output the contents of A from the program
memory, and assert the LOADA and PARALLEL signals so that, A is loaded
parallel and the operation is ADDITION.
The algorithms for addition, subtraction and multiplication are given below
B input is masked, and the output of the adder has the value A. After this
phase, CLOCK must be asserted to load register A.
The AU hardware is totally negative edge triggered. Therefore the
clock must have a transition from high to low. This enables us to assert more
than one signal at the same time before the negative edge transition of the
CLOCK. However, there must not be any transitions in the control and data
signals while the clock changes from high to low.
52
After the CLOCK is made low, LOADA signal must be set to high and
ADD/SUBTRACT signal must be set accordingly, leaving the PARALLEL signal
untouched. Then the CLOCK must have another transition so that the result
of the ADDER (74LS83) is transferred to Register A, and the carry (or borrow)
is loaded to the E flip flop.
You must decide on the operation by considering the signs as given in
the algorithm. If 2’s complement of A has to be taken, this should be done
through the software, after reading the result of the operation (addition or
subtraction) as explained in the next paragraph.
Then the result must be shifted right into register Q. This is achieved
by asserting the SERIAL signal and supplying four CLOCK transitions. After
this, register Q holds the result, and the value is read into another program
memory through the port. Then, with another CLOCK transition, the value of
the E flip-flop is in register Q. The value of E can be extracted by reading Q,
masking Q3, and shifting right the result, as required. This concludes the
addition or subtraction operation. The answer and the overflow are expected
to be in the memory of MC68HC11 EVBU.
Multiplication is a bit more complicated than addition or subtraction.
The multiplicand is assumed to be the B input and the multiplier will be in
register Q. In order to load register Q with process. That is; we first load the
multiplier into register A, and asserting four CLOCK transitions. On doing this,
the contents of register A and the E flip-flop are cleared automatically. Note
that the PARALLEL/SERIAL signal must be switched accordingly. From this
point on, the multiplication algorithm is performed. The Q register is read in.
If the rightmost bit (Q0) is a one, then the contents of B is added to A. For
this purpose the PARALLEL signal must be asserted before the CLOCK pulse.
After addition, the E flip-flop and the registers A and Q must be shifted right.
This is achieved by asserting the SERIAL signal and then a CLOCK pulse. Then
the Q register is read in again. If now, the rightmost bit is zero, we will not
perform any addition, but will shift right E, A and Q. This will be performed
four times and the result will be in E, A and Q. Note that after every shifting
right of E, A and Q, the E flip-flop must be cleared for correct result.
This is achieved by setting LOADA signal first to low, then to high. While
doing this CLOCK must not have a transition.
After the multiplication is completed, the least significant nibble of the
result is read from register Q through the port. Then the contents of register
A is shifted into register Q. This value can be extracted as before. This
concludes the multiplication operation.
3. THE CONTROL UNIT
The control unit is the MC68HC11 EVBU. The control signals are read in
or output from the port. The port can be constructed using an octal latch
(74ls374), an octal buffer (74ls244) and a decoder (74ls138). Port is mapped
53
to 4000-7FFF. See manual for Experiment 4 of both 446 and 447, and 447
lecture notes (available at the webpage of Mr. Bazlamaçcı), if you have any
problems with the construction of the port (and yes, we assume and expect
that you are familiar with certain 447 topics).
For the generation of control signals, a control program must be
written. The program first, must wait for the START signal to go from high to
low as discussed in part 2. This is achieved by polling the port (the bit
corresponding to START signal).
After detecting the transition, the control program must read in the
operation code (F0, F1), B and its sign Bs. The program must read the value
for register A from memory and must output this value with the necessary
control signals to load register A in AU (as discussed in part 2).
After loading register A, the algorithm for the selected operation is
performed (see part 2). Note that A and its sign As are used as Q and Qs
during the multiplication operation. The sign of the result is always calculated
separately by the software and stored to a temporary memory location. The
result of any operation is stored separately in memory. This is needed
because we do not want to lose the actual value of A and As. So you must use
dummy memory locations to store the result related to A and As.
Since the program can read the sign of B through the port and the sign
of A from memory, depending on operation, the control program must
calculate the sign of the result. In the cases of addition or subtraction, it must
also decide on the actual operation.
54
Connection diagram between MC68HC11 and AU:
You are mapping addresses between $4000 and $7FFF.
Error!
E
?
?
?
?
?
?
?
?
Q3
Q2
Q1
Q0
Bs
F0
F1
START
74LS244
68HC11
Evaluation Board
A3/ Q3
A2/ Q2
A1/ Q1
A0 / Q0
LOADA’/ Bs
ADD’-SUB/ F0
PAR-SER’/ F1
CLK/ START
OE
GND
74LS374
R/W E A15 A14
1
2
3
4
5
6
7
8
74LS138
E
A3
A2
A1
A0
LOADA’
ADD’/SUB
PAR/SER’
CLK/START’
16
15
14
13
12
11
10
9
º
PIN TABLE:
PC7/AD7
PC6/AD6
CLK/ START
PAR-SER’/ F1
16
R/W’ E
6
5
15
A15
35
PC5/AD5
PC4/AD4
ADD’-SUB/ F0
LOADA’/ Bs
14
13
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
A3/ Q3
A2/ Q2
A1/ Q1
A0 / Q0
12
11
10
9
A14
36
55
4. PRELIMINARY WORK
Part 1:
Study and understand the operation of the AU in figure 2. Then, write
the control program for AU. As discussed above, you will construct a port to
read and output data and control signals.
The value of A and its sign As are entered manually before the
execution of your program. You are free to choose any valid location in the
memory (To be on the safe side, use addresses between $8000-$B000).
Note that the operation of the AU is clocked and is negative edge
triggered. Parallel loading and shifting in AU requires clocked operation.
You should first draw a flow chart for your control program, indicating
clearly all steps to be performed. This will also help you very much in writing
and debugging your control program. Also, to speed up construction of the
circuit, prepare a schema of hardware with drawings of ICs in it, and
indicating which pin connects to which, by indicating the pin numbers of the
integrated circuits.
Part 2:
Implement the arithmetic processor you designed in Xilinx. You should
submit the following print-outs:
 Schematic design
 Simulations performed for an addition, a subtraction and a
multiplication operation. Results should be clearly indicated.
While constructing your circuit, you will notice that ICs used in the
experiment are absent in the Xilinx chip library, so your design should
undergo some minor modifications.
You may use SR4CLE as the shift register, but be careful that it is a
sihf left register. So, you will need to connect input and output pins of the
register in reverse order to the other chips. The input pin named L of this chip
is the mode select input of the register. When it has the value 0, the register
performs serial shifting and when it has the value 1, it performs parallel load.
The SL1 input pin is the Sin. D0,D1,D2,D3 are the parallel data inputs and
Q0,Q1,Q2,Q3 are the outputs. CE is chip enable (active high), CLR is clear
(active high).
The shift registers have only one clock input, so you might need to mask
the clock input of the Q register in case of parallel load. Masking operation
may be done by gating the Par/Ser input with the clock of the circuit, but you
should take care of any delays of the clock to the other gates.
56
You may use ADD4 as the adder. It ads A3-A0 and B3-B0. CI is carry-in,
S3-S0 is the sum output, CO is carry-out and OFL is the overflow output.
57
5. EXPERIMENTAL WORK
1. Construct the four bit adder/subtractor using 74LS86 and 74LS83, then verify the
operation.
B0
B1
B2
B3
Error! ADD / SUB
B0-3
A0-A3
74LS86
LEDs
74LS83
2. Construct the rest of the AU given in the Figure 2, and manually test the
operation of your hardware. For this purpose, you may fix the A and B inputs
of AU and then supply the control signals from the switches. Note that you
will be doing unsigned arithmetic.
Notice that when changing mode select signal of 7495, both clock signals
should be low (See the truth table in the datasheet of 7495 for details)
3. Construct the I/O port
4. Load the control program and verify its operation
Bülent Candan
April, 1990
Revised by
M. Fatih Bayramoğlu
Neslihan Yalçın
Evren İmre
April, 2003
Parts List
58
1x74LS83 4 bit adder
2x74LS95 4 bit parallel access shift register
1x74LS74 Dual positive edge triggered D type flip flop
1x74LS86 Quad 2 input EXOR gate
1x74LS08 Quad 2 input AND gate
1x74LS04 Hex inverter
1x74LS241 Tri-state buffer with complementary enables
1x74138 Decoder
1x74374 Octal latch
1x74244 Octal buffer
59
EXPERIMENT 6
ARITHMETIC ALGORITHMS
1. BACKGROUND INFORMATION
In this experiment, you are going to write an arithmetic library containing
addition, subtraction, division and multiplication subroutines for a 68HC11 system. An
arithmetic library is a block of machine language code capable of doing some
arithmetic operations on the input data. The library has a single entry point (that is
you will run a single code). The operation to be performed by the library must be
passed in an operation code register, which can be a predefined memory location. In
our case the operation code register will be holding the arithmetic operation to be
performed on the input data (multiplication, division, etc.).
After a call to the entry-point of the library, the code that you will write will first
detect the operation to be done and will transfer control to the related subroutine.
That subroutine will read the input parameters (the multiplicand % the multiplier in
the case of a multiplication operation) from the interface registers. The interface
registers are predefined memory locations as well. The related subroutine will then
perform the required arithmetic operation on the input data and will write the result
to the related locations in the interface registers. After that, the library code
terminates and the control is passed back to the user program.
For the interface registers and the user program we advise you a memory
mapping organization, which is shown below. Naturally you can use another
organization and run the program as well.
$8000
.
.
.
$9000
$9001
$9002
.
.
User program (which means you will start the program with the command "G 8000")
Operation Code Register
Interface Registers (these register has different meaning for different operations)
...
...
...
Before running the program the user enters the necessary values into the Operation
code register and the interface register. After entering the values the user starts the
program. The structure of the User program (according to this memory organization)
will be something like
1.
Look at $9000 – operation code register and understand the type of operation.
a. If it is as addition
i. Jump to addition subroutine and perform the addition.
ii. Write the desired result to the necessary memory location
b. If it is as subtraction
i. Jump to subtraction subroutine and perform the subtraction.
ii. Write the desired result to the necessary memory location
c. (Continues…)
60
The contents of the interface registers are operation dependent and will be
explained for each case separately. Please note that the interface registers are only
for parameter passing between the calling program and the arithmetic library. Thus,
you may find it easier to use some hardware registers (such as accumulator A,
accumulator B and Index Register IX) instead, in implementing the arithmetic
algorithms.
Floating Point Arithmetic
The information given in section 10-4 “Floating Point Arithmetic Operations” of
your textbook is sufficient for this experiment. The floating representation to be used
is:
s mantissa
8 bits
exponent
8 bits
2. PRELIMINARY WORK
You will write an arithmetic library including signed-magnitude addition,
subtraction, multiplication, and division and floating point multiplication. This
corresponds to chapters 9 and 10 of “Computer System Architecture” by M. Morris
Mano. Remember that the library will have only one entry point and will contain the
services described below.
16-bit Addition / Subtraction
The algorithm given on p. 337 of your textbook will be implemented. A and B
are 16 bit quantities and stored in two bytes each. Signs are stored separately. You
have to make operations on an 8-bit machine (68HC11). The interface registers for
this part are:
$900 XXXXXXXA
1
As is the sign bit of A
s
$900 XXXXXXXB
2
s
Bs is the sign bit of B
$900
3 A high
$900
4
A low
$900 will be in A and As.
Results
5 B high
$900
8-bit multiplication
6
B low
$900 The hardware
thisalgorithm
is the bitgiven
that indicates
on p.340 the
of your textbook will be implemented.
7
AVF (B)
overflow.
The multiplicand
and the multiplier (q] are both 8 bits and the product will be in
AQ (most significant byte in A). The interface registers for this part are:
61
$900
1 XXXXXXXAs As is the sign bit of the result
$900 XXXXXXXQ
2
s
Qs is the sign bit of Q
$900 XXXXXXXB
3
s
Bs is the sign bit of B
$900
4
A
Result high
Note that as the sign bits are stored separately A, Q and B are all 8-bits wide so the
$900
sequence counter (SC) described in the book will be initially loaded with 8. (SC<- n,
5
Q
not SC<-(n-1))
$900
6 8-bitBdivision
16 by
An algorithm for division is given on p. 345. Write the program for 16 by 8-bit
division, keeping in mind that the signs of operands are stored separately.
Some notes on the algorithm:
 Checking for divide overflow can be done much more easily with a test and
branch instruction of 68HC11.
 During the division of magnitudes, as the operands are 8 bits (signs are stored
separately) we cannot decide that a>=B by inspecting E after shlEAQ. Therefore
use a compare or test and branch instruction here.
$900
1 XXXXXXXAs As is the sign bit of A
$900 XXXXXXXQ
2
s
Qs is the sign bit of Q
$900 XXXXXXXB
3
s
Bs is the sign bit of B
$900
4
A
$900
Floating
Point
5
Q Normalization
$900
6 WriteBa routine to normalize the input floating point number. The mantissa
and
$900the exponent are passed at $9007 and $9008 respectively (in interface
registers).
After normalization,
the result
6
DVF
Divide overflow
flag will be at the same address.
62
Floating Point Multiplication
The multiplication algorithm given on p.384 will be implemented. Note that as
the sign bits are stored within the mantissa, multiplication needs a little bit care.
Interface registers are:
$900
9
$900
A
$900
B
$900
C
$900
D
$900
E
B
Mantissa of multiplicand
b
Exponent of multiplicand
Q
Mantissa of multiplier
Q
Exponent of multiplier
A
Mantissa of product
A
Exponent of product
63
2. EXPERIMENTAL WORK
Write and test the arithmetic library you have prepared. For testing the
operations, you can manually write some input data into corresponding interface
registers and execute the user program.
Prepared by ERKAN ÜNAL Spring 1990
Re-edited by ERDEM AKAGÜNDÜZ Spring 2003
64
EXPERIMENT 7
INTRODUCTION TO MULTITASKING CONCEPT
AND ROUND-ROBIN SCHEDULING
1. BACKGROUND INFORMATION
1.1
MULTITASKING OPERATING SYSTEMS
Operating system (OS) is a program which is an interface between
computer system users and computer hardware. It performs resource
allocation fairly and efficiently. Operating system constitutes an interface
between users and hardware such that users do not have to know the details
of the hardware. The OS’s such as CP/M and MS/DOS are for single-user
microcomputer systems and they can execute a single task at a time. On the
other hand, OS’s such as UNIX may execute multiple tasks concurrently.
Apple-OS, Linux, Windows are popular multitasking OS’s for real time
applications.
Task, or process, is a program which performs a specific job. It is not
necessary to have multiple processors in the system for executing tasks
concurrently. One processor may be shared among the tasks by the OS. The
idea of multitasking is simple: A task is executed until the point it must wait,
typically for the completion of some I/O request. In a simple computer
system, the processor would just sit idle during I/O. All of this waiting time is
wasted and no useful work is accomplished. With multitasking, we try to use
this time productively. Several tasks are kept in memory at a time. When one
task has to wait, the OS takes the processor from that task and gives it to
another task. Every time a task has to wait, another task may take over the
use of the processor. In this manner processor utilization is increased. Also,
multitasking capability enables the partitioning of complicated jobs into simple
tasks which can be implemented individually.
The multitasking OS should support some mechanisms to share the
system resources –other than the processor- such as memory, I/O devices,
data and programs.
Main modules of a multitasking OS can be listed as follows:
 Processor scheduler
 Memory management module
 I/O management module
 Inter-task communication and synchronization module
In this experiment, only the processor scheduler module, which
performs the allocation of the processor among tasks, will be discussed.
EE-446 LABORATORY
65
1.2
PROCESS STATES
A task is in one of three basic states in a multitasking environment:
Running, Ready, Waiting.
At most one task can be executed at a time in a single processor
system. The task in execution is in running state. A task is in ready state
when it is not being executed, and it is waiting for the processor in the ready
queue of processes. A task which is waiting for a system resource other than
the processor or for an event (a release of a resource, or I/O completion) is in
wait state.
For simplicity, WAIT state will not be considered in our experiment; all
tasks will be assumed to be in READY state.
Scheduling is a decision policy for selection of a READY task to become
RUNNING. Scheduler also determines when a RUNNING task releases the
processor for another task. There are various scheduling policies with
different properties. However, it is possible to divide them into two main
groups: Preemptive & Nonpreemptive Scheduling.
A task running under the control of a nonpreemptive scheduler does
not release the processor until it completes its task. In a preemptive system,
the RUNNING task may be preempted before the completion of its task, and
processor is given to another READY task. It doesn’t matter whether the
RUNNING task has completed its operation or not.
Some well-known scheduling algorithms are First-Come-First-Served,
Shortest Process First, Longest Job First, Preemptive or Nonpreemptive
Priority-Based Scheduling, and Round-Robin Scheduling.
1.3
ROUND-ROBIN SCHEDULER
Round-robin scheduler allows a task to run for a specified period of
time. At the end of the determined time interval, it is placed at the end of the
ready queue. The processor which is the head of the ready queue, is taken
from the READY queue (it will be RUNNING in a moment!) and it gets the
processor even if the preempted process has not finished its task.
Time slice (or, so-called time quantum) for each task may be different
according to the importance of a task if priorities are assigned.
In our experiment, we will prepare a round-robin scheduler mechanism
with 32 msec time slice. At the end of each 32 msec slice, context switching is
performed. If this round-robin scheduler is used in a system with three tasks
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66
(T1, T2, T3), the execution of tasks and their states will be as shown in
Figure 7.1.
Figure 7.1. Round-robin scheduling with three tasks
First, T1 begins execution. When t=32 msec, T1 is suspended and put
at the end of the READY queue. At the same time, first task in ready queue
(T2) enters RUNNING state. Task switching continues in this manner.
Completion of a time slice may be informed by a timer which generates a
hardware interrupt periodically. When a task is suspended by means of an
interrupt, its current context should be saved, then at the beginning of
another time slice of the same task, previous context should be restored such
that the task should resume its execution from the point at which it stopped.
See Figure 2 for the diagram illustrating “READY / RUNNING” transition.
Figure 7.2. Context switching
Context switching time is the time required to save context of a task
(process state, program counter and registers) and to load the context of
another process. For high performance of a round-robin scheduler, time slice
should be selected such that it is much greater than context switching time,
and greater than most (~ 80%) of the processor execution times of tasks.
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1.4
ROUND-ROBIN SCHEDULER OF THE EXPERIMENT
For each task, a 20-Byte stack area will be allocated, beginning from
memory location $B000 (see Figure 7.3). Each task will use its private stack
area if it performs any stack operation. Context of the preempted task will be
saved into its private stack area. When an interrupt occurs, IHR (Interrupt
Handling Routine) should save the content of the stack pointer (SP) to the
memory locations reserved for the suspended task. Then, next task in
READY queue will be selected, and this task will begin to execute by
restoring its context from ITS stack. Concurrent execution of tasks begins by
means of initialization routine. This routine initializes the stacks and other
data structures such that each tasks seems as preempted just before it
begins to execute its first instruction.
EE-446 LABORATORY
68
SP points the first free RAM location in the stack. Note that SP moves
in the direction of the decreasing memory addresses. See Figure 7.4. When
data is pushed onto stack, SP moves upward, towards smaller addresses.
The incoming interrupt saves registers and context to the stack as shown
in the figure.
The timer system is based on a free-running 16-bit counter with a
four-stage programmable prescaler. A timer overflow system is present to
check whether the timer has restarted or not. The 68HC11 has many timer
functions beyond this, but in this experiment we will use only the timer
overflow system. Refer to Figure 7.5 for details.
Figure 7.5. Timer overflow system of 68HC11
The free running counter starts from $ 0000 as the MCU comes out of
reset and then counts up continuously. When the maximum count is reached
($ FFFF), the counter rolls over to $ 0000, sets an overflow flag, continues
counting up. As long as the MCU runs, there is no way to reset, change, or
interrupt the counting of this counter.
A programmable prescaler allows the user to select one of four
clocking rates to drive the 16-bit timer counter. This choice allows the
programmer to make a trade-off between timer resolution and timer range.
The fastest rate causes the timer counter to clock at the E-clock rate, which
results in a timer resolution of 500 ns and a timer range of 32.77 msec
between overflows (E=2 MHz in our boards).
To obtain the timer overflow interrupt that we need for context
switching, we need to make some configuration. Things that should be done
are (See also Figure 7.7):
 Prescaler adjustment (Write to PR1:PR0 in TMSK2 register)
 Enable overflow interrupts (Write a one to TOI in TMSK2 register)
 Clear overflow status bit (Write a one to TOF in TFLG2 register)
Also, every time the counter rolls over (i.e. we experience a timer
overflow interrupt) the overflow status bit must be cleared to tell the
MCU that we are aware of the overflow and to receive only one interrupt
because of the overflow. Figure 6 illustrates some timer values. For more
information, refer to the M68HC11 reference manual, Section 10: Main Timer
and Real Time Interrupt.
EE-446 LABORATORY
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Figure 6. Information about 68HC11 timer
Figure 7.7. 68HC11 Timer interrupt mask & flag registers
Since we are building an operating system, we need high timer
resolution to give the user a continuous operation sense. Thus, we need small
overflow time. To achieve the fastest rate, we clear PR1:PR0 bits (see Figure
6). This means that we give 32.77 msec to every task.
EE-446 LABORATORY
70
2.
PRELIMINARY WORK
2.1
DESCRIPTION
TASK CONFIGURATION DATA STRUCTURE:
This data structure indicates the number of tasks (NOT) in the system
and their beginning addresses (BAT[.]). It may be considered as an input
of scheduler.
Address
length (in Bytes)
NOT
$ 0000
1 {number of tasks in the system}
BAT[1]
$ 0001
2 {beginning address of task 1}
BAT[2]
$ 0003
2 {beginning address of task 2}
:
:
:
:
:
:
SCHEDULER DATA STRUCTURE:
This data structure indicates the RUNNING task (RT) and the address
of the top of the stacks in READY state (SPT[.]).
Address
length (in Bytes)
RT
$ 0100
1 {ID of the running task }
SPT[1]
$ 0101
2 {stack pointer of task 1}
SPT[2]
$ 0103
:
:
:
:
:
:
EE-446 LABORATORY
2 {stack pointer of task 2}
71
2.2. ALGORITHM
INITIALIZATION:
1. RT  1
Select task 1 as the first running task.
2. SPT[i]  (B000 + (i x 20) - A) , i = 1, 2, …., NOT
Allocate a stack for each task.
3. MEMW[(B000 + (i x 20) - 2)]  BAT[i] , i = 1, 2, …., NOT
MEMB[(B000 + (i x 20) - 9)]  00 , i = 1, 2, …., NOT
Initialization of initial context of tasks: locations reserved for PC, points the
beginning address of the task and CCR is cleared to enable interrupt. Do not
care the initial values of other registers.
4. CLI ; “clear interrupt” so that interrupt is enabled.
5. SP  SPT[1] , RTI
Load the SP of task 1 to the stack pointer register and begin executing
it by restoring its initial context with RTI instruction.
ISR:
1. SPT[RT]  SP
Save the SP of the interrupted task.
2. RT  RT + 1
IF (RT = NOT + 1) THEN RT  1
Select the next task for execution.
3. SP  SPT[RT] , RTI
Execute selected task by restoring its context from its stack.
NOTE: For this algorithm,
 All numbers are in Hex form,
 MEMB[i] denotes a single byte data at memory location (i),
 MEMW[i] denotes a double byte data at memory locations (i) and (i + 1),
 SP stands for the stack pointer register of the processor.
1. Write INITIALIZATION and ISR subroutines.
2. To test the operation of the scheduler, three programs, which will
be used as TASKS, are given in Appendix. Examine and understand
the operations of those programs.
EE-446 LABORATORY
72
3. EXPERIMENTAL WORK
Load your scheduler and programs given in appendix. Run them
concurrently and check the operation of your scheduler.
EE-446 LABORATORY
73
APPENDIX
RT
SPTBASE
NOT
BATBASE
loop1
loop12
loop11
loop2
loop22
loop21
loop3
display
loop32 l
loop31
EQU
EQU
EQU
EQU
$0100
$0101
$0000
$0001
org $a000
ldaa #$3F
ldab #$FF
decb
bne loop11
deca
bne loop12
ldaa #$07
jsr $ffb8
bra loop1
; Task-1 : ‘Beep’ sound is created
; Commands to create a time interval
org $a100
ldaa #$FF
ldab #$FF
decb
bne loop21
deca
bne loop22
ldaa #$65
jsr $ffb8
bra loop2
; Task-2 : ‘e’ is displayed on the screen
; Commands to create a time interval
org $a200
ldaa #$7F
; Task-3 : A ‘1’ and a ‘0’ is displayed on LEDS
; Do not forget: PA6 (pin 28) is connected to a LED
dab #$FF
decb
bne loop31
deca
bne loop32
ldaa #$40
eora $1000
staa $1000
bra loop3
; The output changes between 0 and 1 repeatedly
; ASCII Beep has the Hex equivalent $ 07
; OUTA subroutine
; ASCII Beep has the Hex equivalent $ 07
; OUTA subroutine
;
;
;
;
The address of PORT-A register is $ 1000.
Bit 6 of port A is complemented,
i.e., it is “ex-or”ed with a 1 ( a  1 = a’ )
Note that Binary(01000000) = Hex (40)
org $00d0
jmp ISR
org $8000
lds #$9000
ldaa #$80
staa $1024
staa $1025
sei
INIT
…………… (write your INITIALIZATION subroutine)
……………
……………
……………
EE-446 LABORATORY
74
ISR
cli
lds $0101
rti
; load first task's SP (there should be at least one task)
jsr $ff7c
; buffalo prompt
sei
…………… (write your INTERRUPT SUBROUTINE)
……………
……………
……………
ldaa #$80
; this part should be repeated here
staa $1024
; because interrupt flags are to be cleared
staa $1025
; after $ 0000 - $ FFFF count
cli
rti
; back to the execution
Prepared by
LEVENT ÖZAª
May, 1987
Updated, and Adapted to 68HC11 by
Alper BEREKETLİ & Mehmet Nazir KAÇAR
April, 2003
EE-446 LABORATORY
75
APPENDIX
A.1. IC DATASHEETS
A.1.1. 74LS00 (Quad 2-Input NAND Gates)
A.1.2. 74LS04 (Hex Inverters)
A.1.3. 74LS10 (Triple 3-Input NAND Gates)
EE-446 LABORATORY
76
A.1.4. 74LS30 (8-Input NAND Gate)
A.1.5. 74LS138 (3-to-8 Decoder/Demultiplexer)
A.1.6. 74LS240/244 (Octal Inverting/Non-inverting Buffer/Line
Drivers with 3-state outputs)
h
EE-446 LABORATORY
77
A.1.7. 74LS373/374 (3-state octal D-transparent latches/Edgetriggered flip-flops)
EE-446 LABORATORY
78
A.2. THE 6811 CONNECTOR CABLE PINOUT
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79