Q1A :by entering into microprocessor age , narrate the history of microprocessor evolution and revolution your own words . While going through this evolution and revolution, compare:
- Word length -clock speed -addressing range - number of transistors - major application- execution speed in terms of MIPS and cache memory for the following microprocessors:
Answer:
Word length
Clock speed Addressing
Range
Number of transistor
Intel 4004 4 bit 1MHZ 4 byte 2,300
Intel 8080
Motorola 6800
Intel 8086
8 bit
8 bit
1MHZ
1MHZ
16 bit 4.47-10MHZ
64KB
64KB
1MB
Pentium with MMX 32 bit 66-200MHZ
Pentium III xeon 64 bit 600MHZ
Pentium IV 64 bit 2.3GHZ
Major appl.
MB
MB
MB
Intel 4004
150,000
150,000
30,000
1900000
>3,000,000
>3,000,000
Execution speed in terms of MIPS
50 KIPS
Cache memory
8 KB
Intel 8080
Motorola 6800
Intel 8086
Pentium with MMX
Pentium III xeon
Power tool controllers , simple controller and computer peripheral
Toys ,video games, programmable robots, video display, printer
Personal computer, telephone
,TV.
Networking/servers and pc
Networking and server computer
Personal computer and networking
Video conferencing
MIPS
MIPS
2.5MIPS
MIPS
MIPS
MIPS
16KB
8 KB
16KB
16KB
512KB, 1MB
512KB,1MB Pentium IV

Q1 B : what is the key characteristic that differentiates an 8-bit microprocessor from a
16-bit microprocessor? What other differences typically exit between the two classes that are not specifically related to word size ?
Answer:
8-bit microprocessor:
Word size is 8-bit, that can address up to 64k, and its compatible with
TTL, the first 8-bit µp is 8008.
16-bit microprocessor: word size of 16-bit µp is 16-bit, it can address up to 1MB
(1024K),its faster than 8-bit µp, speed of 60 to 233 MHz, 16-KB Cache Memory (8 k for instruction +8k for data), it has more instruction than 8-bit µp. the first 16-bit µp is 8086.
Q2 (a): literature on specific microprocessor contains several common features . by
Exploring the data sheets write down the information about :

Microprocessor Architecture

Instruction Set

Minimal system using microprocessor

Control Signals

Pin functions
Answer

Microprocessor architecture : No of register (ACC,IR,PC,SP) Address bus/ data bus size and control unit and ALU ,flags

Instruction set : listing of operation microprocessor van perform
LDA, STA, ADD, MOV, JSR, BSR, JMP, LSL, NADA

Minimal system using this microprocessor: how other devices are connected with microprocessor? Example … minimal system containing MPU, ROM, RAN, I/O
PORT, CLOCK, ADDRESS DECODER, power supply.

Control signal : write /read, CS ,interrupts (these signals directed other IC

Pin function : address pin, tat pins, control pins, power supply, clock I/P ,interrupts serial data I/O

Q2(b) : Briefly define the role of following registers of 6800 microprocessor :

Program Counter

Instruction Register

Accumulator Register
ANSWER:
Program counter: program counter is 16 bit register that always hold the address of next instruction to be executed.
Instruction register: it is special purpose register to hold the instruction fetched from memory.
Accumulator register: accumulator register hold the data for manipulation like logic
,store, output, input ,arithmetic ,load
Q2(C): Briefly define following pin function of 6800 microprocessor :

DBE

R/W

CLOCK

TSC

IRQ

RESET
Answer:
1.
DBE data bus enable pin number 36:
This pin input controls the data bus drives in the 6800 microprocessor, A high input on the
DBE pin enables the data lines, whiles a low input disables or three –state the data lines , because data transfers to and from memory and I/P occurs during the time the Q2 clock is high
,the DBE pin is many times connected to the Q2 lines of the clock.
2. R/W: read/write control, pin number 34:
This pins output is control line that signals an external device (Ram, Row, PIA, Whether the
6800MPU is reading or writing. A HIGH output from the R/W line signals a read whereas A
LOW output signals that a write operation is under way.
3. CLOCK (Q1 and Q2) pin number 3 and 37
These input pins receive non overlapping clock signals from the external system clock circuitry.
4. TSC Three state control pin number 39
When the TSC input pin is driven high by an external device , all address lines and R/W line will be three stated. The TSC line is used with DMA configurations. When DMA Is not used the TSC pin may be grounded.
5. IRQ Interrupts request line
The microprocessor can be interrupts from the normal execution of instruction and asked to execute some other instruction.
6. RESET:
When reset pin id driven from high to low, the 6800 microprocessor sets the I flag to 1 and jumps to the rest or restart interrupts service routine pointed to by FFFEH AND FFFFH.
The reset input is typically used to initialize or restart the system.

Q3 (A): Program can generally be developed much faster using high –level languages than using assembly languages. You have to counter this advantage with number of advantage assembly languages.
The high level language is a medium of communication that is independent of a given computer. Programs are written in English – like words, and they can be executed on a machine using a translator (a Compiler or a translator), they are easy to understand.
The program written in high level language when converted into machine code by the compiler , yields many unnecessary instructions , the program written in directly in assembly language is usually is usually shorter and faster than the one converted from a high level language by the compiler.
Q3 ( B): Briefly describe pipeline architecture of 8086 microprocessor. Mention the jobs performed by Bus Interface Unit (BIU) &Execution Unit (EU).
The only difference between the 8086 and the 8088 microprocessors is that BIU of 8088 can transfer only 8 bits data at one time.
Two main parts to the microprocessor
1The bus interface unit (BIU)
2The execution unit (EU)
Jobs performed by bus interface unit ( BIU ):

It is interface to the outside world.

It is performs BUS operation such as
1.
instruction fetching
2.
reading operand from memory
3.
reading operands to memory
4.
Inputting or outputting data to I/O peripherals.

Its jobs also include instruction queuing & address generation.
Jobs of execution unit:

Fetching instructions.


Fetching operands from general purpose registers

Executing instructions

Generates operand addresses & passes them to the BIU.
Q3 C : Draw the software model of 8086 microprocessor .
Q4 (A) : What is the word shown in figure below ? Express the result in hexadecimal form . Is it stored at even or an odd address boundary?
Address Memory
(Hex) (Binary)
0072C 1111 1110
0072B 1010 1010
Answers
The most significant byte of the word is stored at address 0072C and equals to
11111101= FD H
Its least significant byte is stored at address 0072B and is
10101010=AA H
Together these two byte give the word
11111101101010101= FDAA H
Expressing the address of the least significant byte in binary from gives
0072B= 00000000011100101011
Since the rightmost bit (LSB) is logic 1 , the word is stored at an odd address boundary in memory.

Q4 (b): what would be 'offset' required to map to physical location 002B3(16) if the segment base address is 0029 (16).
Answer:
= 002b3 -0029= 0299H
PA= 002B30
SR= 0029
--------------------------
0029 H
Q4 (C): calculate the value of the physical address that follows. Assume all number as hexadecimal umbers.
(1) A200: 12CF (ii) B2C0:FA12
(1) A200:12CF
A2000
12CF
----------
A32CFH
(d) B2C0:FA12
B2C00
FA12
-----------
C2612
Q4 (D): A data segment is to be loaded from address A0000(16) to AFFFF(16) . what value must be loaded in to DS?
Address is: 0000 H
Q 4 (C) : How large is the 8088 memory address space?
1 M byte.
Q5( A): A microprocessor- based weighing bridge in a sugar mill requires 4K memory plus 2 I/P &2 O/P ports. Choose a suitable memory allocation to minimize the I/P &O/P address decoding for this up –based system .draw neat &clean diagram showing the connectivity of microprocessor with program memory, address decoder ,and I/P ports .
Solution
Program required = 4k
This can be stored within bottom 32 k
Then
A15 = 0 Then ROM will selected
=1 Then I/O is selected.

A0 A1
0
0
0
1
Are decoded to select one of 4 interfaces
I/P1 is selected
I/P2 is selected
1 0 O/P1 is selected
1 1 O/P2 is selected

A2- A14 are not connected to I/O interface
A15 A14 A13
A12…………….A3 A2
A1 A0
0 X X
XX…………XX
X X
1 X X
XX…………XX
X 0
SELECTED
X ROM/RAM
MEMORY
0 I/P1
1 X X
XX…………XX
X 0 1 I/P2
1
1
X
X
X
X
XX…………..XX
X 1
XX………….XX
X 1
0
1
O/P1
O/P2

] Q6 (A): Distinguish between data addressing modes & memory addressing modes?
Answers :
The data- addressing modes include register operand addressing mode, immediate operand addressing mode where the operand to access is specified as residing in an interval registers of the microprocessor while memory address mode a physical address (PA) of the operand and the initiate a read or write operation to this storage location.
PA= segment base: base +index +displacement
Q6 (B): Identify the addressing modes used for the source and the destination operands in the instruction that follow:
(i) MOV AL,BL
(ii) MOV AX,OFF H
(iii) MOV [DI],AX
(iv) MOV DI,[SI]
(v) MOV [BX+SI],BP
(vi) MOV CL,[BX+4]
(vii) IN AL,P8
(viii) OUT DX,AX
(ix) MOV ARRAY [BX+SI],DX
(x) MOV EAX,[BX]
Answers:
Instruction Sources Destination
1 MOV AL , BL Register Register
2 MOV AX,OFF H Immediate Register
3 MOV [DI],AX Register Indirect
4
5
MOV DI,[SI]
MOV [BX+SI],BP
6 MOV CL,[BX+4]
7
8
9
IN AL,P8
OUT DX,P8
MOV ARRAY[BX+SI],DX
10 MOV EAX,[BX]
Indirect
Based index
Relative
Immediate
Immediate
Register
Indirect register register
Register register
Based relative index
Scaled index register

(c) What is label? What do the symbol [ ] indicate?
Label: the left most fields which are used which is used to store a symbolic name for memory location that it represents all labels begins with a letter or special character.
The [ ] symbols denote indirect addressing
Q # 7
Explain the indexed addressing mode and based indexed addressing mode.
Give illustrative example in each case.
Index addressing mode:
Index addressing mode:
Uses the value of the displacement as a pointer to the starting point of an array of data in memory, and the contents of the specified register as an index that selects the specific elements in the array that is to be accessed.
Eg: MOV AL, [SI] +2000H
SS 8-bit,
PA= ES : DI + 16-bit
DS SI Displacement
CS
Base- indexed addressing mode:
Combining based addressing mode together with indexed addressing mode, can be used to access complex data structure as two dimensional arrays.
Eg: MOV AH, [BX] [SI] +1234H
CS 8-bit,
PA= DS : BX + S I + 16- bit
SS BP DI Displacement
ES
Q. # 08 (A) Write a short program to transfer a word from an input device whose address is 10A0 H, into DX.
IN AX, 10AOH
MOV DX, AX

(B) Provide a complete interpretation of the content of CS: 0050 H , including an appropriate diagram.
The source segment base value is the code segment CS register and the source of the offset is
0050H so the PA = CS:0050H
Q # 09 (A) List the differences between 8086 and 8088 microprocessor.
The only difference between an 8088 microprocessor and an 8086 microprocessor is the BIU.
In The 8088, the BIU data bus path is 8 bits wide versus the 8086's 16-bit data bus. Another difference Is that the 8088 instruction queue is four bytes long instead of six.
The important point to note, however, is that because the EU is the same for each processor, the Programming instructions are exactly the same for each. Programs written for the 8086 can be run On the 8088 without any changes.
Q #09 ( b) Is 8086/8088 TTL compatible? Explain your answer?
Yes, 8088/8086 microprocessor is compatible. if the noise immunity figure is de-rated to 350 mv from 400 mv.
( C ) What information appears on the address / data bus of the 8088 while ALE is active?
Address bits A
7
-A
0
( D ): Explain the operation of the TEST pin and the wait instruction?
TEST pin is input which is tested by WAIT.

( E ) Describe bus buffering and latching.

Before the 8088/8086 microprocessor can be used with memory or I/O interfaces, their multiplexed bus must be demultiplexed.

Buses need to be buffered for large systems. Because the maximum fan-out is 10, the system must be buffered if it contains more than 10 other components.

74LS 373 Latches are used to demuliplex the address /data bus (AD7_ AD0) connection and multiplexed address/status connection ( A19/S6 – A16/S3 )
Q# 10 (A) Why it is essential to understand bus timing ? Draw a block diagram in which clock generator (8284A) and 8086 microprocessor illustrates the connection for the clock and reset signals.
It is essential to understand bus timing before choosing a memory or I/O device for interfacing with 8086/8088 microprocessor, and it is provides insight into the operation of the bus signals and basic read and write timing of the 80886.8088.

( b) illustrate and explain simplified 8086/8088 write bus cycle.
The three buses of the 8086 and 8088 address bus ,data mcontrol fuction exactly the same way as those of any other microprocessor .if data are written to the memory , the microprocessor outputs the memory address on the addressbus,oututs the data to be written into memory on the data bus , and issue a write ( WR) to memory and =0
=1 for the 8088 . The 8086 and
( c ) compare minimum mode versus maximum mode of operation for the 8086/8088 microprocessor
There are two available mode of the operation for the 8088/8086 microprocessor, Minimum mode and Maximum mode. Min mode is obtained by the connection of the selection pin
MN/MX to + 5 v and max. Mode is selected by grounded.
Maximum mode is used when ever a coprocessor is connected to the system.
In Minimum mode the signal of the I/O is generated by the processor so it costs less minimum mode allow the eight – bit peripherals to be used with the 8088/8086 without any special consideration.
Q #. 11 (a) Explain the characteristics of I/O interface
Interface devices are grouped according to several different characteristics
1. Analog/Digital : if the device uses a digital data format this simplifies the interface to the computer, but most nature signals occur naturally in analogue form. There is need to process signals using an A/D converter ( I/P) and D/A converter (O/P) in order to connected the computer/ microprocessor to the outside world.
2 - Electrical characteristics: of the device to be connected to the to the computer may vary enormously.

3- Operating speed : the speed of operation of the device affects the interface design
4- Data availability: the interface may be able to provide or receive data continuously or data transfer may be restricted to discrete time intervals.
5 . Data timing: data may need to be transmitted to or received from the computer at regular time intervals or irregularly.
(b) Contrast a memory mapped I/O system with an isolated I/O system
Memory mapped I/ O: any instruction that reference to memory can accomplish the I/O transfer.
Isolated I/ O : the data transfer between microprocessor and the I/O device takes places using special I/P instruction IN & OUT
( c ) Explain the term handshaking as it applies to computer system.
Handshaking :
Many I/O devices accept or release information at a much slower rate than the microprocessor; another method of I/O control called Handshaking or polling synchronizes the I/O device with the microprocessor. An example device that requires handshaking is a parallel printer that sends 100 cps . its clear that the processor can send 100
CPS to the printer , so to slow the processor down to match the speed of the of the printer .
The computer printer devices is facilitated using parallel I/O device PPI .As the printer is an output device , one can program port B of PPI as output port in handshake mode ( i.e. mode 1 ) in this case m few lines of port C serve the purpose of handshake line , where as the printer can intimate the computer about its status on port A of PPI , which is programmed as simple input in mode 0 . the printer port physically appears to the near of CPU casing as female D-Type 25
Pin connector .

( d ) Draw the I/O map of personal computer illustrating many of the fixed I/O areas.
Q# 12. ( a ) write a series of instruction that will output AA16 to an output port located at address C000H of the I/O address space
SOLTION
MOV DX, C000 ; DX register must be loaded with address of the output port .
MOV AL, AA ; Data to be output must be loaded into AL.
OUT DX, AL ; Data is sent at output address C000H.

( b ) suppose data are to be read from two byte wide input ports at address FF H and A9
H respectively and then output as word wide output as word output port at address
FAFD H . Write a sequence of instruction to perform this input/output operation.
Solution:
IN AL.AA ; first read byte from the port address AAH into AL.
MOV AH, AL ; and move it to AH
IN AL, A9 ; other byte can be read into AL
MOV DX, FAFD ; load DX with variable address
OUT DX, AX ; send contents of AX at output FAFD
Q# 13 ( a ) the 82C55 PPI has how many programmable I/O PIN CONNECTION . list the pins that belong to group A & group B in the 82C55. Also mention two pins which accomplish internal I/O port section.

The 82C55 has 24 programmable I/O.

Group A consist:
1port A
2upper half of port C (PC7-PC4)
3A1,A0,WR

Group b consist from :
1port B (PB7-PB0)
2 lower half of port c(PC3-PC0_
3RD
4RESET
5CK
6VCC
7 GND
. Two pins accomplish internal I/O port address is A0 and A1

(b ) what three modes of operation are available to the 82C55 PPI? Mention the purpose of STB signal is strobes input operation of the 82C55
Mode 0: Latched I/O
Mode 1: strobes I/O
Mode2: bi-directional I/O.
(c) How is the interrupt request pin (INTR) enabled input mode of operation of the
82C55?
The INTR pin becomes logic 1 when the STB input returns to logic 1, and it is cleared when the data are input from the port by the microprocessor.
(d) In strobe output operation of the PPI, what is the purpose of ACK signal?
The ACK signal is an output that signals that the data have been removed from the port.
Q.# 14 By considering all aspects of microprocessor based application design explain
- System specification
- block level system design
- Software design
- Hardware design
- Hardware and software integration
-prototype
SYSTEM SPECIFICATION:
The specification states that functions that the system must perform but does not necessarily cover how the functions are implemented.
BLOCK DIGRAM:
This includes:

Selecting microprocessor type

Determination of I/O and memory requirements

Division of tasks between hardware and software
Software design:

It is often proceeds in parallel with the hardware design.

The software may be written in assembly language or in a high level language or in combination of two.

Depending on the type of the computer used for the software development, it may be possible to debug parts of the software with out hardware.
HARDWARE DESGIN
It consists of selection of:

Microprocessor

Memory (RAM & ROM )

Peripheral IC's

Design circuitry to connect them together to from the system
HARDWARE & SOFTWARE INTERGATRION

Hardware debugging usually begins by testing the system with short test programs


After the hardware is able to execute these test program the hardware /software integration begins.

The actual application software replaces the test programs and the complete system is debugged.

This can be cheapening task, since there are often both hardware and software problems to be found and is not always clear which it which.

Several types of test equipment are available for assisting in this process:
1LOGIC ANALYZER: which captures a trace of the bus activity and displays the sequence of bus cycles that were executed?
2IN CIRCUIRT EMULATORS : which pugs into the microprocessor socket and allows the operation of the system be controlled and monitored.
Q. # 15 (a) Discuss the function of an interrupt in a microprocessor based system and explains the interrupts structure of the Intel family of microprocessors
1) interrupts provide a mechanism for changing the program environment.
2) Transfer program control is initiated by the occurrence of an event internal to the microprocessor or an event in its external hardware .
3) For instance when an interrupt signals occurs indicating that an external device , such as printer , requires services , the microprocessor must suspend what it is doing in the main part of the program and pass control to a special routine (Interrupt services routine
) that performs the function required by the device .
4) When the microprocessor terminates execution in the main program, it remembers the location where it left off and then it picks up execution with first instruction in services routine. After this routine run to completion, program control is returned to the point where the microprocessor originally left the main body of program.
5) Interrupts are practically useful when interfacing I/O device that provide data at relatively low data transfer rates.
The interrupts of the entire Intel family of microprocessor include :
Hardware pins that request interrupt (INTR & NMI) and one hardware pin (INTA) that acknowledges the interrupt requested through INTA.
In addition to the pins , the microprocessor also has software interrupts
INT,INTO,INT3, and BOUND
Two flags bits , IF ( Interrupt flag) and TF ( Trap flag) , are also used with the interrupt structure and a special return instruction IRET ( or IRED in 80386/higher )
Hardware , software , and internal interrupts are serviced in priority basis.
Internal interrupts are the highest priority group.
Next lowest is the nonmaskable interrupts.
Next lowest is software interrupts
External hardware interrupts are the lowest priority group.

(b) Explain the operation of software interrupts instruction INT, INTO, INT3 &
BOUND.
Answer:
INT: INT instruction calls the interrupts service procedures that begins at address represented in vector number
INTO: INTO instruction checks the overflow flag (OF), if OF =1, the instruction calls the procedure whose address is stored in interrupt vector type number 4.
If OF = 0, then the INTO instruction performs no operation and next sequential instruction in the program executes.
INT3: INT3 instruction is often used as a breakpoint interrupt because it is easy to insert a 1byte instruction into a program, breakpoints are often used to debug faulty software.
BOUND: The BOUND instruction which has two operands, compares a register with two words of memory data for example, if the instruction BOUND AX, DATA is executed, AX is compare with the contents of DATA and DATA +1 and also with DATA+2 and DATA+3 if
AX is les than the contents of DATA and DATA+1. the type 5 interrupt occurs. If AX is greater than DATA+2 and DATA +3 , a type 5 interrupt occurs. If AX is within the bounds of these two memory word no interrupts occurs.
( c ) what is 8295A? Also mention how many 8295 a are required to have 64 interrupt inputs.
8259A is programmable interrupts controller that adds eight interrupt inputs to the microprocessor.
It required a master 8295A and eight 8295A slaves.
Q. # 16 ( a ) The interrupt vectors and vector table are crucial to an understanding of hardware and software interrupts .At what memory address is the interrupts vector table is located?
In the first 1 k byte at location 00000000 H-000003FFH
( b ) describe the function of the following dedicated interrupts of 8086 microprocessor:
Divider Error
Single step or trap
Over flow
Bound
Answer
Type 0 _ Divider Error: Occurs whenever the result of a division overflows or whenever an attempt is made to divide by zero
Type 1 – Single step or Trap: occurs after the execution of each instruction if the trap
(TF) flag bit is set. Upon accepting this interrupt the TF bit is cleared so the interrupt service procedure executes al full speed.
Type 4 – overflow: is a special vector used the INTO instruction. The INTO instruction interrupts the program if an overflow condition exits as reflected by the overflow flag (OF)
Type 5 –BOUND: is an instruction that compares register with boundaries stored in the memory. If the contents of the register is greater than or equal to the first word in memory and less than or equal to the second word, no interrupt occurs because the contents of the register is within bounds. If the contents of the register of the register is out of bounds, a type 5 interrupt execute

Q .17 (a) Write assembly language procedure to fill the screen with string " Advanced microprocessor system "?
Title first assembly language program
.model small
.data
NAL DB
41h,64h,76h,61h,60h,63h,65h,64h,6dh,4dh,69h,63h,72h,6fh,70h,72h,6fh,63h,65h,73h,73h,6fh,
72h,6dh,53h,79h,73h,74h,65h,6dh
.code
.startup
MOV CX, 29
MOV BX, 0H
MOV AH, 2H
Back: MOV AL, [BX] +NALO
INT 21H
INC BX
Loop back
.exit
End
(b) Explain
(I) In how many ways DMA process may be initiated and be terminated.
To initiate the DMA process, we use HOLD signal.
To terminate the DMA process, we use EOP signal.
(ii) The sequence of events as DMA is required by an I/O device.
The DMA I/O technique provides direct memory access to the memory, while the µp is temporarily disabled. This allows data to be transferred between memory & the
I/O devices at a rate that is limited only by the speed of the memory components in the system or the DMA.
This process can be done by using the HOLD pin (input) that is used to request a DMA action and the HOLD pin is an output that acknowledges.
(iii) What happens when DMAC receives DMA request from another channel while it is serving one?
The 8237 DMA controller supplies the memory and I/O with control signals and memory address information during the DMA transfer, the 8237 DMA controller is capable of
DMA transfers at rates of up to 1.6MB per sec. so, DMAC receive DMA from another channel, this means that, the channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k-bytes with a single programming.

Q. 18
The device we discussed in this lecture fall into two classes: microprocessors & single chip microcomputers (microcontrollers).
(i) What are the characteristics required chip microcomputer?
A practical µp controlled the system would almost certainly be implemented a single chip
µ-computer since the application relatively simple at high value market, so , it is possible to develop a-µp application on the MC6800,6802 subsequently to one smaller charger chip µcontroller from the same family.
6805 is suitable:
RAM (B) ROM (B) I/O clock minimum system
64 1100 20 yes one chip
(ii) The 6802 includes many of theses characteristics. Is it single chip microcomputer? If not, what is missing?
I/O, ROM is missing
Since it is 6800+clock and 128 bytes RAM
(iii) What are major advantages &disadvantages of single chip microcomputer?
Single chip has the MPU, Memory, I/O function, all integrated into a single IC.
ADVANTAGE:
Single chip microcontrollers are cheap, flexible.
DISADVANTAGE:
Limited memory & I/O lines.
Q 19 Answer briefly & accurately to following questions.
( I )What do the following MOV instructions accomplishes?
MOV AX,BX Copy contents of BX into AX
MOV BX,AX
MOV BL,CH
Copy contents of AX into AX
Copy contents of CH into BL
0
16
) ii )- List the 32 bit registers used for register addressing?
EAX
EBX
ECX
EDX
ESP

EBP
ESI
EDI
0 32
(iii):- What is wrong with the MOV BL, CX instruction?
CX is 16 bit register but BL is 8 bit register…that is not possible.
.
(iv ) - Select an instruction for each of the following tasks ?
Copy BL into CL
Copy SI into BX
MOV CL, BL
MOV BX,SI
Copy DS into AX
Copy Al into AH
MOV AX,DS
MOV AH,AI
(v )What is the purpose of .Model tiny statement?
The .Model tiny statement directs the assembler to assemble the program into single segment.
( vi ) What assembly language directive indicates the start of the code segment?
The .CODE statement or directive indicates the start of code segment.
(vii ) What is the displacement and how it is measured the memory address in a MOV
[2000H] ,AL instruction ?
Move instruction copies the contents of AL register into the 2000H.
( viii ) What is wrong with MOV [BX],{DI] instruction ?
Memory-to-memory transferred are not allowed
( ix ) What mode of operation is selected when MN/MX is grounded?
Maximum Mode
( x ) What happens when HOLD input to the 8086/8088 is paced at its logic 1 level ?
When HOLD input to the 8086/8088 is paced at its logic 1 level then HOLD input request for
DMA
( xi )Which bus connections on the 8086 microprocessor are typically demultiplexed?
8086 demultipexed all three buses: address (A
19
A
0 and BHE), data buses (D
15
D
0
) and control
Bus (M/IO , RD and WR)

(xii)Which TTL integrated circuits is often used to demultiplexed the buses on 8088 /
8086 ?
An 8 – bit transparent latch (74LS373)
(xiii) What is the purpose of the demultiplexed BHE signal on the 8086 microprocessor
?
Used for memory bank selection
( xiv ) If the clock input to the 8088/8086 is 4 MHz , how long is one bus cycle ?
250 ns
(xv )How many MIPS is the 8086/8088 capable of obtaining when operated with 10 MHz clock?
2.5 MIPS.
( xvi )How munch time is allocated for memory access when the 8088/8086 microprocessor are operated with 5 MHz clock ?
460ns
( xvii ) List the number of words in bytes or KB found in each memory device for the following no of address connections ?
8
11
256
1024
2K*4
12
13
4096
8192
( xviii ) List number of data items stored in each of the following memory devices and number of bits in each datum ?
2K memory location and 4 bits are stored in each datum.
1K*1
4K*8
16K*1
1K memory locations and 1 bit stored in each datum
4K memory location and 8 bits stored in each datum
16K memory location and 1 bit stored in each datum.
64K*4 64K memory location and 4 bits stored in each datum.
(xix ) What is the purpose of CS and CE pin on memory ?

These pins are used to select or enable device so that it can perform read or write operation.
( xx )What is the purpose of OE pin on memory devices?
The OE enables or disable a set of ti-state buffers located within memory devices & must be active to read data
(xxi )What is the purpose of WE pin on a RAM?
It cause the memory to perform write operation provided the CS or CE pin is also active
.
(xxii )How many bits of storage do the following EPROM memory devices contain?
2708
2716
2732
(1K *8) =1024 bytes
(2K*8)=2048 bytes
(4K*8)=4096 bytes
2764 (8K*8)=8192 bytes
27128 (16k*8)=16384 bytes
( xxiii )- SRAM is acronym for that type of device?
SRAM is devices that retain data for as long as power is applied to memory devices.
( xxiv )The 4016 memory has a G pin as S pin and W pin What are these pins used for
RAM?
G pin work as OE ands S pin as CS pin and W pin as WE
( xxv )how much memory access time is required by the slowest 4016 ?
250 ns
( xxvii ) DRAM is an acronym for what type of device?
Dynamic RAM (RRAM) contains data for only a short period, usually 2-4 ms. It must be refreshed periodically.
( xxvii )The TMS4464 has 8 address inputs, yet it is a 64 k DRAM, explain how many address can be forced into 8 address input?
The addresses inputs to most DRAMS derive are multiplexed. This allows the 16 bit address to be sent to DRAM through 8 address input pins.

( xxviii )What are the purposes of CAS and RAS inputs of a DRAM?
CAS and RAS are two special pins called as Column Address Strobe and Row Address Strobe.
( xxix ) How much time is required to refresh a typical DRAM?
2-4 ms
( xxx ) What is the purpose of BHE and A
0 pins on 8086 micro processor ?
The BHE select the upper memory bank and A
0 select lower memory bank.
Q No.20
What are Embedded systems? Give some Examples of Embedded systems.
What is Technology behind Embedded systems? Explain Criteria to choose a microcontroller for small embedded microcontroller based application.
[ Refer Lecture 27-28 Embedded System Design ]