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Chapter 2 : I/0 Memory Interface
POINTS TO REMEMBER
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 Home
 Topics
 Chapter 1 :
Microproces
 sor
Architecture
Chapter 2 :
Memory is. used to storing data.
I/0 Memory
Interface
 Chapter 3 :
Instruction
Set &
Assembly
Languages
Programmin g
 Chapter 4 :
Microproces sor
Developme
Types of memories:
• RAM
•ROM
RAM is a Random Access Memory or
Read/Write Memory. One can read and write in RAM.
nt System
Chapter 5 :
Case
Structure &
Microproces sor
Application
Chapter 6 :
Basic
Architect
RAM is of two types:
• SRAM
• DRAM.
SRAM : It is also known as static RAM. In
SRAM data will remain stored temporary as long as power is supplied. The basic cell in

SRAM is a flip-flop.
DRAM : It is also known as dynamic RAM. In
DRAM the basic cell is a capacitor.
ROM : ROM is the Read Only Memory. It is a permanent storage device. It is used in computers, microprocessors.
ROM is of four types
(a) Masked ROM
(b) PROM
(G) EPROM
(d) EEPROM.
(a) Masked ROM : It is stored permanently through photomasking during fabrication.
This programming is done through masking and metalization process.
(b) PROM : It is the programmable read only memory.
(c) EPROM : It is the erasable programmable read only memory.

(d) EEPROM : It is the electrically erasable programmable read only memory
DMA: It is Direct Memory Access. In this scheme, data is transferred between memory and I/O device by bypassing microprocessor.
Data transfer techniques are classified into
1. Parallel data transfer techniques
2. Serial data transfer techniques
3. Synchronous data transfer techniques
4. Asynchronous data transfer techniques
5. Interrupt driver data transfer techniques.
9. The 8251 USART supports synchronous and asynchronous modes of operation.
10. The mode word and command word for an 8251 remains same—for transmitter and receiver.

QUESTION-
ANSWER
Q 1. Write short note on semiconductor memory.
Ans. Semiconductor memory :
Semiconductor memory is used to store data. The main advantages Of semiconductor memories are
1. Small in size
2. Low cost
3. Better reliability
4. High speed.

Volatile Memory : If the information stored in a memory is lost when the electrical power is switched OFF, then the memory is called as volatile memory. These are called
RAM (Random Access Memories).
Non-volatile Memory : If the information once stored in memory does not change unless altered deliberately are called as nonvolatile memory. These are ROM, PROM,
EPROM etc.
Q 2. Differentiate between parallel data

transfer and serial data transfer.
Ans.
Q 3 Distinguish between synchronous and asynchronous data transfer
Ans.

Q 4 Define following terms
(a) Simplex
(b) Duplex
(c) Half duplex
(d) Full duplex
Ans (a) Simplex It is one way transmission on the other hand the connection in such a way that transfer data only in one direction
(b) Duplex It is two way transmission It transfer data in both direction
(C) Half duplex It is also two way transmission But it is a connection between two terminals such that, data may travel in both the directions as well as transmission activated in one direction at a time
(d) Full duplex It is a connection between two terminals such that data may travel in

both the directions simultaneously So it will contain one way transmission or two way transmission at a time
Q 5 Give the applications of 8251 programmable communication interface chip
Ans 1 8251 can be used to transmit receive serial data Data transmission to a CRT terminal using the 8251 in status check mode
2. A programmable chip designed for synchronous/asynchronous serial data communication.
Q 6. What is DMA data transfer? Explain in brief.

Ans. DMA implies direct memory access.
Either in programmed I/O or interrupt I/O transfer, the data between the I/O devices and external memory is via the accumulator.
For voluminous data transfer, there are the time commuting and even through the I/O devices speed matches with speed of UR So there is direct transfer of data directly between the I/O device and external memory without going through accumulator.
This is called DMA.
Q7. Explain what is SIM.
Ans. This is Set Interrupt Mask
• This is a 1 byte instructions.
• This instructions reads the contents of the accumulator and enables or disables the interrupts according to the contents of the accumulator.
• Bits W7 and W6 of accumulator are used

for serial I/O and do not affect the interrupts. D6 1 enables the serial I/O
Q 8. What is the last instruction executed by every interrupt?
Ans. The last operation is to retrieve the relearn address from the stack memory and loaded in the PC to contrive the main program.
PUSHCS

PUSHIP
Q.9 What is contained in interrupt vector table of each interrupt?
Ans. The interrupt vector table holds the starting address of the interrupt subroutine:
The starting address of interrupt service subroutine (ISS) is after called interrupt sector.
Q 10. Why data transfer with DMA is accelerated?
Ans. Because DMA scheme of data transfer is commonly used for high speed data transfer. For example, data transfer between the memory and a floppy disk. A DMA

controller is necessary for the DMA transfer which can allow the peripheral to transfer the data into or form the memory.
Q 11. It compare peripheral I/O and memory mapped l10 (PTU, May2007)
Ans.

Q 12 Write down the communication steps with 110 devices which are similar to those in communicating with memory (PTU, Dec 2007)
Ans The steps in communicating with an
I/O device are:
(i) The micro processing unit places an 8 bit address on the address bus, that is decoded by the external logic
(ii) The micro processing unit places an 8-bit address on the address bus, which is decoded by external decode logic
(iii) The micro processing unit sends a control signal (I/O Read or I/O Write) and enables the I/O device
(iv) Data is transferred using the data bus
Q 13 Why the number of 0/P ports in

peripheral mapped I/O is restricted to
256’
(PTU, May 2008)
Ans In I/O addressing mode 8085 has capability of 8 bit I/O address through which it can address 255 I/O ports
Q 14 Discuss DMA controller briefly
(PTU, May 2008)
Ans In I/O data transfer data is transferred by using microprocessor The microprocessor will read data from I/O device and then will write data to memory
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In this case there are two operations for single data transfer.
If the data is less, then micro process will not waste its time ; transferring data from I/O to memory or back. But suppose, data is huge, then the transfer rate from I/O to memory or back will

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 slow down because of microprocessor intervention. In such case, to speed up the process of transferring the data, we can think, Can I/O have direct access to memory and the answer is, yes.
It can have Direct memory access
(DMA), but under Supervision. The device which supervises, data transfer is named as DMA controller.
Now let’s have diagrammatic representation of the scheme, which depicts microprocessor, DMA controller, memory and I/O device.

Q 15. Name the two modes used by the
DMA processor to transfer data.
(PTU, May 2009)
Ans. 1. Burst or Block Transfer DMA
2. Cycle Steal or Single Byte Transfer DMA.
Q16. List the features of 8251. (PTU,
Dec. 2009)
Ans. Features of 8251
1. It supports both synchronous and asynchronous modes of operation.
2. The synchronous baud rate — DC to 64 K baud.
3. The asynchronous baud rate — DC to

19.2 K baud.
4. The synchronous mode supports 5-8 bits characters.
5. In asynchronous mode it supports 5-8 bits characters.
6. It contains full duplex system.
Q 17. DrawBlock diagram of 8251.
OR
What is the function of 8251 chip’
Discuss in detail (PTU, May 2008)
Ans 8251 (USART) USART is Universal
Synchronous/Asynchronous Receiver and
Transmitter 8251 supports both synchronous as well as asynchronous data transfer It contains full duplex double buffered system
It provides error detection logic, detects parity over run, framing errors It uses separate TxC and RxC clock inputs for
transmitter and receiver So transmitter and

receiver can be operated in different baud rates
Synchronous baud data rate — DC to 64K baud
Asynchronous baud rate — DC to 192 K baud
8251 Block diagram The 8251 is a 28 pin
DIP package all inputs and outputs are TTL compatible The block diagram of 8251 contains following blocks
1 Data bus buffer
2 Read/write control logic
3 Transmitter section
4 Receiver section
5 Modem control

1 Data Bus Buffer It is a 3 state bidirectional, buffer used to interface internal data bus of 8251 to the system data bus The direction of data transfer through data bus buffer is decided by and This buffer transfers control word, status word data for transmitter and data from receiver, depending on signal given by R/W control logic
2 Read/Write Control Logic This block accepts different control signals such as RD,
WR C/D CS, CLK and Reset from control bus and generate control signals for device

operation.
3. Transmitter Section: It is accepts parallel data from the data bus buffer. The contents of the transmitter buffer are automatically transferred to output register if the output register is empty. The data is shifted oUt serially on the TxD pin for asynchronous mode start bit and stop bits are added to data byte for synchronous mode synchronous characters are transferred before the data bytes.
4. Receiver Section : This section consists of receive buffer and receive control blocks.
The expanded block diagram of receiver section show 3 blocks
(a) Receiver buffer register

(b) Serial input register
(c) Receiver control logic.
5. Modem Control : For sending dat over long distances the telephone lines are used.
The telephone lines are analog in nature so
MODEM are used to convert digital data to analog data. To control MODEM, 8051 provides a block called as MODEM control.

Q 18 Draw microcomputer system using
8085 MPU, to memory (EPROM, RWM), input and output and bus linking to
(I/O and memory) peripherals to the
MPU (PTU, May 2007)
Ans.

Q 19. Differentiate and explain UART and USART in data transfer operation.
(PTU, May 2008)
Ans. UART (8250) : UART stands for
Universal Asynchronous Receiver and
Transmitter.
But now day, we generally used USART.
USART (8251) USART is Universal
Synchronous/Asynchronous Receiver and
Transmitter. Mostly we used USART, because USART supports both synchronous as well as synchronous data transfer operation. On the other hand UART supports only asynchronous communication.
Advantage of USART:
1. 8251 is mostly used for serial communication. -
2. It is sending data out, accepting data bits, generation/removing other signals etc.
3. The 8251 (USART) will convert parallel

data into serial stream and transmit on serial output line. But in case of 8250
(USART) is done in parallel mode only.
4. At the same time it can receive serial data on serial input line, converts it to parallel from then transfer to processor.
Q.20. What do you mean by. DMA?
Explain its working. (PTU, Dec. 2008)
OR
What do you understand by DMA? Draw the block diagram of 8257 and explain the function of each block.
Ans.

The block diagram of 8257 is shown in fig. different blocks of 8257 are as follows
(i) Data bus buffer
(ii) Control logic block
(iii) DMA channels
(iv) Priority resolver
(v) Read/Write control logic.
1. Data Bus Buffer:

(I) It is a tri state bi-directional buffer. In slave mode, it transfers data between microprocessor and internal bus.
(ii) The direction of data bus buffer is set by read/write control logic.
2. Control logic block:
(i) It consist of control logic, mode set register and status register.
(ii) It generates control and address signals.
(iii) It is disabled in slave mode.
(iv) It activates HRQ signal on channel DMA request.
(v) Control logic controls the sequence of
DMA operations during all DMA cycles in master mode.
3. DMA Channels : 8257 provides four different channels. Each channel consist two
16 bit registers.
(I) DMA address register

(ii) Terminal count register.
4. Priority Resolver:
(I) It consist of priority resolving logic circuit that resolves the priority of each channel.
5. Read/Write Control Logic
(i) In slave mode, it accepts address bits and controls signals from microprocessor.
(ii) It consist of flip-flops.
(iii) It oontrols all internal read/write operations.
(iv) In master modes, it generates address bits and control signals.
Q 21. Discuss the memory mapped I/O technique and its use. (PTU, Dec. 2008)
OR

Using diagram explain how many address lines are used to identity an
110 port in the peripheral I/O and in the memory - mapped I/O method.
(PTU, Dec. 2007)
OR
Draw the circuit for interfacing processor, memory and I/O devices through DMA. (PTU, Dec. 2009)
Ans. Memory Mapped I/O:
(I) Each I/O device will have 16-bit address.
(ii) The I/O devices are treated as memory locations. There will be no separation like memory and I/O.
(iii) The control signals used will be same as memory i.e. MEMR and MEMW.
(iv) The number of I/O device will be 64 KB shared by I/O and memory.
(v) For data transfer, microprocessor will send address on A0 to Al 5 lines and generates control signals or MEMR and
MEMW.

(vi) In MEMR it accepts data from I/O device while in MEMW it transfers data to I/O device.
Input/Output Interfacing in Memory
Mapped I/O
(1)The simple input device is a buffer and output device is latch. To interface these devices to 8085, the control lines 1G, 2G of buffer and G input of h cont” 8085.
(ii) The address is of 16 bits A0 to A15 and control signal MEMR and MEMW are used to control the buffer latch.
(iii) The combination of address lines A0 and A15 can be done by using NAND gates and then it is combined with MEMR and MEMW signal.
(iv) The interfacing diagram will be as shown in fig. For buffer when A0 to A15 all are l’s the output of NAND gate will be

low (0). It is combined with MEMR using
NAND gate with inverted inputs and they are connected to 1 G and 2G. So, the address of buffer with be FFFF H.
(v) For latch when A0 to A14 all are l’s and the line A15 MEMW = 0 the output of NAND gate will be low, after that it is combined with MEMW using AND gate with inverted

inputs and connected to G. So, the address of latch will be 7FFE H.
(vi) Instead of gates a 3: 8 decoder logic can be used to select the appropriate device.
Q 22. Draw the circuit for interfacing processor, memory and I/O devices through DMA. . (PTU, May. 2009)
Ans I/O Mapped The interfacing of 8085 microprocessor with 8257 chip In slave mode, the 8257 function as an I/O device
On the other hand in master mode the microprocessor must be isolated from the system bus The isolation is done by an AEN signal
(a) 8212 Latch 1 This latch is used to demultiplex ADO AD7 line of microprocessor
In this case input line is connected to an
AEN output of 8257 This latch is enabled in slave mode and disabled in master mode

Functionally, 8212 i s similar to 74373 latch
(b) Decoder Decoder IC is also used, because the 8085 microprocessor does not provide separate control signals for memory and I/O devices HGnce, a decoder is used to generate MEMR, MEMW, 1i and tOW control signals in slave mode It is disabled in master mode
(c) 8212 latch 2 It is used to hold higher byte of memory address is master mode It is disabled in slave mode 8257 Interfacing
(Memory Mapped I/O)
It is similar to I/O mapped I/O except the following connections
1 MEMR of 8257 pin is connected to the IOR of system bus
2 FOR of 8257 is connected to the MEMR of system bus
3 MEMR of 8257 is coroneted to the j5 of system bus.

4 I OW of 8257 is connected to the MEMR of system bus
A4 — A15 lines to generate signal
5. The address decoder uses
Q 23 Sketch the explain the timing diagram of an input transfer on a synchronous bus (PTU, Dec 2009)
Ans Synchronous (unconditional) type of transfer will be used when the speed of the peripheral is equal to the speed of microprocessor In this mode the microprocessor reads data from an I/O port or write data to a 0/P port The data is transferred without checking whether the peripheral device is ready or not

Timing diagram When transmission is enabled the TxD line will be made HIGH If
CTS = 0, the transmitter will start transmitting data The first character transmitted serially on TxD line is synchronous character or characters The data is loaded by CPU to transmit buffer register This data is transferred to output buffer When this transfer occurs transmitter generates a signal TxRDY This signal is used to signal CPU to send next byte of data The process of sending continuous data bits on
TxD line will continue If the CPU doesn’t send next byte of data and transmitter competes transmission of previous data byte, the TxE line is made high and synchronous characters are transmitted on line. When the data byte is loaded by CPU the transmitter will stop transmitting synchronous characters. It will reset the TxE line i.e. LOW and restart transmitting data bits on TxD line.

At the end of data byte parity bit is added.
The process repeats for each for each byte.
Other signals TxRDY bit and pin functions are same as synchronous mode. The synchronous mode transmission and its associated signals timings are shown below fig.
Q24. With a neat diagram, explain how
8251 is interfaced with 8085 and used for

serial communication. (PTU, May 2009)
OR
Explain the interfacing 8251 chip with
8085 microprocessor.
Ans. The 8251 interfacing with 8085 is to be implemented using I/O mapped I/O. It use
A0 to A7 or A8 to A15 address lines and the control signals used are ICR and low. The
Reset and CLK are connected to Reset Out and CLK out of 8085. The hardware can be minimised by using common decoder for chip. select and control signals. The address of 5251 can be calculated as:

O 25 Interface the following memory
ICS with 8086
(a) Two 4KB EPROMS, ending at FFFFFH
(b) Two 4KB SRAMS, starting at 00000H

Ans. RAM 1 Starting address is 0000H ending address is OOFFFH
RAM 2 Starting address is 01100 H ending address is FE000H
• ROM 1: Starting address is FE000H ending address is FEFFFH
ROM 2: Starting address is FF000H ending address is FFFFFH

Q 26. Draw the block diagram of 8255 and explain Its various modes. Also write down the control word for various combinations.
Or
Explain the control word register of

8255.
Ans. 8255 : The Intel 8255 is a general purpose programmable I/O device which is designed for use with áiflntei and most other microprocessors it provides 24 i/O pins which may be Individually programmed In 2 groups of 12 and used in 3 major modes of operation

Mode of operations
1. MODE 0
2. MODE 1
3. MODE 2
1. MODE 0 : The each group of 12 I/O pins

may be programmed in sets of 4 and 8 to
inputs or outputs.
2. MODE 1: Each group may be programmed to have 8 lines of input or output. 3 of the remaining 4’pins are used for handshaking and interrupts control signals.
3. MODE 2: It is a stroked bi-directional bus configuration.
Pin Configuration : The 8255 is a 40 pin
DIP package integrated circuit IC, designed to perform a variety of interface functions in a computer environment. The 8255 was not originally designed to be connected to the
Z80. it was manufactured by Intel for the
8080 microprocessor

DD-D7 These are the data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines.
CS (Chip Select Input) : If this line is a logical 0, the microprocessor can read and write to the 8255.
RD (Read Input) : Whenever this input line

is a logical 0 and RD input is a logical 0, the
8255 data outputs are enabled onto the system data bus.
WR (Write Input) : Whenever this input line is a logical 0, data is written to the 8255 from the system data bus.
AO — Al (Address line) : The logical combination of these two input lines determines which internal register of the
8255 data is written to or read form.
RESET The 8255 is placed into its reset state if this input line is a logical 1. All peripheral ports are set to the input mode PAO — PA7, PB0— PB7, PCO —
PC7. These signals are used as 8-bit I/O ports. They can be connected to peripheral devices. The 8255 has three 3-bit I/O ports and each one can be connected to the physical lines of an external device.
These lines are labelled PAO — PA7, PBO
— P87 and PCO — PC7. The groups of the

signals are divided into three different I/O ports labelled port A (PA), port B (PB) and port C (PC).
Q 27. Define the different modes of operation of DMA. What are various control signals generated by DMA controller in master mode? (PTU, Dec. 2009)
Ans. Mode of operation of DMA:
1. Rotating priority mode
2. Fixed priority mode
3. Extended write mode
4. TC stop mode
5. Auto load mode.
1. Rotating Priority Mode : If the RP bit of mode set register is set then the 8257

(DMA) operates in rotating priority mode.
After each DMA cycle, the priority of each channel changes.
2. Fixed Priority Mode: If the RP bit of mode set register is rest then 8257 operates in fixed priority mode. In fixed priority mode, channel 0 has highest priority and channel 3 has lowest priority.
3. Extended Write Mode: If the EW bit of mode set register is set, then 8257 generates advanced or extended write control signals (ö and MEMw) . This mode is used to interface slower devices to the system.
4. TC Stop Mode: It the TC stop bit in mode set register is set, then 8257 disables the channel whose TC is reached. Thus it

stops further DMA operations or that channel. If the TC stop bit is reset, then the
TC have no effect on channel, corresponding channel must be disabled by the microcomputer system through software.
5. Auto Load Mode: If AL bit of mode set register is set, the 257 operates in auto load mode. In this mode the data is transferred by channel 2only and other channels are not used for data transfer.
Q 28. What are Volatile and Non-
Volatile Memory?
Ans. Volatile memory: It is the Read/Write memory i.e which can be used to read or write the information. This is also known as user memory. Basically, when the power supply to the memory equipment is off, the data or information is lost So that’s why it is volatile memory RAM is volatile memory It stores the information as long as power is supplied to it

Two types of RAM
- Static RAM
- Dynamic RAM
Non-Volatile memory ACM is non-volatile memory which stores the information permanently It contents are not lost when power supply is switched off It is not accessible to user and hence he cannot write anything into it ACM is used to store permanent programs and to store initialising programs of a computer microcodes of CISC processor etc
Q29 Diagrammatically explain the difference between memory mapped and peripheral mapped I/O
Ans

To transfer data between the MPU and I/O devices memory related instructions (such as LDA STA) and memory control signals
(MEMR and MEMW) are used
In above case,.

Q30. Distinguish between PROM and
ROM.
Ans. PROM — Programmable Read Only
Memory, ROM — Read Only Memory.
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