Controlling the System
For Academic Use Only
Controlling the System
Introduction
System Generator infers clocks from sample times and abstracts away the Clock Enable (CE).
Multiple blocks give access to Clock Enable and/or Reset ports. It also provides several means to
develop control logic including MCode, Expression, Mealy State Machine, Moore State Machine,
and Black Box (write your own VHDL code). In this lab, you will use some of these features to
create the control logic for an address generator.
Note: There are completed examples in c:\xup\workshops\dsp_flow\labs\lab7\lab7_soln.
Objectives
After completing this lab, you will be able to:



Use the Clock Enable port in Simulink
Understand the logic behind the address generator for a MAC-based FIR filter
Develop and use a MCode block to generate a simple relational block
Design Description
In this lab, you will create an address generator for a 92-Tap MAC-based FIR filter using (i)
predefined functionality blocks, and (ii) MCode block. This process includes creating the signal
that drives the address for the memory, in which the samples will reside (data_addr); the address
for the memory in which the coefficients will reside (coef_addr); and the write enable signal that
dictates when a new sample can be saved in the memory (we).
One way to implement this filter is to store the filter coefficients and samples in a dual-port block
RAM that is used as a cyclic RAM buffer. The dual-port RAM will be used in a mixed-mode
configuration with the data written and read from port A (RAM mode), and the coefficients read
from port B (ROM mode). The functional block diagram of the design is shown in Figure 17-1.
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0
DIN_A
A
CE
WE
Data_addr
CYCLIC
COUNTER
0 – N-1
N-1
N
LOGIC
DIN_B
ROM
B
WE_B
CYCLIC
COUNTER
N – 2N-1
Coef_addr 2N-1
RAM MUST BE:
READ AFTER WRITE
WE
DIN
D1 X X
WE
X
…X
D 2X X X
WE
X
… X D3 X X X X
X
Data_addr 0 1 2 3 …91 91 0 1 2 3 …90 90 91 0 1 2
3
Coef_addr 92 93 94 95 …183 92 93 94 95 96 …183 92 93 94 95 96
Figure 17-1. Design Description.
The data address sequence (data_addr) should count upwards from 0 to 91 and stall for one clock
cycle every 92 clock cycles:
data_addr: 0 1 2 3 … 91 91 0 1 2 3 … 89 90 90 91 0 1 ... 88 89 89 90 91 0 1 2 3 4
we:
coef_addr: 92 93 … 183 92 93 94 95 … 183 92 93 94 95 …183 92 93 94 95 …
The data write enable signal (we) should go active every 92 clock cycles as shown above.
Procedure
This lab comprises two steps. You will use the System Generator blocks to create address
generators and write enable signal as explained in the design description section. In Step 1, you
will use the predefined functional blocks and estimate the resource utilization. In Step 2, you will
replace the relational functional block with an MCode block for which you will write a function.
Below each general instruction for a given procedure, you will find accompanying step-by-step
directions and illustrated figures providing more detail for performing the general instruction. If
you feel confident about a specific instruction, feel free to skip the step-by-step directions and
move on to the next general instruction in the procedure.
Note: If you are unable to complete the lab at this time, you can download the lab files for this
module from the Xilinx University Program site at http://university.xilinx.com.
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Create the Design and Estimate Resources
Step 1
Open the counter_enabled.mdl model in MATLAB from the
C:/xup/workshops/dsp_flow/labs/lab7 directory, add necessary blocks to
generate the coefficient read address (coef_addr), data write enable (we), and
data address (data_addr) signals as described in the design specification section.
Simulate the design for 200 units and verify the functionality.
 Open the MATLAB command window by double-clicking on the MATLAB icon on your desktop, or
go to Start Menu  Programs  MATLAB 6.5  MATLAB 6.5
 Change directory to c:/xup/workshops/dsp_flow/labs/lab7/: Type cd
c:/xup/workshops/dsp_flow/labs/lab7/ in the command window.
 Open the counter_enabled.mdl
 Set the parameters of the coef_counter block as follows, leaving rest of the parameters as
they are:




Number of Bits: 8
Arithmetic Type: Unsigned
Initial Value: 92
Count To Value: 183
 Set the parameters of the data_counter block as follows, leaving rest of the parameters as
they are:





Number of Bits: 7
Arithmetic Type: Unsigned
Initial Value: 0
Count To Value: 91
Provide Enable Port: checked
 Add the control logic that will drive the en port of the data_counter to generate the following
data address sequence:
0 1 2 3 … 90 91 91 0 1 2 3 ...89 90 90 91 0 1 2 3 … 89 89 90 91
en
 Add the necessary logic to generate the we output with the following behavior:
we:
coef_addr: 92 93 182 183 92 93 94 …182 183 92 93 …182 183 92 93 94 95 …
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 Simulate the design and verify that the output is similar to shown below
Figure 17-2. Simulation Result of the Controlling the System.
 Save the model
Add the Resource Estimator block to the design and estimate the resource
utilization. Generate the VHDL code and implement the design using Project
Navigator. Determine the resource utilization using the post-map report.
 Double-click the System Generator block and set the following parameters




Compilation: HDL Netlist
Product Family: Spartan3 xc3s200-4ft256
Target Directory: c:/xup/dsp_flow/labs/lab7/ise
Synthesis Tool: XST
 Add the Resource Estimator block from Xilinx Block  Index
 Double-click the Resource Estimator block
 Click the Estimate Area button
?
1. What is the resource utilization estimate?
Number of Slices:
Number of FFs:
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Number of LUTs:
 Click the Generate button
 Open the counter_enabled.npl project ( Xilinx ISE 6) from c:\xup\dsp_flow\labs\lab7\ise
 Implement the design
 Click the resource estimator block’s Post-Map Area button of the Resource Estimator
?
2. What is the resource utilization estimate?
Number of Slices:
Number of FFs:
Number of LUTs:
 Save the model
Develop a MCode model
Step 2
Open the counter_enabled_mcode.mdl model in MATLAB from the
C:/xup/workshops/dsp_flow/labs/lab7 directory, add the MCode block, and
write a m-code function to generate the we signal and en signal, as described in
the design specification section. Simulate the design for 200 units and verify the
functionality.
 Open the counter_enabled_mcode.mdl model
 Add the MCode block in the design from Xilinx Block  Index
 Open a new M-file using File  New  M-file from the MATLAB main window
 Write an m-code that will look at count input and set done to true when it is equal to 183 or
else it will set done to false
 Save the file as term_cnt.m
 Double-click the MCode block and enter term_cnt as the function name in the block
parameter field
 Complete rest of the design, making sure to add a delay element at the MCode block’s output
to delay the write enable signal
 Simulate the design and verify the functionality
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Generate the design using the System Generator block. Implement the design and
estimate the resource utilization using post-map report
 Double-click the System Generator block and generate the design
 Open counter_enabled_mcode.npl (Xilinx ISE 6) from c:/xup/dsp_flow/labs/lab7/ise
 Implement the design
 Click the resource estimator block’s Post-Map Area button of the Resource Estimator
?
3. What is the resource utilization estimate?
Number of Slices:
Number of FFs:
Number of LUTs:
 Save the project
Conclusion
In this lab, you learned how to use Clock Enable port in Simulink and understood the logic behind
the address generator for a MAC-based FIR Filter. You also learned how to use MCode block and
write a simple model that is synthesizable.
A
Answers
Figure 17-3. Controlling the System Solution.
1. What is the resource utilization estimate?
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Number of Slices:
Number of FFs:
Number of LUTs:
Controlling the System
14
16
24
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2. What is the resource utilization estimate?
Number of Slices:
Number of FFs:
Number of LUTs:
15
16
28
Figure 17-4. Controlling the System Solution Using MCode Block.
3. What is the resource utilization estimate?
Number of Slices:
Number of FFs:
Number of LUTs:
16
16
28
M-code solution
function done = term_cnt(count)
if count == 183
done = true;
else
done = false;
end
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