RAVINDER
H.No. #51, Ashok Vihar Colony, Azad Nagar Hissar, Haryana -125001
Contact No: -( +919416787860, 01662-254155,
Email id: - ravinder.ballyan@gmail.com
OBJECTIVE
Career Objective: To be associated with a firm, this provides career development opportunities and contributes in
its progress through my knowledge and skill.
PROFESSIONAL EXPERIENCE
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Organization 1
: CRM College , Hissar
Position
: Lecturer
Duration
: September 27, 2013 – April 30, 2014
Organization 2
: RF SILICON PVT. LTD
Position
: Trainee Engineer
Duration
: August 22, 2012 -- July 30, 2013
Organization 3
: NEXTERA TELECOM PVT. LTD
Position
: Service Engineer
Duration
: July 28, 2009 -- August 3, 2010
(7.5 Months)
(10 Months)
(1 Year)
PROFESSIONAL QUALIFICATION
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M.TECH (Micro-Electronics & VLSI Design)
Electronics Science Department
Affiliated to Kurukshetra University Kurukshetra
Aggregate Percentage: 60%
Dec - 2012
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B. E. (Electronics & Communication Engineering)
BRCM College of Engineering & Technology, Bhiwani, Haryana
Affiliated to MDU, Rohtak
May - 2009
Aggregate Percentage: 61.5%
PROFESSIONAL COURSES
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PG Diploma in ASIC Design and Verification, at National Institute of Electronics and Information Technology
(NIELIT), Calicut. An Autonomous Scientific Society of DIT, the Ministry of Communications and Information
Technology, Govt. of India.
EDUCATIONAL QUALIFICATION
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Matriculation from HBSE Bhiwani.
Intermediate from HBSE Bhiwani.
Sept- 2002
April- 2005
TECHNICAL SKILLS
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Hardware Description Language
Hardware Verification Language
Front End tools
Back End tools
EDA Platform
Programming language
Scripting Languages
Operating system
: System Verilog ,Verilog HDL , VHDL
: System Verilog
: ModelSim10.0c, FPGA Advantage, Synopsys VCS/DC, QuastaSim
: Mentor IC Station( Eldonet)
: Altera Quartus II, Xlinx Spartan
: C,
: Perl, Tcl
: Linux, Windows XP ,Vista ,Window7/8
UNDER GRADUATE TECHNICAL TRAINING
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6 weeks summer training at BHARAT SANCHAR NIGAM LTD. Hissar.
6 weeks summer training in Information Security & Ethical Hacking at APPIN Tech. LAB Delhi.
SEMINAR PRESENTATION
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“Fabrication process for developing Superconducting VLSI circuit: Minimizing Plasma Charging Damage”
at Electronics Science Dept., Kurukshetra University Kurukshetra.
ACADEMIC PROJECT DETAILS
M. TECH. (MAJOR PROJECT)
Title
HIGH PERFORMANCE ARCHITECTURE DESIGN AND VERIFICATION OF
DISCRETE WAVELET TRANSFORM (DWT)
Team size
1
Duration
6 Months
Tool Used
Synopsys VCS, Design Compiler, Xilinx Spartan.
Organization
National Institute For Electronics And Information Technology (NIELIT), Calicut.
Description
The main aim of the project is to Design and implement the image compression
technique in FPGA. The design involves RTL development of Data-Path, Control-Path
M. TECH. (MAJOR PROJECT)
Title
HIGH PERFORMANCE ARCHITECTURE DESIGN AND VERIFICATION OF
DISCRETE WAVELET TRANSFORM (DWT)
Team size
1
Duration
6 Months
Tool Used
Synopsys VCS, Design Compiler, Xilinx Spartan.
and Processing Blocks for lifting-based Forward DWT Processor in Verilog HDL. The
project is aimed at efficient hardware architecture for the algorithm, synthesis and
timing verification using Synopsys (DC/VCS). The synthesized hardware is targeted
towards Xilinx Spartan 3E. The FPGA performance is compared with the Matlab
model.
M. TECH.
(MINI PROJECT)
Title
RISC PROCESSOR DESIGN AND SYNTHESIS USING VERILOG HDL AND
VERIFIED USING SYSTEM VERILOG
Team size
1
Duration
Two Month
Tool Used
Synopsys VCS, Design Compiler
Organization
NIELIT, Calicut
Description
The project involves RTL-design and Simulation of RISC processor. The design
involves designing of Data-Path, Control logic and Memory for the RISC processor.
Various Instruction Sets are Designed and synthesized. The Synthesis of the Design is
carried out in 65nm TSMC library standard. The simulation is verified for different
instruction sets using VCS environment. The Timing Reports, Area Reports are
generated for RISC processor netlist using Synopsys DC. I also verified the DUT (RISC
PROCESSOR) by creating VE and generating different test cases for the DUT and also
by ABV.
M.Tech. PROJECT (3rd sem)
Title
Standard cell design and Bit cell
Team size
2
Duration
Two Month
Organization
Electronics science deptt. KUK
Description
I design the schematic of INVERTER, AND, DFF. Complete flow of layout design of
INVERTER. DRC/LVS checks and simulation. Also design 6T bit cell schematic and
plot the various waveforms.
B.E.
PROJECT
Title
MOBILE BUGS
Team size
1
Duration
Two Month
Organization
BRCM collage of engineering & technology
B.E.
PROJECT
Title
MOBILE BUGS
Team size
1
Duration
Two Month
Description
To complete my project work I used 12 V batteries for power supply. An ordinary RF
detector using tuned LC circuits is not suitable for detecting signals in the GHz
frequency band used in mobile phones. The transmission frequency of mobile phones
ranges from 0.9 to 3 GHz with a wavelength of 3.3 to 10 nm. So a circuit detecting
gigahertz signals is required for a mobile bug. Here the circuit uses a 0.22microF disk
capacitor to capture the RF signals from the mobile phone.
EXTRA CURRICULAR ACTIVITY
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Won the 2nd prize for Hindi Essay Writing Competition in RYTHEM’12 at NIELIT Calicut.
Organizing member of National level ‘NASET’ at Kurukshetra University.
Participated in ‘The War of The Future CEOs’ at BRCM College of Engineering & Tech. Bahal (Bhiwani).
Participated in National level ‘Electro Spectrum’ at BRCM College of Engineering & Tech. Bahal.
STRENGTH
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Positive attitude
Focused at work and self-motivated
Hard working
PERSONAL INFORMATION
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Name
Father’s Name
Mother’s Name
Date of Birth
Marital Status
Sex
Nationality
Languages Known
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Ravinder
Mr. Brij Lal
Mrs. Savitri Devi
21 Feb.1987
Married
Male
Indian
English, Hindi
REFERENCE
JAYARAJ U KIDAV
Scientist ‘C’,
VLSI Design group
NANDA KUMAR R
Scientist ‘B’,
VLSI Design gro up
NIELIT, Calicut
NIELIT, Calicut
Contact - +919495642541
Contacts - 9995427802
DECLARATION
I hereby declare that above-mentioned information is correct up to my knowledge and I bear the
responsibility
for the correctness of above-mentioned particulars.
Place: HISSAR
Signature:
Date:
Name:
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/
RAVINDER