RICHARD V. H. BOOTH
195 Ballek Rd.
Riegelsville PA 18077
(610)838-8714
rvbooth@ieee.org
Summary
Analog/Mixed-Signal Circuit Designer with extensive experience designing SerDes receiver circuits, Phase-Locked
Loops, linear regulators, digital circuits, and test-chips. Proven strengths in digital and analog design techniques,
using and building design tools, and consulting with customers. As Technical Manager, supervised Compact
Modeling and Device Characterization group, requiring innovative coordination of projects.
Career History
LATTICE SEMICONDUCTOR, Bethlehem, PA
Staff Engineer / Mixed-Signal FPGA Hardware Design
2006 - present
 6G SerDes design
- Implemented Decision Feedback Equalizer (DFE) including LMS algorithm module for adapting tap weights.
The DFE module includes an expandable tap-delay shift register and shared-resource IDAC bank for reduction
in chip area. The algorithm block supports 4 operation modes, including single-stepping for observing the
coefficients during adaptation, and externally-controlled adaptation.
Co-designed front-end of receiver. This includes a wide-band VGA circuit, which can either be digitallycontrolled, or tuned by an AGC loop to control the signal swing reaching the CDR.
- Designed CDR/DFE components: built library of high-speed CML latches and gates, preliminary full-rate
phase-detector, and programmable CML divider. Redesigned ICO to reject parasitic oscillation modes and
achieve specified frequency range.
General-purpose PLL design: 45nm technology, 100MHz – 1.25GHz
- PLL supports Fractional-N frequency synthesis, using variable-order MASH modulator for VCO phase
selection and feedback divide selection.
- Dividers are 50% duty-cycle, glitch-free divide value change, with dynamic variable phase advance/delay.
- Implemented VCO phase rotation circuit for adjusting relative phase advance/delay.
High-speed differential output buffer design
- Output buffer supports many differential output standards, including LVDS, hyper-transport and TMDS.
- Designed buffer to operate up to 2Gbps data rate.
FPGA PFU and routing optimization and characterization
- Developed design of experiments and optimization approach to choose best dimensions for different
routing muxes. Approach minimizes power consumption and maximizes performance.
- Fully characterized routing delays and power consumption for each fan-out configuration.
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AGERE SYSTEMS (FORMERLY LUCENT TECHNOLOGIES, AT&T BELL LABORATORIES), Allentown, PA
Distinguished Member of Technical Staff / Mixed-Signal Integrated Circuit Design
1999 - 2005
 Power Management Integrated Circuit
- Developed and synthesized verilog RTL for algorithm modules to manage battery charger, battery
temperature sensor, and high-voltage boost start-up circuits.
- Verified 8 PMIC components at block-level and system-level by writing and using structural and AMS
behavioral models, including thermal/electrical model for battery and thermistor.
 PLL design
- Designed over 15 phase-locked loops for frequency-synthesis, phase-alignment and data-recovery,
including spread-spectrum/frequency-slewing and calibrated/continuous VCO frequency
- Designed L-C oscillator-based PLL using 5GHz tank circuit, and differential logic.
- Surpassed all customer expectations with measured performance of latest 90nm PLL: peak-to-peak period
jitter less than 40ps over frequency range of first applications: 600MHz to 1GHz.
 Wrote s-domain and z-domain transfer function plotting tool for phase-stability analysis.
 Developed PLL modeling technique to provide verilog modules with built-in analog capability.
 Provided web-based divider settings calculators for each PLL to greatly simplify end-use design.
Technical Manager / Compact Modeling and Device Characterization
1992 - 1999
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Managed group of 8 members of Compact Modeling and Device Characterization group.
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Provided measurements, compact-models, characterization and support to circuit designers, researchers, and
technology developers. Developed accurate and consistent methodology to characterize integrated devices.
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Developed family of four MOSFET models that trade accuracy with simulation speed
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Developed physically-based diffused and polysilicon resistor models.
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Built extensible compact-model compiler for development, implementation and characterization of device
models, now included in open-source project on SourceForge: decida.
RICHARD V. H. BOOTH
IMEC (INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM), Leuven, Belgium
Research Engineer (Postdoctoral Assignment) / Process and Device Modeling
1989 - 1992
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Developed system for optimization of integrated circuit process technology, incorporating: integrated process,
device and circuit simulation; device parameter extraction; and statistical analysis techniques.
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Optimized IMEC 0.5-micron CMOS technology by minimizing sensitivity of device and circuit parameters to
variations in process and device design parameters.
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Developed novel software technique to transform input factors to improve response-surface model accuracy.
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Wrote program to calculate hot-carrier injection profile in MOS transistors.
LEHIGH UNIVERSITY, Bethlehem, PA
Graduate Research and Teaching Assistant
1981 – 1989
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Assisted construction of computer-controlled low-pressure chemical vapor film deposition system.
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Designed processing sequence for rapid fabrication of novel test-structures for research and education.
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Helped to organize and teach graduate-level laboratory course in microelectronics fabrication technology.
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Developed package of general-purpose multidimensional graphics subroutines for use with computer
simulation programs, used to present complex device simulation results.
WESTINGHOUSE ELECTRIC CORPORATION, Linthicum, MD
Associate Engineer / CMOS and CCD integrated circuit design
1980 - 1981
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Designed, simulated and coordinated layout of digital interface portion of discrete analog signal-processing
chip set.
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Initiated and followed processing of experimental wafer lots used to characterize CMOS SOS technology.
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Wrote MOS and bipolar transistor parameter-extraction program.
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Measured functional blocks on 16-tap adaptive-filter circuit implemented in bulk CCD-CMOS technology.
HARRY DIAMOND LABORATORIES, Adelphi, MD
Electrical Engineering Intern / Bipolar integrated circuit design
1978 - 1980
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Designed, layed-out, processed and measured test pattern used to evaluate speed and power dissipation of
Current Source Logic (CSL) circuits.
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Developed novel, highly accurate, integrated current mirror configuration.
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Wrote bipolar transistor parameter-extraction program for characterizing bipolar technology.
Professional Affiliations
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IEEE senior member
Sigma Xi Scientific Research Society
Education
LEHIGH UNIVERSITY, Bethlehem, PA
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PhD in Electrical Engineering
Dissertation: Simulation and Measurement of Hot-Carrier Injection and Degradation in Short-Channel MOS
Transistors
MS in Electrical Engineering
Thesis: An Examination of Several Models for the Saturated MOSFET
UNIVERSITY OF MARYLAND, College Park, MD
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BS in Electrical Engineering (Magna cum Laude)