5
4
3
2
1
LLW-1/LGG-1 Schematics
D
D
Sandy Bridge
Cougar Point
2010-11-08
C
C
REV : SB
DY:None Installed
UMA:UMA platform installed only
PX:Discrete(both Robson and Whistler) SKU installed
RBS:Robson SKU installed only
WTL:Whistler SKU installed only
SAMSUNG:Use SAMSUNG VRAM
Hynix:Use Hynix VRAM
VRAM_1G:Use 1G VRAM
VRAM_2G:Use 2G VRAM
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5
4
3
2
Cover Page
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
1
SB
of
94
PCB Layer Stackup
##OnMainBoard
LLW-1 / LGG-1 Block Diagram
L1: TOP
L2: GND
L3: Signal
L4: Signal
Battery Charger/Selector
AMD GPU
DDR3
800MHz
VRAM
2GB/1GB88~91
Whistler-LP 1G/2G
Seymour-XT 1G 83~87
XDP
Conn.
BQ24745
Project Code:
PCB(Raw Card):10282
11
Channel A
LVDS
Intel CPU
Sandy Bridge
VGA Port
SATA CONN
ODD CONN
Mini PCI-E
WWAN Card
56
56
HD AUDIO CODEC
CX20671
29
AUDIO
COMBO Jack
58
FDI
eSATA
USB 2.0 PORT3
USB 2.0 CH11
PCI Express 2
USB 2.0 (14 ports)
LPC I/F
Azalia bus
PCI Express 8
INT. RTC
61
49
CH12
LOM
RTL8111E
0D75V_S0
RJ45
1D8V_S0
RT8015
47
3D3V_S5
1D8V_S0
VCCSA
RT8208B
48
0D85V_S0
PWR_VCCSA_DCBATOUT
USB 2.0 CH13
NEW CARD
GFX CORE
PCI Express 8
RT8208B
92
82
USB 2.0 CH10
USB 2.0 PORT4
1V_VGA
RT9025
LPC Bus / 33MHz
93
1D5V_S3
1V_VGA_S0
1D8V_VGA
KBC
Nuvoton NPCE795
27
CH2
69
Bluetooth
Camera
PCI Express 2
USB 2.0
CH9
46
1D5V_S3
PWR_DCBATOUT_VGA_COREVGA_CORE
CH8
FingerPrint
USB 2.0 PORT1
0D75V
RT9025
LPC Debug
Board Conn
71
USB 2.0
61
CH1
65
1D5V_S3
DDR_VREF_S3
USB 2.0 CH13
PCI Rev 2.3
SATA Port5
46
PWR_1D5V_DCBATOUT
ACPI 2.0
17~25
USB 2.0 PORT2
Mini PCI-E
WLAN Card
Media Card Reader
R5U220
32
PCI Express 3
Serial ATA 150MB/s
USB 2.0 CH10
57
1D5V_S3
TPS51218
82
AC97 2.3/Azalia Interface
USB 2.0 CH4
45
RT9026
Intel
PCH
PCI Express
eSATA Combo CN
1D05V_VTT
PWR_1D05V_DCBATOUT 1D05V_VTT
PCI Express 4
SATA Port 0
VCC_CORE
TPS51218
15
SATA Port 4
42~44
DCBATOUT_VCC_GFXCORE
VCC_GFXCORE
UNBUFFERED
DDR3 SODIMM
4~10
SATA
66
NCP6131
204-PIN DDR3 SODIMM
Channel B
Display Port
5V_S5
CPU DC/DC
DCBATOUT
DDR3 1333
DMI x4
SIM
Slot
66
41
3D3V_S5
PWR_5V_DCBATOUT
14
DDR3 1333MHz
80
HDMI connector
51
UNBUFFERED
DDR3 SODIMM
DDR3 1333
CONN
49
VGA connector
50
I2C/SM Bus Switch
OUTPUTS
BT+
PWR_3D3V_DCBATOUT
SM Bus
RFID
INPUTS
DCBATOUT
BD95280
CONN
14" HD
1366*768
40
System DC/DC
PEG x16
ThermalSensor
EMC2103
28
L5: VCC
L6: Signal
L7: GND
L8: BOTTOM
1D8V_VGA_S0
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CH3
63
93
3D3V_S5
G-Sensor
79
SPI FLASH
60
Int.KB/Track point
Touch Pad
69
Title
Size
A3
Date:
Block Diagram
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
2
SB
of
94
A
PCH Strapping
Name
SPKR
4
B
C
Processor Strapping
Huron River Schematic Checklist Rev.0_7
Schematics Notes
Reboot option at power-up
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ
- 10-kΩ weak pull-up resistor.
INIT3_3V#
Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51
GNT[3:0]# functionality is not available on Mobile.
Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Strap Description
Configuration (Default value for each bit is
1 unless specified otherwise)
CFG[2]
PCI-Express Static
Lane Reversal
1:
0:
CFG[6:5]
Disabled - No Physical Display Port attached to
1: Embedded DisplayPort.
Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
HDA_SDO
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO8
2
GPIO27
4
0
PEG DEFER TRAINING
1: PEG Train immediately following xxRESETB de assertion
1
0: PEG Wait for BIOS for training
POWER PLANE
VOLTAGE
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
5V
1.5V
0.75V
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3D3V_LAN_S5
3.3V
WOL_EN
Legacy WOL
3D3V_AUX_KBC
3.3V
DSW, Sx
ON for supporting Deep Sleep states
3D3V_AUX_S5
3.3V
G3, Sx
Powered by Li Coin Cell in G3
and +V3ALW in Sx
11
DMI termination voltage. Weak internal pull-up. Do not pull low.
HAD_DOCK_EN#
/GPIO[33]
GPIO15
1
CFG[7]
Disable Danbury:Leave floating (internal pull-down)
3
15 -> 0, 14 -> 1, ...
11 : x16 - Device 1 functions 1 and 2 disabled
10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
Disable Danbury:Left floating, no pull-down required.
NC_CLE
Normal Operation.
Lane Numbers Reversed
Default
Value
PCI-Express
Port Bifurcation
Straps
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
SPI_MOSI
NV_ALE
E
Pin Name
CFG[4]
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm
weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
D
Huron River Schematic Checklist Rev.0_7
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
Voltage Rails
DESCRIPTION
ACTIVE IN
3
S0
CPU Core Rail
Graphics Core Rail
S3
AC Brick Mode only
All S states
2
USB Table
Pair
PCIE Routing
LANE1
RESERVED
LANE2
LAN
LANE3
1
CARD READER
LANE4
MiniCard WLAN
LANE5
RESERVED
LANE6
RESERVED
LANE7
RESERVED
LANE8
SATA Table
NEW CARD
SATA
Pair
Device
Device
SMBus ADDRESSES
0
X
1
USB2
I 2 C / SMBus Addresses
2
FINGERPRINT
Device
3
BLUETOOTH
4
Mini Card2 (WWAN)
5
X
6
X
7
X
0
HDD
8
ESATA1
1
mSATA
9
USB1
2
N/A
10
USB Ext. port 4
3
N/A
11
Mini Card1 (WLAN)
4
ODD
12
CAMERA
5
ESATA
13
New Card
EC SMBus 1
Battery
Capacity Board
EC SMBus 2
PCH
MXM
LCD
Thermal Sensor
PCH SMBus
CK505 Clock Generator
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
Ref Des
HURON RIVER ORB
Address
Hex
Bus
KBC_SDA1/KBC_SCL1
KBC_SDA1/KBC_SCL1
KBC_SDA2/KBC_SCL2
KBC_SDA2/KBC_SCL2
KBC_SDA2/KBC_SCL2
KBC_SDA2/KBC_SCL2
1
<Core Design>
Wistron Corporation
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
Table of Content
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
3
SB
of
94
5
4
SSID = CPU
3
2
1
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
1 OF 9
CPU1A
19 FDI_TXN[7:0]
C
B28
B26
A24
B23
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
G21
E22
F21
D21
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
G22
D22
F20
C21
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
19 FDI_FSYNC0
19 FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
19 FDI_INT
H20
FDI_INT
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
EDP_COMPIO
EDP_ICOMPO
EDP_HPD
C15
D15
EDP_AUX
EDP_AUX#
C17
F16
C16
G15
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
C18
E16
D16
F15
EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
19 FDI_TXP[7:0]
Note:
Lane reversal does not apply to
FDI sideband signals.
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
19 FDI_LSYNC0
19 FDI_LSYNC1
1D05V_VTT
R402 1
2 24D9R2F-L-GP
DP_COMP
R403 1
2 10KR2J-3-GP
eDP_HPD
DY
B
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_IRCOMP_R R401 1
2 24D9R2F-L-GP
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0
C401
C402
C403
C404
C405
C406
C407
C408
C409
C410
C411
C412
C413
C414
C415
C416
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0
C417
C418
C419
C420
C421
C422
C423
C424
C425
C426
C427
C428
C429
C430
C431
C432
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
PX
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
SCD1U6D3V1KX-GP
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_RXN[0..15]
PCI EXPRESS* - GRAPHICS
19 DMI_RXP[3..0]
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
DMI
19 DMI_RXN[3..0]
B27
B25
A25
B24
Intel(R) FDI
19 DMI_TXP[3..0]
SANDY
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
eDP
D
19 DMI_TXN[3..0]
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
PEG_RXP[0..15]
D
PEG_RXN[0..15]
83
PEG_RXP[0..15] 83
C
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG Static Lane Reversal
PEG_TXN[0..15] 83
PEG_TXP[0..15] 83
B
SANDY
Table 4.1- Central Processing Unit slot multi-source
Supplier
Description
FOXCONN
Wistron P/N
PZ98827-364B-41F
N/A
62.10055.421
2-2013620-3
N/A
62.10040.771
TYCO
A
Lenovo P/N
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
CPU (PCIE/DMI/FDI)
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
4
SB
of
94
5
4
SSID = CPU
3
2
1
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
2 OF 9
CPU1B
R501 1
2 62R2J-GP
TPAD14-GP
H_PROCHOT#
C502
SC47P50V2JN-3GP
TPAD14-GP
1
TP501
SKTOCC#_R AN34
SKTOCC#
1
TP502
H_CATERR# AL33
BCLK
BCLK#
A28
A27
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A16
A15
CLK_EXP_P
CLK_EXP_N
20
20
1D05V_VTT
RN502
CLK_DP_P_R
CLK_DP_N_R
CLK_DP_P_R 1
CLK_DP_N_R 2
CLK_DP_P_R 20
CLK_DP_N_R 20
4
3
DY
2
H_PROCHOT#_R AL32
56R2F-1-GP
PROCHOT#
Connect EC to PROCHOT# through inverting OD buffer.
AN32
22,36,85 H_THERMTRIP#
H_CPUPW RGD_R
10KR2J-3-GP
19 H_PM_SYNC
22,36 H_CPUPW RGD
C
19,37 PM_DRAM_PW RGD
1
R504
2
R505 1
H_CPUPW RGD_R
0R2J-2-GP
DY
2VDDPW RGOOD
0R2J-2-GP
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
37 VDDPW RGOOD
BUF_PLT_RST#
AR33
RESET#
R8
2
SM_DRAMRST# 37
AK1 SM_RCOMP_0 R508 1
SM_RCOMP_1 R507 1
A5
SM_RCOMP_2 R510 1
A4
2 140R2F-GP
2 25D5R2F-GP
2 200R2F-L-GP
R503
4K99R2F-L-GP
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
JTAG & BPM
2
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
THERMTRIP#
PWR MANAGEMENT
R506 1
SM_DRAMRST#
1
R513 1
PECI
DDR3
MISC
27,42 H_PROCHOT#
AN33
H_PECI
THERMAL
22,27
D
SRN1KJ-11-GP-U
CATERR#
2
1
D
SNB_IVB#
H_SNB_IVB#
CLOCKS
18
1D05V_VTT
MISC
SANDY
C26
PRDY#
PREQ#
AP29
AP27
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCLK
XDP_TMS
XDP_TRST#
TDI
TDO
AR28
AP26
XDP_TDI
XDP_TDO
1D05V_VTT
C
RN501
DBR#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
AL35
XDP_DBRESET#
AT28 XDP_BPM0
AR29 XDP_BPM1
AR30 XDP_BPM2
AT30 XDP_BPM3
AP32 XDP_BPM4
AR31 XDP_BPM5
AT31 XDP_BPM6
AR32 XDP_BPM7
1
1
1
1
1
1
1
1
TP503
TP504
TP505
TP506
TP507
TP508
TP509
TP510
XDP_TDI
XDP_TMS
XDP_TDO
XDP_TCLK
4
3
2
1
5
6
7
8
SRN51J-1-GP
XDP_TRST# R511 1
2 51R2J-2-GP
SANDY
1
1D05V_VTT
1
3D3V_S0
2
R509
75R2F-2-GP
2
R502
1KR2J-1-GP
B
1
1
1
1
1
3D3V_S0
XDP_DBRESET# 11,19
XDP_PREQ# 11
XDP_PRDY# 11
TP511
TP512
TP513
TP514
TP515
XDP_DBRESET# R516 1
2 1KR2J-1-GP
R512
43R2J-GP
2 BUF_PLT_RST#
B
D
D
1
XDP_DBRESET#
XDP_PREQ#
XDP_PRDY#
XDP_TDO
XDP_TDI
XDP_TRST#
XDP_TCLK
XDP_TMS
Q501
2N7002K-2-GP
Q502
2N7002K-2-GP
S
G
S
84.2N702.J31
2nd = 84.2N702.031
G
84.2N702.J31
2nd = 84.2N702.031
Table 5.1- N-Channel MOSFET multi-source
18,27,32,36,65,66,71,80,82,83
A
PLT_RST#
Supplier
Description
Lenovo P/N
Wistron P/N
PANJIT
2N7002K
N/A
84.2N702.J31
DIODES
2N7002K
N/A
84.2N702.031
NXP
2N7002BK
N/A
84.07002.I31
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
CPU (Thermal/CLK/PM)
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
5
SB
of
94
5
4
3
2
1
SSID = CPU
3 OF 9
4 OF 9
CPU1D
SANDY
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
D
C
B
14
14
14
14
14
14
M_A_BS0
M_A_BS1
M_A_BS2
M_A_CAS#
M_A_RAS#
M_A_W E#
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AE10
AF10
V6
SA_BS0
SA_BS1
SA_BS2
AE8
AD9
AF9
DDR SYSTEM MEMORY A
14 M_A_DQ[63:0]
M_A_DQ[63:0]
SA_CAS#
SA_RAS#
SA_WE#
SA_CLK0
SA_CLK#0
SA_CKE0
AB6
AA6
V9
SA_CLK1
SA_CLK#1
SA_CKE1
AA5
AB5
V10
SA_CLK2
SA_CLK#2
SA_CKE2
AB4
AA4
W9
SA_CLK3
SA_CLK#3
SA_CKE3
AB3
AA3
W10
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
AK3
AL3
AG1
AH1
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
AH3
AG3
AG2
AH2
SANDY
M_A_DIM0_CLK_DDR0 14
M_A_DIM0_CLK_DDR#0 14
M_A_DIM0_CKE0 14
15 M_B_DQ[63:0]
M_B_DQ[63:0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_DIM0_CLK_DDR1 14
M_A_DIM0_CLK_DDR#1 14
M_A_DIM0_CKE1 14
M_A_DIM0_CS#0 14
M_A_DIM0_CS#1 14
M_A_DIM0_ODT0 14
M_A_DIM0_ODT1 14
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
C4
G6
J3
M6
AL6
AM8
AR12
AM15
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
D4
F6
K3
N6
AL5
AM9
AR11
AM14
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQS#[7:0] 14
M_A_DQS[7:0] 14
M_A_A[15:0] 14
15
15
15
15
15
15
SANDY
M_B_BS0
M_B_BS1
M_B_BS2
M_B_CAS#
M_B_RAS#
M_B_W E#
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR SYSTEM MEMORY B
CPU1C
SB_CLK0
SB_CLK#0
SB_CKE0
AE2
AD2
R9
SB_CLK1
SB_CLK#1
SB_CKE1
AE1
AD1
R10
SB_CLK2
SB_CLK#2
SB_CKE2
AB2
AA2
T9
SB_CLK3
SB_CLK#3
SB_CKE3
AA1
AB1
T10
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
AD3
AE3
AD6
AE6
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
AE4
AD4
AD5
AE5
M_B_DIM0_CLK_DDR0 15
M_B_DIM0_CLK_DDR#0 15
M_B_DIM0_CKE0 15
D
M_B_DIM0_CLK_DDR1 15
M_B_DIM0_CLK_DDR#1 15
M_B_DIM0_CKE1 15
M_B_DIM0_CS#0 15
M_B_DIM0_CS#1 15
M_B_DIM0_ODT0 15
M_B_DIM0_ODT1 15
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
C7
G3
J6
M3
AN6
AP8
AK11
AP14
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
C
M_B_DQS#[7:0] 15
M_B_DQS[7:0] 15
B
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_RAS#
SB_WE#
M_B_A[15:0] 15
SANDY
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5
4
3
2
CPU (DDR)
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
6
SB
of
94
5
4
3
2
1
SSID = CPU
5 OF 9
CPU1E
CFG0
TP701
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
1
1
TP702
D
1
1
1
1
1
1
1
1
1
1
TP703
TP704
TP705
TP706
TP707
TP708
TP709
TP710
TP711
TP712
TP714
TP715
1
1
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
AJ31
AH31
AJ33
AH33
RSVD#AJ31
RSVD#AH31
RSVD#AJ33
RSVD#AH33
AJ26
RSVD#AJ26
VCC_VALIDATION_SENSE
VSS_VALIDATION_SENSE
M3 - Processor Generated SO-DIMM VREF_DQ
SANDY
B4:VREF_DQ CHA
R707 1
R706 1
M_VREF_DQ_DIMM0_C
M_VREF_CA_DIMM0_C
B4
D1
RSVD#B4
RSVD#D1
D1:VREF_DQ CHB
2 0R2J-2-GP
2 0R2J-2-GP
DY
1
DY
DY
2 0R2J-2-GP
2 0R2J-2-GP
R711
1KR2F-3-GP
R712
1KR2F-3-GP
2
14 M_VREF_CA_DIMM0
15 M_VREF_CA_DIMM1
DY
1
C
R708 1
R709 1
2
14,37 M_VREF_DQ_DIMM0
15 M_VREF_DQ_DIMM1
3D3V_S5
1
20 mils
2
R710
10KR2J-3-GP
H_VCCP_SEL
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD#F25
RSVD#F24
RSVD#F23
RSVD#D24
RSVD#G25
RSVD#G24
RSVD#E23
RSVD#D23
RSVD#C30
RSVD#A31
RSVD#B30
RSVD#B29
RSVD#D30
RSVD#B31
RSVD#A30
RSVD#C29
J20
B18
A19
RSVD#J20
RSVD#B18
RSVD#A19
J15
RSVD#J15
RESERVED
11
RSVD#L7
RSVD#AG7
RSVD#AE7
RSVD#AK2
RSVD#W8
L7
AG7
AE7
AK2
W8
RSVD#AT26
RSVD#AM33
RSVD#AJ27
AT26
AM33
AJ27
RSVD#T8
RSVD#J16
RSVD#H16
RSVD#G16
T8
J16
H16
G16
RSVD#AR35
RSVD#AT34
RSVD#AT33
RSVD#AP35
RSVD#AR34
AR35
AT34
AT33
AP35
AR34
RSVD#B34
RSVD#A33
RSVD#A34
RSVD#B35
RSVD#C35
B34
A33
A34
B35
C35
RSVD#AJ32
RSVD#AK32
AJ32
AK32
RSVD#AH27
AH27
RSVD#AN35
RSVD#AM35
AN35
AM35
RSVD#AT2
RSVD#AT1
RSVD#AR1
D
C
VCC_DIE_SENSE
1
TP716
PCIE_CLK_XDP_P 11,20
PCIE_CLK_XDP_N 11,20
AT2
AT1
AR1
CFG2
B
1
B
PX
PEG Static Lane Reversal
R702
1KR2J-1-GP
CFG2
2
SANDY
1: Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG7
1
CFG4
PEG DEFER TRAINING
CFG7
Display Port Presence Strap
DY
1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
R703
1KR2J-1-GP
1: Disabled; No Physical Display Port
attached to Embedded Display Port
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
2
2
R705
1KR2J-1-GP
1
DY
CFG5
CFG6
<Core Design>
A
1
1
PCIE Port Bifurcation Straps
DY
DY
R701
1KR2J-1-GP
R704
1KR2J-1-GP
2
2
A
CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Title
Size
A3
Date:
5
4
3
2
CPU (RESERVED)
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
7
of
94
5
4
3
SSID = CPU
CPU1F
A
C840
SC10U6D3V5KX-1GP
2
1
C839
SC10U6D3V5KX-1GP
2
1
C838
SC10U6D3V5KX-1GP
2
1
C810
SC10U6D3V5KX-1GP
2
1
C809
SC10U6D3V5KX-1GP
2
1
C808
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
C843
C844
SC10U6D3V5KX-1GP
2
1
C842
SC10U6D3V5KX-1GP
2
1
C830
SC10U6D3V5KX-1GP
2
1
C829
SC10U6D3V5KX-1GP
2
1
C814
SC10U6D3V5KX-1GP
2
1
C813
SC10U6D3V5KX-1GP
2
1
C812
SC10U6D3V5KX-1GP
2
1
J23
C807
C841
1D05V_VTT
SC10U6D3V5KX-1GP
2
1
VCCIO
SC10U6D3V5KX-1GP
2
1
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
C806
No-stuff sites outside the socket may be removed.
No-stuff sites inside the socket cavity need to remain.
SC10U6D3V5KX-1GP
2
1
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
C805
D
C845
C
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
For CRB VIDALERT# need to pull high 75 ohm close to CPU
1D05V_VTT
H_CPU_SVIDDAT
R804 1
2 130R2F-1-GP
S-HS_20100610 V1.0
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
R803 1
2 43R2J-GP
VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
H_CPU_SVIDDAT 42
B
R801, R802 need to close to CPU
1
VCC_CORE
R801
100R2F-L1-GP-U
2
B
PEG AND DDR
SC10U6D3V5KX-1GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
Output Decoupling Recommendation:
470 uF at Bottom Socket Edge
22 uF at Top Socket Cavity
22 uF at Top Socket Edge
22 uF at Bottom Socket Cavity
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
VCC_SENSE
VSS_SENSE
AJ35
AJ34
VCCSENSE
VSSSENSE
42
42
1
C828
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO_SENSE
VSSIO_SENSE
B10
A10
R802
100R2F-L1-GP-U
VCCIO_SENSE 45
VSSIO_SENSE 45
2
C831
C827
SVID
C832
C826
SC10U6D3V5KX-1GP
2
1
C833
C825
SC10U6D3V5KX-1GP
2
1
C824
SC10U6D3V5KX-1GP
2
1
C834
C820
SC10U6D3V5KX-1GP
2
1
C823
SC10U6D3V5KX-1GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
C819
C811
SC10U6D3V5KX-1GP
2
1
C835
SC10U6D3V5KX-1GP
2
1
C822
C804
SC10U6D3V5KX-1GP
2
1
C836
C818
SC10U6D3V5KX-1GP
2
1
C821
SC10U6D3V5KX-1GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
VCC
4 x
8 x
8 x
8 x
C817
SC10U6D3V5KX-1GP
2
1
C837
SC10U6D3V5KX-1GP
2
1
C816
SC10U6D3V5KX-1GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
C
C815
C803
SENSE LINES
VCC_CORE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CORE SUPPLY
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
D
C802
VCCIO Output Decoupling Recommendation:
2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
7 x 22 uF & 2 x 0805 no-stuff at Top
1D05V_VTT
53A
C801
1
6 OF 9
SANDY
VCC_CORE
PROCESSOR CORE POWER
POWER
2
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (VCC_CORE)
Size
Custom
SANDY
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
8
of
94
4
3
VAXG Output Decoupling Recommendation:
2 x 470 uF at Bottom Socket Edge
2 x 22 uF at Top Socket Cavity
4 x 22 uF at Top Socket Edge
2 x 22 uF at Bottom Socket Cavity
4 x 22 uF at Bottom Socket Edge
B
1D8V_S0
C922
SC1U10V2KX-1GP
2
1
C923
SC1U10V2KX-1GP
2
1
C925
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
PROCESSOR VCCPLL: 1.2A
B6
A6
A2
VCCPLL
VCCPLL
VCCPLL
C924
VCC_AXG_SENSE
VSS_AXG_SENSE
Refer to the latest Huron River Mainstream PDG
(Doc# 436735) for more details on S3 power
reduction implementation.
AL1
+V_SM_VREF_CNT
D
R907
100R2F-L1-GP-U
+V_SM_VREF_CNT should have 10 mil trace width
SM_VREF
2
VCC_AXG_SENSE 42
VSS_AXG_SENSE 42
1
SENSE
LINES
VREF
AK35
AK34
+V_SM_VREF_CNT 37
S-HR_20100609 V1.0
C911
C912
C914
C
0D85V_S0
VDDQ Output Decoupling Recommendation:
1 x 330 uF
6 x 10 uF
1
C917
TC903
ST330U2VDM-4-GP
79.33719.20L
VCCSA Output Decoupling Recommendation:
1 x 330 uF
2 x 10 uF at Bottom Socket Cavity
1 x 10 uF at Bottom Socket Edge
1
0D85V_S0
2
C915
SC10U6D3V5KX-1GP
2
1
M27
M26
L26
J26
J25
J24
H26
H25
C916
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
PROCESSOR VCCSA: 6A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
C913
SC10U6D3V5KX-1GP
2
1
C910
SC10U6D3V5KX-1GP
2
1
C909
SC10U6D3V5KX-1GP
2
1
PROCESSOR VDDQ: 10A
SC10U6D3V5KX-1GP
2
1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
SC10U6D3V5KX-1GP
2
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B
R902 need be close to pin H23.
R902
10R2J-2-GP
VCCSA_SENSE
H23
VCCSA_SENSE
FC_C22
VCCSA_VID1
C22
C24
H_FC_C22
VCCSA_SEL
2
Disabling Guidelines for External Graphics Designs:
Can connect to GND if motherboard only supports external
graphics and if GFX VR is not stuffed.
Can be left floating (Gfx VR keeps VAXG rail from floating)
if the VR is stuffed
R906
100R2F-L1-GP-U
VAXG_SENSE
VSSAXG_SENSE
VCCSA_SENSE 48
H_FC_C22
VCCSA_SEL
48
48
2
1
C
7 OF 9
Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.
1D5V_S0
DDR3 -1.5V RAILS
C921
SANDY
SA RAIL
C906
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
MISC
C920
SC10U6D3V5KX-1GP
2
1
C905
SC10U6D3V5KX-1GP
2
1
C919
SC10U6D3V5KX-1GP
2
1
C904
SC10U6D3V5KX-1GP
2
1
C918
SC10U6D3V5KX-1GP
2
1
C903
SC10U6D3V5KX-1GP
2
1
C908
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
C902
SC10U6D3V5KX-1GP
2
1
C907
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
SC10U6D3V5KX-1GP
2
1
D
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
GRAPHICS
PROCESSOR VAXG: 24A
2
POWER
CPU1G
1
VCC_GFXCORE
VCC_GFXCORE
C901
1
R906,R907 close to CPU
1.8V RAIL
SSID = CPU
2
SC10U6D3V5KX-1GP
2
1
5
SANDY
3
4
RN901
SRN1KJ-7-GP
VCCPLL Output Decoupling Recommendation:
1 x 330 uF
2 x 1 uF
1 x 10 uF
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5
4
3
2
CPU (VCC_GFXCORE)
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
9
SB
of
94
5
4
3
2
1
SSID = CPU
8 OF 9
CPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
D
C
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 9
CPU1I
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
D
C
B
SANDY
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (VSS)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
10
of
94
5
4
3
2
1
D
D
PCH_TCK
21
21
PCH_TMS
PCH_TDI
21
7,20 PCIE_CLK_XDP_N
7,20 PCIE_CLK_XDP_P
7
CFG0
5 XDP_PRDY#
5
XDP_PREQ#
1
1
1
1
1
1
DY
R1111
200R2J-L1-GP
R1112
200R2J-L1-GP
XDP1102
28
2
DY
R1110
200R2J-L1-GP
2
DY
2
21
3D3V_S5
1
1
3D3V_S5
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PCH_TDO
5,19 XDP_DBRESET#
19 PM_RSMRST#
R1124
2 1KR2J-1-GP
1
TP1101
TP1102
TP1103
TP1104
TP1105
DY
R1123
2 1KR2J-1-GP
1
1
1
DY
R1117
100R2J-2-GP
R1118
100R2J-2-GP
2
DY
R1116
100R2J-2-GP
2
DY
2
DY
1
C
C
1
27
MLX-CON26-8-GP
DY
DEBUG Interface for PCH.
DEBUG Interface for Processor.
B
CPU XDP SFF 26pin IF
Pin 1 OBSFN_A0 (PREQ#, I/O)
Pin 2 OBSFN_A1 (PRDY#, I/O)
Pin 3 GND
Pin 4 OBSDATA_A0 (Open, I/O)
Pin 5 OBSDATA_A1 (Open, I/O)
Pin 6 GND
Pin 7 OBSDATA_A2 (Open, I/O)
Pin 8 OBSDATA_A3 (Open, I/O)
Pin 9 GND
Pin 10 HOOK0 (PWRGD, In)
Pin 11 HOOK1 (BP_PWRGD_RST#, Out)
Pin 12 HOOK2 (CFG0, Out)
Pin 13 HOOK3 (vr_READYSYS_PWROK,Out)
Pin 14 HOOK4 (BCLK, In)
Pin 15 HOOK5 (BCLK#, In)
Pin 16 VCCOBS_AB (VCCP Voltage of CPU, In)
Pin 17 HOOK6 (RESET#, Out)
Pin 18 HOOK7 (DBR#, Out)
Pin 19 GND
Pin 20 TDO, In
Pin 21 TRST#, Out
Pin 22 TDI, Out
Pin 23 TMS, Out
Pin 24 TCK1 (Open)
Pin 25 GND
Pin 26 TCK0 ,Out
PCH XDP SFF 26pin IF
Pin 1 OBSFN_A0 (Open), I/O)
Pin 2 OBSFN_A1 (Open, I/O)
Pin 3 GND
Pin 4 OBSDATA_A0 (Open, I/O)
Pin 5 OBSDATA_A1 (Open, I/O)
Pin 6 GND
Pin 7 OBSDATA_A2 (Open, I/O)
Pin 8 OBSDATA_A3 (Open, I/O)
Pin 9 GND
Pin 10 HOOK0 (RSMRST#, In)
Pin 11 HOOK1 (BP_PWRGD_RST#, Out)
Pin 12 HOOK2 (Open)
Pin 13 HOOK3 (Open)
Pin 14 HOOK4 (Open)
Pin 15 HOOK5 (Open)
Pin 16 VCCOBS_AB (3.3VSUS, In)
Pin 17 HOOK6 (RSMRST#, Out)
Pin 18 HOOK7 (DBR#, Out)
Pin 19 GND
Pin 20 TDO (JTAG, In)
Pin 21 TRST# (Open)
Pin 22 TDI (JTAG, Out)
Pin 23 TMS (JTAG, Out)
Pin 24 TCK1 (Open)
Pin 25 GND
Pin 26 TCK0 (JTAG, Out)
TABLE
PCH
PIN
REF
DES
TDO
TMS
TRST#
Enable
Disable
Enable
Disable
DY
200 Ohms
DY
DY
DY
R1116
DY
DY
100 Ohms
DY
DY
DY
R2
DY
DY
R1112 200 Ohms
DY
R1118 100 Ohms
DY
DY
DY
DY
200 Ohms
DY
51 Ohms
DY
DY
DY
DY
100 Ohms
DY
DY
DY
DY
DY
51 Ohms
DY
R1111 200 Ohms
20K Ohms
200 Ohms
DY
DY
DY
R1117 100 Ohms
10K Ohms
100 Ohms
DY
DY
DY
DY
DY
51 Ohms
DY
51 Ohms
51 Ohms
51 Ohms
DY
51 Ohms
R953
20K Ohms
DY
DY
DY
DY
DY
R535
10K Ohms
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
51 Ohms
DY
R541
R103
A
Disable
PRODUCTION
DY
R90
TCK
Enable
PCH ES2 JTAG
R1110
R91
TDI
PCH ES1 JTAG
51 Ohms
B
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
LOGIC
Title
Size
A3
Date:
5
4
3
2
XDP CONN
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
11
SB
of
94
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
Reserved
Date: Tuesday, November 09, 2010
5
4
3
Rev
SB
LLW-1 / LGG-1
2
Sheet
12
of
1
94
A
A
B
C
D
E
4
4
3
3
BLANK
2
2
<Core Design>
Wistron Corporation
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
CLOCK GEN
Date: Tuesday, November 09, 2010
A
B
C
Rev
SB
LLW-1 / LGG-1
D
Sheet
13
of
E
94
1
5
4
C1420
C1421
DY
C1422
SC10U6D3V5KX-1GP
2
1
DY
SC1U6D3V2KX-GP
2
1
C1419
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
B
SC1U6D3V2KX-GP
2
1
Place these caps
close to VTT1 and
VTT2.
DY
C1418
M_A_DQS#[7:0] 6
M_A_DQS[7:0] 6
7 M_VREF_CA_DIMM0
7,37 M_VREF_DQ_DIMM0
30
15,37 DDR3_DRAMRST#
102
104
M_A_DIM0_CLK_DDR1 6
M_A_DIM0_CLK_DDR#1 6
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
11
28
46
63
136
153
170
187
SDA
SCL
200
202
EVENT#
198
VDDSPD
199
SA0
SA1
197
201
NC#1
NC#2
NC#/TEST
77
122
125
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
RESET#
0D75V_S0
203
204
VTT1
VTT2
PCH_SMBDATA 15,20,65,66
PCH_SMBCLK 15,20,65,66
4
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
Thermal EVENT
3D3V_S0
TS#_DIMM0_1 R1403 1
DY
SA0_DIM0
SA1_DIM0
C1401
SCD1U10V2KX-5GP
1D5V_S3
3D3V_S0
2 10KR2J-3-GP
C1402
SC2D2U10V3KX-1GP
C
SODIMM A DECOUPLING
1D5V_S3
TC1401
C1403
C1404
DY
C1405
C1406
C1407
DY
C1408
DY
C1409
DY
C1410
79.33719.20L
C1414
C1415
C1416
C1417
Layout Note:
Place these Caps near
SO-DIMMA.
B
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR3-SODIMM1
Size
Custom
DDR3-204P-82-GP
62.10017.U01
Date:
5
R1402
10KR2J-3-GP
TS#_DIMM0_1 15
2nd = 62.10017.T11
3rd = 62.10017.T61
H =9.2mm
D
R1401
10KR2J-3-GP
SC10U6D3V5KX-1GP
2
1
VREF_CA
VREF_DQ
CK1
CK1#
1
ODT0
ODT1
126
1
M_VREF_CA_DIMM0
M_VREF_DQ_DIMM0
M_A_DIM0_CLK_DDR0 6
M_A_DIM0_CLK_DDR#0 6
2
116
120
6 M_A_DIM0_ODT0
6 M_A_DIM0_ODT1
A
101
103
SC10U6D3V5KX-1GP
2
1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
CK0
CK0#
1
12
29
47
64
137
154
171
188
M_A_DIM0_CKE0 6
M_A_DIM0_CKE1 6
2
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
73
74
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
SA1_DIM0
SC10U10V5ZY-1GP
2
1
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
CKE0
CKE1
SA0_DIM0
SC10U6D3V5KX-1GP
2
1
10
27
45
62
135
152
169
186
M_A_DIM0_CS#0 6
M_A_DIM0_CS#1 6
SC10U6D3V5KX-1GP
2
1
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
114
121
SC10U10V5ZY-1GP
2
1
C1413
0D75V_S0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CS0#
CS1#
6
6
6
SCD1U10V2KX-5GP
2
1
SCD1U10V2KX-5GP
2
1
SC2D2U10V3KX-1GP
2
1
SCD1U10V2KX-5GP
2
1
M_VREF_DQ_DIMM0
C1412
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_A_RAS#
M_A_W E#
M_A_CAS#
SC10U6D3V5KX-1GP
2
1
2
R1404
0R2J-2-GP
DY
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
110
113
115
SCD1U10V2KX-5GP
2
1
1
20100706
C1411
BA0
BA1
RAS#
WE#
CAS#
1
6
109
108
M_A_BS2
6
M_A_BS0
6
M_A_BS1
M_A_DQ[63:0]
DDR_VREF_S3
C
1
2
6
C1424
NP1
NP2
SC10U6D3V5KX-1GP
2
1
C1425
NP1
NP2
SCD1U10V2KX-5GP
2
1
DY
SCD1U10V2KX-5GP
2
1
SC2D2U10V3KX-1GP
2
1
SCD1U10V2KX-5GP
2
1
M_VREF_CA_DIMM0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
ST330U2VDM-4-GP
2
1
2
R1405
0R2J-2-GP
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
SCD1U10V2KX-5GP
2
1
1
20100706
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
1
M_A_A[15:0] 6
DDR_VREF_S3
C1423
2
2
SSID = MEMORY
D
3
DM1
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
14
of
94
5
4
3
SSID = MEMORY
C1519
DY
C1520
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
C1518
SC1U6D3V2KX-GP
2
1
Place these caps
close to VTT1 and
VTT2.
C1521
M_B_DQS#[7:0] 6
M_B_DQS[7:0] 6
A
7 M_VREF_CA_DIMM1
7 M_VREF_DQ_DIMM1
11
28
46
63
136
153
170
187
SDA
SCL
200
202
EVENT#
198
VDDSPD
199
SA0
SA1
197
201
NC#1
NC#2
NC#/TEST
77
122
125
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
RESET#
0D75V_S0
203
204
H = 5.2mm
VTT1
VTT2
SA1_DIM1
SA0_DIM1
PCH_SMBDATA 14,20,65,66
PCH_SMBCLK 14,20,65,66
3D3V_S0
TS#_DIMM0_1 14
DY
SA0_DIM1
SA1_DIM1
C1501
SCD1U10V2KX-5GP
C1502
SC2D2U10V3KX-1GP
1D5V_S3
C
1D5V_S3
SODIMM B DECOUPLING
Layout Note:
Place these Caps near
SO-DIMMB.
DY
C1503
C1511
4
DY
C1504
C1512
C1505
C1513
C1506
C1507
DY
C1508
C1509
DY
C1510
B
C1514
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR3-SODIMM2
2nd = 62.10017.T01
3rd = 62.10017.T51
Size
Custom
DDR3-204P-83-GP
62.10017.T91
5
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
R1502
10KR2J-3-GP
SC10U6D3V5KX-1GP
2
1
VREF_CA
VREF_DQ
30
M_B_DIM0_CLK_DDR1 6
M_B_DIM0_CLK_DDR#1 6
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SC10U6D3V5KX-1GP
2
1
126
1
14,37 DDR3_DRAMRST#
102
104
D
R1501
10KR2J-3-GP
SC10U10V5ZY-1GP
2
1
ODT0
ODT1
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
CK1
CK1#
1
116
120
6 M_B_DIM0_ODT0
6 M_B_DIM0_ODT1
M_B_DIM0_CLK_DDR0 6
M_B_DIM0_CLK_DDR#0 6
2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
101
103
1
12
29
47
64
137
154
171
188
CK0
CK0#
2
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6
SC10U6D3V5KX-1GP
2
1
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
73
74
1
10
27
45
62
135
152
169
186
CKE0
CKE1
3D3V_S0
2
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DIM0_CS#0 6
M_B_DIM0_CS#1 6
SC10U6D3V5KX-1GP
2
1
B
114
121
SCD1U10V2KX-5GP
2
1
C1517
CS0#
CS1#
6
6
6
SC10U6D3V5KX-1GP
2
1
SCD1U10V2KX-5GP
2
1
SC2D2U10V3KX-1GP
2
1
SCD1U10V2KX-5GP
2
1
M_VREF_DQ_DIMM1
DY
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_B_RAS#
M_B_W E#
M_B_CAS#
SCD1U10V2KX-5GP
2
1
1
R1503
0R2J-2-GP
0D75V_S0
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
110
113
115
SC10U10V5ZY-1GP
2
1
2
DDR_VREF_S3
C1516
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
RAS#
WE#
CAS#
SCD1U10V2KX-5GP
2
1
C1522
C
DY
BA0
BA1
NP1
NP2
SC10U10V5ZY-1GP
2
1
SCD1U10V2KX-5GP
2
1
SC2D2U10V3KX-1GP
2
1
SCD1U10V2KX-5GP
2
1
M_VREF_CA_DIMM1
C1515
109
108
NP1
NP2
SCD1U10V2KX-5GP
2
1
1
R1504
0R2J-2-GP
C1524
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
M_B_BS2
6
M_B_BS0
6
M_B_BS1
M_B_DQ[63:0]
2
6
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
1
6
DDR_VREF_S3
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
2
D
C1523
1
DM2
M_B_A[15:0] 6
DY
2
Date:
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
15
of
94
5
4
3
2
1
D
D
(Blanking)
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR3-SODIMM2
Size
A4
Document Number
Date:
5
4
3
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
2
16
of
1
94
A
5
4
3
2
1
D
D
3D3V_S0
L_DDC_DATA(PAGE17):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
used for the local flat panel display
RN1702
L_BKLT_EN
LVDS_VDD_EN
4
3
J47
M45
L_BKLTEN
L_VDD_EN
49 L_BKLT_CTRL
P45
L_BKLTCTL
49 LVDS_DDC_CLK
49 LVDS_DDC_DATA
T40
K47
L_DDC_CLK
L_DDC_DATA
T45
P39
L_CTRL_CLK
L_CTRL_DATA
L_CTRL_CLK
L_CTRL_DATA
TPAD14-GP
AF37
AF36
LVD_IBG
LVD_VBG
AE48
AE47
LVD_VREFH
LVD_VREFL
49 LVDSA_CLK#
49 LVDSA_CLK
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
49 LVDSA_DATA0#
49 LVDSA_DATA1#
49 LVDSA_DATA2#
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
49 LVDSA_DATA0
49 LVDSA_DATA1
49 LVDSA_DATA2
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
TP1701
1
SDVO_TVCLKINN
SDVO_TVCLKINP
AP43
AP45
SDVO_STALLN
SDVO_STALLP
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
RN1706
SRN2K2J-1-GP
DDI Port B Detect:(SDVO_CTRL_ DATA)
1: Port B detected
0: Port B not detected
SDVO_CTRLCLK
SDVO_CTRLDATA
P38
M39
PCH_HDMI_CLK 51
PCH_HDMI_DATA 51
1
SRN100KJ-6-GP
LVDS_IBG
LVDS_VBG
Cougar
Point
Impedance:90 ohm
Close to PCH side
CRT_RED
CRT_GREEN
CRT_BLUE
50 CRT_BLUE
50 CRT_GREEN
50 CRT_RED
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
M47
M49
CRT_HSYNC
CRT_VSYNC
T43
T42
DAC_IREF
CRT_IRTN
B
5
6
7
8
50 CRT_DDC_CLK
50 CRT_DDC_DATA
RN1705
SRN150F-1-GP
4
3
2
1
50 CRT_HSYNC
50 CRT_VSYNC
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
AT49
AT47
AT40
PCH_HDMI_DET
AV42 DDBP_DATA2#
AV40 DDBP_DATA2
AV45 DDBP_DATA1#
AV46 DDBP_DATA1
AU48 DDBP_DATA0#
AU47 DDBP_DATA0
AV47 DDBP_CLK#
AV49 DDBP_CLK
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
C1708 1
C1707 1
C1706 1
C1705 1
C1704 1
C1703 1
C1702 1
C1701 1
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
51
HDMI_DATA2_R# 51
HDMI_DATA2_R 51
HDMI_DATA1_R# 51
HDMI_DATA1_R 51
HDMI_DATA0_R# 51
HDMI_DATA0_R 51
HDMI_CLK_R# 51
HDMI_CLK_R 51
C
Close to level shifter side
P46
P42
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPD_CTRLCLK
DDPD_CTRLDATA
1
DAC_IREF_R
Digital Display Interface
C
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDS
Place near PCH
2
R1701
2K37R2F-GP
CRT
1
2
27 L_BKLT_EN
49 LVDS_VDD_EN
1
2
SRN2K2J-1-GP
3D3V_S0
4 OF 10
PCH1D
L_CTRL_DATA
L_CTRL_CLK
4
3
4
3
RN1701
1
2
Impedance:90 ohm
Impedance:100 ohm
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
B
COUGAR-GP-U2-NF
2
R1702
1KR2D-1-GP
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (LVDS/CRT/DDI)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
17
of
94
4
3
3D3V_S5
SSID = PCH
3D3V_S5
10
9 LCD_PRESENCE#
W W AN_IN
8
INT_PIRQA#
7
INT_PIRQC#
6
SRN8K2J-2-GP-U
DY
2
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default
C
RN1803
DGPU_HOLD_RST#
DGPU_PW R_EN#
1
2
4
3
2 1KR2J-1-GP
BBS_BIT1
2 1KR2J-1-GP
BBS_BIT0
BBS_BIT0 21
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
3D3V_S0
2
DY
BOOT BIOS Strap
0
0
LPC
0
1
Reserved
1
0
1
1
R1814
8K2R2J-3-GP
BOOT BIOS Location
K40
K38
H38
G38
PIRQA#
PIRQB#
PIRQC#
PIRQD#
1
GNT1#/GPIO51 SATA1GP/GPIO19
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
83 DGPU_HOLD_RST#
Reserved
C46
C44
E40
DGPU_SELECT#
DGPU_PW R_EN#
93 DGPU_PW R_EN#
BBS_BIT1
TP1804
SPI(Default)
1
B
49
56
63
66
DGPU_PW M_SELECT#
TP1801
1
D47
E42
F46
PCI_GNT3#
LCD_PRESENCE#
SATA_ODD_DA#
BDC_PRESENCE#
LCD_PRESENCE#
SATA_ODD_DA#
BDC_PRESENCE#
W W AN_IN
TP1806
1
PCI_PME#
PCI_PLTRST#
EC1802
SC4D7P50V2CN-1GP
1
2
DY
1
65,71 CLK_PCI_LPC
20 CLK_PCI_FB
27 CLK_PCI_KBC
2
R1804
R1805
R1806
2 22R2J-2-GP CLK_PCI_LPC_R
2 22R2J-2-GP CLK_PCI_FB_R
2 22R2J-2-GP CLK_PCI_KBC_R
1
1
1
DY
EC1801
SC4D7P50V2CN-1GP
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
G42
G40
C42
D44
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
K10
PME#
C6
AT10
BC8
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD
DF_TVS
AV5
AY1
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
R1808
2K2R2J-2-GP
R1809
RSVD
AV10
RSVD
AT8
RSVD
RSVD
AY5
BA2
RSVD
RSVD
AT12
BF3
USBRBIAS#
PLTRST#
H49
H43
J48
K42
H40
RSVD
RSVD
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USB
DY
R1803 1
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
SRN10KJ-5-GP
R1802 1
B21
M20
AY16
BG46
1 4K7R2J-2-GP PCI_GNT3#
PCI
R1801
AY7
AV7
AU3
BG4
NV_CLE
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
H_SNB_IVB#
5
DMI & FDI Termination Voltage
Set to Vss when LOW
NV_CLE
Set to Vcc when HIGH
NV_ALE
NV_CLE
+V_NVRAM_VCCQ
DY
R1810
1KR2J-1-GP
Danbury Technology:
Disabled when Low.
Enable when High.
NV_ALE
C
USB
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
Pair
61
61
69
69
63
63
66
66
USB_PN8 57
USB_PP8 57
USB_PN9 61
USB_PP9 61
USB_PN10 82
USB_PP10 82
USB_PN11 65
USB_PP11 65
USB_PN12 49
USB_PP12 49
USB_PN13 82
USB_PP13 82
C33 USB_RBIAS R1811 1
B33
2
1KR2J-1-GP
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS
D
1
1
RN1801
1
2
3
4
5
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD
RSVD
RSVD
RSVD
2
SRN8K2J-2-GP-U
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
Cougar
Point
1
PCH_GPIO14
USB_OC#6_7
USB_OC#10_11
LAN_PW R_ON
+V_NVRAM_VCCQ
5 OF 10
PCH1E
10
9
8
7
6
NVRAM
3D3V_S0
1
2
3
4
5
RSVD
3D3V_S0
SATA_ODD_DA#
INT_PIRQD#
INT_PIRQB#
BDC_PRESENCE#
1
RN1802
USB_OC#0_1
USB_OC#12_13
USB_OC#8_9
USB_OC#2_3
D
2
2
5
2 22D6R2F-L1-GP
USB_OC#0_1
USB_OC#2_3
LAN_PW R_ON
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
PCH_GPIO14
Device
0
X
1
USB2
2
FINGERPRINT
3
BLUETOOTH
4
Mini Card2 (WWAN)
5
X
6
X
7
X
8
ESATA1
9
USB1
10
USB Ext. port 4
11
Mini Card1 (WLAN)
12
CAMERA
13
New Card
B
USB_OC#0_1 61
LAN_PW R_ON 31
USB_OC#8_9 57,61
USB_OC#10_11 82
COUGAR-GP-U2-NF
3D3V_S0
OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
U1801
VCC
4
Y
B
1
A
2
PCI_PLTRST#
GND
3
DY
A
PLT_RST#
1
5,27,32,36,65,66,71,80,82,83
74LVC1G08GW -1-GP
DY
73.01G08.L04
2ND = 73.7SZ08.DAH
R1807 1
DY
2 0R2J-2-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
C1801
SC220P50V2KX-3GP
Size
A3
Date:
5
4
3
A
C1802
SC220P50V2KX-3GP
2
1
2
R1816
100KR2J-1-GP
1
5
2
DY
KBC CLK EMI
2
PCH (PCI/USB/NVRAM)
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
18
of
94
5
4
SSID = PCH
3
2
4 DMI_RXN[3..0]
4 DMI_RXP[3..0]
1
FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
4 DMI_TXN[3..0]
4 DMI_TXP[3..0]
3 OF 10
PCH1C
4
Signal Routing Guideline: 4
DMI_ZCOMP keep W=4 mils and4
4
routing length less than 500
mils.
4
DMI_IRCOMP keep W=4 mils and
4
4
routing length less than 500
4
mils.
DY
1
1
DMI_RXP3
DMI_RXP2
DMI_RXP1
DMI_RXP0
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_TXN3
DMI_TXN2
DMI_TXN1
DMI_TXN0
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_TXP3
DMI_TXP2
DMI_TXP1
DMI_TXP0
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
Cougar
Point
1D05V_VTT
R1904
100KR2J-1-GP
R1926
10KR2J-3-GP
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
4
4
4
4
PW ROK
2
2
SYS_PW ROK
BC24
BE20
BG18
BG20
FDI
D
DMI_RXN3
DMI_RXN2
DMI_RXN1
DMI_RXN0
DMI
4
4
4
4
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_TXN7
FDI_TXN6
FDI_TXN5
FDI_TXN4
FDI_TXN3
FDI_TXN2
FDI_TXN1
FDI_TXN0
4
4
4
4
4
4
4
4
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_TXP7
FDI_TXP6
FDI_TXP5
FDI_TXP4
FDI_TXP3
FDI_TXP2
FDI_TXP1
FDI_TXP0
4
4
4
4
4
4
4
4
FDI_INT
AW16
FDI_INT
4
D
BJ24
DMI_ZCOMP
FDI_FSYNC0
AV12
FDI_FSYNC0
R1901 1
2 49D9R2F-GP DMI_COMP_R
BG25
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
4
R1902 1
2 750R2F-GP
BH21
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
4
FDI_LSYNC1
BB10
FDI_LSYNC1
4
DSWVRMEN
A18 DSW ODVREN
RBIAS_CPY
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
4
3D3V_S0
SUS_PW R_ACK
5,11 XDP_DBRESET#
R1903 1
DY
2 0R2J-2-GP SUSACK#
R1925 1
DY
2 0R2J-2-GP SYS_RESET# K3
R1905 1
R1923 1
R1924 1
R1927 1
2 0R2J-2-GP
DY
2 0R2J-2-GP
2 0R2J-2-GP
R1906 1
PW ROK
L22
R1907 1
2 0R2J-2-GP
DY
5,37 PM_DRAM_PW RGD
SYS_RESET#
SYS_PWROK
PWROK
2 0R2J-2-GP
MEPW ROK L10
36,37,45,46,47 RUNPW ROK
SUSACK#
2 10KR2J-3-GP
P12
36 SYS_PW ROK
27,36 S0_PW R_GOOD
42,48 D85V_PW RGD
C12
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
11 PM_RSMRST#
PM_RSMRST#
SUS_PW R_ACK
27 SUS_PW R_ACK
27 PM_PW RBTN#
APWROK
System Power Management
C
DPWROK
E22 PCH_DPW ROK
B9
PCIE_W AKE#
CLKRUN#/GPIO32
N3
PM_CLKRUN#
SUS_STAT#/GPIO61
G8
PM_SUS_STAT#
WAKE#
RTC_AUX_S5
R1911
R1910
1
1
DY
C
2 10KR2J-3-GP
PM_RSMRST#
2 0R2J-2-GP
PCIE_W AKE# 65,82
PM_CLKRUN# 27
1
TP1901 TPAD14-GP
DSWODVREN - On Die DSW VR Enable
SUSCLK/GPIO62
N14 SUS_CLK
SLP_S5#/GPIO63
D10 PM_SLP_S5#
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
R1913 1
2 0R2J-2-GP
1
PCH_SUSCLK_KBC
27
SLP_S4#
H4
SLP_S4#_R
R1914 1
2 0R2J-2-GP
PM_SLP_S4# 27,46,82
SLP_S3#
F4
SLP_S3#_R
R1915 1
2 0R2J-2-GP
PM_SLP_S3# 27,36,37,47,82
AC_PRESENT
SLP_A#
G10 PM_SLP_A#
H20
ACPRESENT/GPIO31
SLP_SUS#
G16 PM_SLP_SUS#
PMSYNCH
AP14 H_PM_SYNC
20
BATLOW #
E10
BATLOW#/GPIO72
20
PM_RI#
A10
RI#
Enabled (DEFAULT)
LOW
Disabled
RTC_AUX_S5
1
TP1903TPAD14-GP
B
27 AC_PRESENT
HIGH
TP1902 TPAD14-GP
SLP_LAN#/GPIO29
1
DSW ODVREN
TP1904TPAD14-GP
R1917 1
2 330KR2J-L1-GP
R1918 1
2 330KR2J-L1-GP
B
DY
K14 PM_SLP_LAN#
H_PM_SYNC
1
5
TP1905TPAD14-GP
3D3V_S0
COUGAR-GP-U2-NF
PM_CLKRUN# R1919 1
3D3V_S5
2 8K2R2J-3-GP
RN1901
1
2
3
4
AC_PRESENT
SUS_PW R_ACK
SRN10KJ-6-GP
R1921 2
DYR1922 2
1 10KR2J-3-GP PM_PW RBTN#
R1920 2
1 10KR2J-3-GP PM_SLP_LAN#
PCIE_WAKE#
CRB : 1K
CEKLT: 10K
R1909 1
2
A
1 10KR2J-3-GP PCIE_W AKE#
3D3V_AUX_S5
PEG_B_CLK_RQ# 20
Need Check!!
R1908
2
1 10KR2J-3-GP PM_RSMRST#
2 100KR2J-1-GP
1
8
7
6
5
PM_RSMRST#
CRB : PL 10K
ANNIE : PL 100K
Q1901
R1916
10KR2J-3-GP
4
3
PM_RSMRST# R1912 1
3V_5V_POK_#
5
2
3V_5V_POK
6
1
2 1KR2J-1-GP
RSMRST#_KBC 27
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2N7002KDW -GP
Title
84.2N702.A3F
2nd = 84.DM601.03F
PCH (DMI/FDI/PM)
Size
A3
Date:
5
4
A
41
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
19
of
94
5
4
3
2
SSID = PCH
3D3V_S5
1
3D3V_S5
1
2 OF 10
J2
AB49
AB47
PCIE_CLK_RQ1#
M1
C
RN2013 SRN0J-6-GP
2
3
1
4
32 CLK_PCIE_CR#
32 CLK_PCIE_CR
CARD READER CLK
RN2014
1
2
65 CLK_PCIE_WLAN#
65 CLK_PCIE_WLAN
SRN0J-6-GP
CLK_PCH_SRC3_N
4
CLK_PCH_SRC3_P
3
Y37
Y36
PCIE_CLK_WLAN_RQ3#
65 PCIE_CLK_WLAN_RQ3#
3D3V_S0
AA48
AA47
PCIE_CLK_CR_RQ2# V10
32 PCIE_CLK_CR_RQ2#
WLAN CLK
CLK_PCH_SRC2_N
CLK_PCH_SRC2_P
PCIECLKRQ1# and PCIECLKRQ2#
support S0 power only
A8
Y43
Y45
RN2018
1
2
4
3
SRN10KJ-5-GP
PCIE_CLK_RQ1#
PCIE_CLK_CR_RQ2#
PCIE_CLK_RQ4#
RN2015
1
2
82 CLK_PCIE_NEW#
82 CLK_PCIE_NEW
SRN0J-6-GP
CLK_PCH_SRC5_N
4
CLK_PCH_SRC5_P
3
PCIE_CLK_NEW_RQ5#
82 PCIE_CLK_NEW_RQ5#
L12
L14
E6
V40
V42
PCIE_CLK_RQ6#
T13
V38
V37
PCIE_CLK_RQ7#
K12
B
7,11 PCIE_CLK_XDP_N
7,11 PCIE_CLK_XDP_P
2
2
PERN5
PERP5
PETN5
PETP5
SML1CLK/GPIO58
SML1DATA/GPIO75
SML0_DATA
SML1_CLK
M16
SML1_DATA
PERN7
PERP7
PETN7
PETP7
CL_CLK1
CL_DATA1
CL_RST1#
M7
CL_CLK
T11
CL_DATA 1
P10
SML1_CLK 27
1
TPAD14-GP
TP2002
TPAD14-GP
AK14
AK13
6
1
5
2
4
3
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
PCIECLKRQ1#/GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
PCIECLKRQ2#/GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_GND1_N
CLKIN_GND1_P
PCIECLKRQ3#/GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCH_SMBCLK
CLKIN_SATA_N
CLKIN_SATA_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
PCIECLKRQ5#/GPIO44
CLKIN_PCILOOPBACK
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
14,15,65,66
SMB_CLK
TP2003
TPAD14-GP
PX
M10 PEG_CLKREQ#_R R2003 1
2 0R2J-2-GP
AB37
AB38
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
RN2016
1
2
4
3
R2008 1
AV22
AU22
CLKOUT_DMI_N
CLKOUT_DMI_P
RN2010
1
2
4
3
AM12
AM13
CLKOUT_DP_N
CLKOUT_DP_P
RN2017
1
2
BF18
BE18
CLK_BUF_EXP_N
CLK_BUF_EXP_P
BJ30
BG30
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
G24
E24
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
AK7
AK5
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
K45
CLK_BUF_REF14
PEG_CLKREQ#
85
2 0R2J-2-GP
C2008
2
1
XTAL25_IN
CLK_PCIE_VGA# 83
CLK_PCIE_VGA 83
R2006
1M1R2J-GP
SRN0J-6-GP
CLK_EXP_N
CLK_EXP_P
5
5
XTAL25_OUT
X2001
SC12P50V2JN-3GP
XTAL-25MHZ-96GP
C2007
2
1
SRN0J-6-GP
4
3
CLK_DP_N_R
CLK_DP_P_R
DY
SC12P50V2JN-3GP
5
5
3D3V_S0
3D3V_S0
UMA
R2012
10KR2J-3-GP
2
1
H45
DY
R2008 and C2008 CO-LAY
SRN0J-6-GP
RN2011
PCIECLKRQ4#/GPIO26
PCH_SMBDATA 14,15,65,66
Q2001
CL_RST# 1
XTAL25_IN
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CRB : 1K
CEKLT: 10K
2N7002KDW-GP
SML1_DATA 27
TP2001
2 1KR2J-1-GP
2nd = 84.DM601.03F
84.2N702.A3F
NEW CARD
CLKOUT_PCIE1N
CLKOUT_PCIE1P
3
4
SRN2K2J-1-GP
SMB_DATA
PERN6
PERP6
PETN6
PETP6
PCIECLKRQ0#/GPIO73
D
DRAMRST_CNTRL_PCH 1
R2009
RN2007
PCH_GPIO74
E14
4 RN2006
3 SRN10KJ-5-GP
3D3V_S0
2
1
C13
1
2
2
SMBUS
SML1ALERT#/PCHHOT#/GPIO74
SML0_CLK
G12
3 RN2005
4 SRN2K2J-1-GP
PCIE_CLK_RQ6#
PCH_GPIO74
37
3
4
CLK_PCI_FB
V47 XTAL25_IN
V49 XTAL25_OUT
R2013
10KR2J-3-GP
DY
UMA_DIS#
DGPU_PRSNT#
C
UMA_DISCRETE#
UMA: 1 1
DIS :0 1
SG(PX) : 0 0
Optimus(Muxless) : 1 0
UMA_DIS#
22
PX
R2010
10KR2J-3-GP
SRN10KJ-5-GP
V45
V46
AB42
AB40
19 PEG_B_CLK_RQ#
WLAN
C8
DRAMRST_CNTRL_PCH
2
1
1
PCIE_CLK_LAN_RQ0#
82 PCIE_CLK_LAN_RQ0#
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW.
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN
PERN4
PERP4
PETN4
PETP4
SML0CLK
SML0DATA
A12 DRAMRST_CNTRL_PCH
2 RN2004
1 SRN2K2J-1-GP
SML1_CLK
SML1_DATA
2
SRN0J-6-GP
CLK_PCH_SRC0_N Y40
4
CLK_PCH_SRC0_P Y39
3
Card Reader
SML0ALERT#/GPIO60
1 RN2003
2 SRN2K2J-1-GP
3
4
1
RN2012
1
2
82 CLK_PCIE_LAN#
82 CLK_PCIE_LAN
LAN CLK
PCIE_TXN8_C
PCIE_TXP8_C
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
PERN3
PERP3
PETN3
PETP3
PERN8
PERP8
PETN8
PETP8
SMB_DATA 80,82
R2005
10KR2J-3-GP
1
C2009
C2010
BE38
BC38
AW38
AY38
DY
2
82 PCIE_RXN8
82 PCIE_RXP8
82 PCIE_TXN8
82 PCIE_TXP8
SMB_CLK 80,82
4
3
SML0_DATA
SML0_CLK
1
BG40
BJ40
AY40
BB40
SMB_DATA
SMB_CLK
SMB_DATA
R2011
10KR2J-3-GP
2
BJ38
BG38
AU36
AV36
LAN
SMB_CLK
C9
1
BG37
BH37
AY36
BB36
SMBDATA
H14
PEG_CLKREQ#_R
27
2
BF36
BE36
AY34
BB34
PERN2
PERP2
PETN2
PETP2
EC_SWI#
1
PCIE_TXN4_C
PCIE_TXP4_C
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
SMBCLK
R2004
10KR2J-3-GP
E12
2
C2005
C2006
PCIE_TXN3_C
PCIE_TXP3_C
BG36
BJ36
AV34
AU34
SMBALERT#/GPIO11
Link
65 PCIE_RXN4
65 PCIE_RXP4
65 PCIE_TXN4
65 PCIE_TXP4
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
PCIE_TXN2_C
PCIE_TXP2_C
BE34
BF34
BB32
AY32
Cougar
Point
PERN1
PERP1
PETN1
PETP1
Controller
C2003
C2004
BG34
BJ34
AV32
AU32
18
+VCCDIFFCLKN
PEG_B_CLKRQ#/GPIO56
XCLK_RCOMP
Y47 XCLK_RCOMP R2007 1
2 90D9R2F-1-GP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCIECLKRQ6#/GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
FLEX CLOCKS
32 PCIE_RXN3
32 PCIE_RXP3
32 PCIE_TXN3
32 PCIE_TXP3
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
1
1
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1_C
PCIE_TXP1_C
PCI-E*
D
C2001
C2002
1
1
1
1
CLOCKS
82 PCIE_RXN2
82 PCIE_RXP2
82 PCIE_TXN2
82 PCIE_TXP2
TP2004
TP2005
TP2006
TP2007
1
PCH1B
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
K43 JTAG_TCK R2001 1
DY
F47 CLK_48_USB30 1
TP2008
H47 LAN_25M
TPAD14-GP
2 22R2J-2-GP
R2015 1
K49 DGPU_PRSNT#
2 22R2J-2-GP
DY
JTAG_TCK_VGA 83,85
For VGA_ 27M
LAN_XI
B
82
COUGAR-GP-U2-NF
PL 10K FOR Integrated CLOCK GEN mode.
RN2009
CLK_BUF_REF14
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
1
2
3
4
5
10
9
8
7
6
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
SRN10KJ-L3-GP
need very close to PCH
3D3V_S5
RN2001
1
2
3
4
SRN10KJ-6-GP
RN2002
1
2
3
4
8
7
6
5
PCIE_CLK_WLAN_RQ3#
PCIE_CLK_RQ7#
8
7
6
5
PCIE_CLK_LAN_RQ0#
PCIE_CLK_NEW_RQ5#
PCIE_CLK_RQ4#
EC_SWI#
BATLOW#
19
PM_RI#
19
SRN10KJ-6-GP
Table 20.1- Dual N-Channel MOSFET multi-source
A
Supplier
Description
PANJIT
2N7002KDW
Lenovo P/N
N/A
Wistron P/N
84.2N702.A3F
DIODES
DMN601DWK-7
N/A
84.DM601.03F
NXP
2N7002BKS
N/A
84.2N702.E3F
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5
4
3
2
PCH (PCI-E/SMBUS/CLOCK/CL)
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
20
of
94
A
5
4
3
2
1
Table 21.1 Project_ID
RTC_AUX_S5
3D3V_S0
LW_GG_SEL
1
SSID = PCH
LW
RN2104
SRTC_RST#
3
4
1
RTC_X1
SRN20KJ-GP-U
2 10MR2J-L-GP
RTC_X2
C2103
SC1U6D3V2KX-GP
LW
High
GG
LOW
R2109
10KR2J-3-GP
LW _GG_SEL
1
2
R2101 1
INTVRMEN- Integrated SUS
1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
2
2
1
D
X2101
LPC_AD[0..3]
1 OF 10
PCH1A
LPC_AD[0..3]
RTC_RST#
SRTCRST#
SM_INTRUDER# K22
R2105
1
2 330KR2F-L-GP PCH_INTVRMEN C17
29
SRN33J-5-GP-U
29
HDA_SDOUT
+3VS_+1.5VS_HDA_IO
2 1KR2J-1-GP
TPAD14-GP
11 PCH_TCK
3D3V_S0
No Reboot Strap
1
DY
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
66
66
66
66
mSATA
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4
56
56
56
56
JTAG_TCK
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
SATA_RXN5
SATA_RXP5
SATA_TXN5
SATA_TXP5
57
57
57
57
SATAICOMPO
Y11
SATAICOMPI
Y10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
2 1KR2J-1-GP
HDA_SPKR
Low = Default
HDA_SPKR High = No Reboot
PCH_TCK
J3
11 PCH_TMS
H7
JTAG_TMS
11 PCH_TDI
K5
JTAG_TDI
H1
JTAG_TDO
11 PCH_TDO
+3VS_+1.5VS_HDA_IO
T3
27,60 SPI_CLK_R
B
R2103 1
1
2 1KR2J-1-GP
27,60 SPI_CS0#_R
HDA_SYNC
This signal has a weak internal pull down.
On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
co-operate with R2310
SPI_CS0#_R
22,27
AM10
AM8
AP11
AP10
T10
HDA_RST#
HDA_SDOUT
NO REBOOT STRAP
R2106
TP2105
INT_SERIRQ
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_SYNC
PCH_GPIO33
V5
HDD
L34
HDA_SDOUT
2 1KR2J-1-GP
LPC_FRAME# 27,65,71
56
56
56
56
HDA_BCLK
D
R2110
10KR2J-3-GP
LW _GG_SEL
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
JTAG
1
DY
R2107 1
E36
K36
AM3
AM1
AP7
AP5
N34
HDA_SDIN0
D36
LDRQ0#
LDRQ1#/GPIO23
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_SYNC
HDA_SPKR
FWH4/LFRAME#
SERIRQ
C
SATA_COMP
R2112
ODD
ESATA
1D05V_VTT
2 37D4R2F-GP
1
1D05V_VTT
SPI_CLK
SATA3RCOMPO
AB12
SATA3COMPI
AB13
SATA3_COMP R2113
1
2 49D9R2F-GP
SATA3RBIAS
AH1
RBIAS_SATA3 R2114
1
2 750R2F-GP
B
Y14
SPI_CS0#
T1
SPI_CS1#
27,60 SPI_SI_R
V4
SPI_MOSI
27,60 SPI_SO_R
U3
SPI_MISO
SPI
R2115
27 ME_UNLOCK
Low = Default
High = Enable
INTVRMEN
HDA_BITCLK
C
Flash Descriptor Security Overide
INTRUDER#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
GG
27,65,71
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
2
RTCRST#
G22
Cougar
Point
LPC
D20
SRTC_RST#
2 1M1R2J-GP
HDA_RST#
HDA_BITCLK
3
4
RTC_RST#
1
RN2102
2
1
29 HDA_CODEC_RST#
29 HDA_CODEC_BITCLK
RTCX2
R2104
1 R2122 HDA_SYNC
1 R2123 HDA_SDOUT
2
2
C20
C38
A38
B37
C37
SATA 6G
33R2J-2-GP
33R2J-2-GP
RTCX1
RTC_X2
SATA
X-32D768KHZ-40GPU
29 HDA_CODEC_SYNC
29 HDA_CODEC_SDOUT
RTC_AUX_S5
A20
RTC
1
G2101
GAP-OPEN
1
2
3
C2104
SC1U6D3V2KX-GP
2
1
C2101
SC15P50V2JN-2-GP
2
1
2
C2102
SC15P50V2JN-2-GP
RTC_X1
IHDA
4
2
1
P3
SATALED#
SATA_LED# 22
SATA0GP/GPIO21
V14
SATA1GP/GPIO19
P1
SATA_DET#0 22
BBS_BIT0
BBS_BIT0
18
COUGAR-GP-U2-NF
PLL ODVR VOLTAGE
Low = 1.8V (Default)
HDA_SYNC High = 1.5V
0827
3D3V_S0
For EMI
DY
EC2103
SC4D7P50V2CN-1GP
2
2
EC2102
SC22P50V2JN-4GP
22 PSW _CLR#
22 MFG_MODE
22 S_GPIO
DY
1
2
3
4
BBS_BIT0 R2108 1
8
7
6
5
<Core Design>
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to
sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
PCH_GPIO33 R2125
2
PCH_TCK
1
R2102
DY
1 1KR2J-1-GP
4
3
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2 51R2J-2-GP
Title
Size
A3
Date:
5
2 10KR2J-3-GP
SRN10KJ-6-GP
EC2105
SC4D7P50V2CN-1GP
1
2
DY
1
DY
EC2101
SCD1U10V2KX-5GP
1
HDA_CODEC_SDOUT
SPI_CS0#_R
2
1
HDA_BITCLK
HDA_RST#
A
3D3V_S0
RN2103
2
PCH (SPI/RTC/LPC/SATA/IHDA)
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
21
of
94
5
4
3
2
1
SSID = PCH
INTERNAL GFX
TACH1/GPIO1
H36
TACH2/GPIO6
TACH3/GPIO7
GPIO15
GPIO16
U2
SATA4GP/GPIO16
A20GATE
SCLOCK/GPIO22
PCH_GPIO24
E8
GPIO24/MEM_LED
E16
PLL_ODVR_EN
P8
PSW _CLR#
GAP-OPEN
1
G2201
1
C
TP2204
2
TPAD14-GP
21
NC_FP_DET#
27 PCH_TEMP_ALERT#
STP_PCI#/GPIO34
K4
GPIO35
V8
SATA2GP/GPIO36
SATA3GP/GPIO37
N2
SLOAD/GPIO38
M3
SDATAOUT0/GPIO39
V13
TPAD14-GP
TP2212
PCH_GPIO57
D6
GPIO57
RN2204
PCH_GPIO12
PCH_GPIO57
3
4
2
1
SRN10KJ-5-GP
B
PCH_GPIO15
1
R2201
2
1KR2J-1-GP
NCTF_VSS#A44
A45
NCTF_VSS#A45
A46
NCTF_VSS#A46
A5
NCTF_VSS#A5
A6
NCTF_VSS#A6
1
R2221
2
10KR2J-3-GP
NCTF_VSS#B3
B47
NCTF_VSS#B47
BD1
NCTF_VSS#BD1
BD49
PCH_GPIO24
NCTF_VSS#BD49
TPAD14-GP
TP2209
1
PCH_NCTF_2
BE1
NCTF_VSS#BE1
TPAD14-GP
TP2210
1
PCH_NCTF_3
BE49
NCTF_VSS#BE49
TPAD14-GP
TP2211
1
PCH_NCTF_4
BF1
BF49
2 0R2J-2-GP
H_PECI
R2206
100KR2J-1-GP
5,27
2
27
T14
INIT3_3V#
H_CPUPW RGD
1
R2204
5,36
2 390R2J-1-GP
1
H_THERMTRIP# 5,36,85
TP2201 TPAD14-GP
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
NCTF_VSS#BF1
NCTF_VSS#BF49
COUGAR-GP-U2-NF
NCTF_VSS#BG2
BG2
BG48
1D05V_VTT
20100723 V1.62
FDI TERMINATION VOLTAGE OVERRIDE
3D3V_S0
AK10 TS_VSS 1 R2222 2
0R0402-PAD
P37
NCTF_VSS#BG48
DY1
2
56R2F-1-GP
C
GPIO37
(FDI_OVRVLTG)
R2207
10KR2J-3-GP
NCTF_VSS#A4
A44
B3
PCH_THERMTRIP_R
INIT3_3V#
SDATAOUT1/GPIO48
SATA5GP/GPIO49
3D3V_S5
AY10
NC_1
V3
A4
AY11
THRMTRIP#
TS_VSS4
PCH_TEMP_ALERT#
PCH_NCTF_1
1
PROCPWRGD
GPIO28
M5
FFS_INT2_R
2 FFS_INT2_R
10KR2J-3-GP
DY
1
H_RCIN#
GFX_CRB_DET
R2224
K1
R2223
1
R2203
PCH_THERMTRIP_R
FDI_OVRVLTG
GFX_CRB_DET
3D3V_S0
H_PECI_R
P5
GPIO27
DMI_OVRVLTG
MFG_MODE
AU16
H_A20GATE 27
1
21
mSATA_DTCT#
H_A20GATE
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
DY
2
27,66 mSATA_DTCT#
GPIO27 has a weak[20K] internal pull up.
To enable on-die PLL Voltage regurator,
should not place external pull down.
GPIO
T5
PECI
RCIN#
P4
FDI_OVRVLTG
1
1
D
R2205
10KR2J-3-GP
R2208
10KR2J-3-GP
NCTF_VSS#BH3
BH3
NCTF_VSS#BH47
BH47
TP2207
NCTF_VSS#BJ4
BJ4
1
NCTF_VSS#BJ44
BJ44
NCTF_VSS#BJ45
BJ45
NCTF_VSS#BJ46
BJ46
NCTF_VSS#BJ5
BJ5
NCTF_VSS#BJ6
BJ6
NCTF_VSS#C2
C2
NCTF_VSS#C48
C48
NCTF_VSS#D1
D1
NCTF_VSS#D49
D49
2
TP2202
TACH0/GPIO17
PCH_GPIO22
NCTF TEST PIN:
TPAD14-GP
1
TP2205 TPAD14-GP
2
G2
SRN10KJ-5-GP
3D3V_S0
TP2206 TPAD14-GP
1
LAN_PHY_PWR_CTRL/GPIO12
PCH_GPIO15
D40
A40 VRAM_SIZE2
UMA_DIS# 20
1
GPIO8
C4
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
H_A20GATE
H_RCIN#
4
3
C41 VRAM_SIZE1
DY
PCH_GPIO12
92,93 DGPU_PW ROK
RN2203
B41 UMA_DIS#
TACH6/GPIO70
TACH7/GPIO71
3D3V_S0
1
2
TACH5/GPIO69
DY
3D3V_S0
DMI TERMINATION VOLTAGE OVERRIDE
R2209
10KR2J-3-GP
TP2208
1
GPIO36
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
DY
DMI_OVRVLTG
R2210
10KR2J-3-GP
0827
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
3D3V_S5
ICC_EN#
NCTF_VSS#E1
E1
NCTF_VSS#E49
E49
B
Integrated Clock Chip Enable
HIGH (R2211 DY)- DISABLED [DEFAULT]
1
C10
10K
SATA_ODD_PW RGT 56
LOW (R2211)-
R2214
10KR2J-3-GP
NCTF_VSS#F1
F1
NCTF_VSS#F49
F49
2
2 0R2J-2-GP
1
E38
ICC_EN#
C40
ICC_EN#
1
R2213
EC_SCI#
100K
1
56 SATA_ODD_PRSNT#
EC_SCI#
R2206
EXTERNAL GFX
1
A42
DGPU_HPD_INTR#
TACH4/GPIO68
2
27
DY
1
1
EC_SMI#
SATA_ODD_PRSNT#
CPU/MISC
D
2 200KR2F-L-GP
Cougar
Point
BMBUSY#/GPIO0
NCTF
3D3V_S0
R2202
2 100R2J-2-GP T7
1
D1,D49,E1,E49,F1,F49
R2218
S_GPIO
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
21
R2205
6 OF 10
PCH1F
2
Note:
For PCH debug with XDP, need to NO STUFF R2218
R2211
1KR2J-1-GP
ENABLED
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
2
DY
3D3V_S0
PLL ON DIE VR ENABLE
0827
RN2201
21 SATA_DET#0
1
DY
RN2202
R2225
10KR2J-3-GP
8
7
6
5
R2215
10KR2J-3-GP
R2220
10KR2J-3-GP
<Core Design>
A
2
SRN10KJ-6-GP
PLL_ODVR_EN
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R2212
1KR2J-1-GP
SRN10KJ-6-GP
Title
DY
2
PCH (GPIO/CPU)
Size
A3
Date:
5
DEFAULT
1
ENABLED -- HIGH (R2212 UNSTUFFED)
DISABLED -- LOW (R2212 STUFFED)
1
EC_SMI#
1
EC_SCI#
2
DGPU_HPD_INTR# 3
4
3D3V_S5
NC_FP_DET#
2
SATA_LED#
A
8
7
6
5
1
21
1
PCH_GPIO22
2
PCH_TEMP_ALERT#3
4
2
21,27 INT_SERIRQ
mSATA_DTCT#
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
22
of
94
5
4
3
2
1
SSID = PCH
3D3V_DAC_S0
Cougar
Point
VCCIO
2 R2312
1
1
D
C2315
HCB1608KF-181-GP
SC10U6D3V5KX-1GP
2
1
2
1
CRT
C2314
SCD1U10V2KX-5GP
0R2J-2-GP
2
0.001A
+3VS_VCCA_LVD
VCCALVDS
AK36
VSSALVDS
AK37
VCCTX_LVDS
AM37
VCCTX_LVDS
AM38
VCCTX_LVDS
AP36
DY
VCCTX_LVDS
AP37
R2309
0R2J-2-GP
R2303
1
DY
0R3J-0-U-GP 2
1 R2304
2 0R2J-2-GP
1D8V_S0
0.06A
+1.8VS_VCCTX_LVDS
0R5J-5-GP 1
2 R2305
C2317
SCD01U16V2KX-3GP
1
1
1
C2316
SCD01U16V2KX-3GP
C2318
SC10U6D3V5KX-1GP
VCCIO
L2302
DY
VCCAPLLEXP
VCCIO
AP26
VCCIO
AT24
VCCIO
AN33
VCCIO
1
1D05V_VTT
AT20
VCCDMI
+1.05VS_VCC_DMI 0R2J-2-GP 1
AB36
VCCCLKDMI
2 R2306
C2320
SC1U6D3V2KX-GP
3D3V_S0
AN34
VCCIO
VccDFTERM
AG16
VccDFTERM
AG17
VccDFTERM
AJ16
VccDFTERM
AJ17
5
NC#4
4
G9091-330T11U-GP
C2312
1D05V_VTT
+1.05VS_VCC_DMI_CCI 0R2J-2-GP 1
0.266A (Totally VCC3_3 current)
C2311
VOUT
2 R2307
0.02A
C2321
SC1U6D3V2KX-GP
1
VCCFDIPLL
BG6
VCCAFDIPLL
0R2J-2-GP 2
1 R2308
3D3V_S5
3D3V_S0
1
0.19A
1D8V_S0
1
VCCVRM
+V_NVRAM_VCCQ
B
DY
C2322
SCD1U10V2KX-5GP
0.042A (Totally current of VCCDMI)
R2313
0R2J-2-GP
VCCDMI
2
VCCIO
AU20
R2314
0R2J-2-GP
V1
VCCSPI
0.02A
1
+1.05VS_VCC_DMI
AP17
FDI
1D05V_VTT
2
TP2302
VCCAFDI_VRM AP16
2
0R3J-0-U-GP
2
TPAD14-GP
1
R2302
1
1D5V_S0_1D8V_S0
B
VCC3_3
2
0.159A(Totally current of VCCVRM)
BH29
C2310
SCD1U10V2KX-5GP
NAND / SPI
1
2
DY
C2324
SC10U6D3V5KX-1GP
2
1
1
2
IND-1UH-100-GP
AP24
AT16
VCCVRM
VIN
GND
EN
SC1U6D3V2KX-GP
2
1
VCCIO
AP23
1
2
3
1D5V_S0_1D8V_S0
SC1U10V2KX-1GP
2
1
AP21
C
C2319
SCD1U10V2KX-5GP
2
VCCIO
1
VCCIO
AN27
3D3V_DAC_S0
U2301
V34
VCC3_3
1
1D05V_VTT
5V_S0
VCCIO
AN26
20100625 V1.2
3.3V CRT LDO
3D3V_S0
2
AN21
C2309
VCCIO
V33
VCC3_3
DMI
C2308
AN17
VCCIO
C2307
SC1U6D3V2KX-GP
2
1
C2306
VCCAPLLEXP
1
SC1U6D3V2KX-GP
2
1
C2305
TP2301
SC1U6D3V2KX-GP
2
1
C
TPAD14-GP
SC1U6D3V2KX-GP
2
1
SC10U6D3V5KX-1GP
2
1
1D05V_VTT
HVCMOS
2
2
VCCAPLLEXP
AN16
C2313
SCD01U16V2KX-3GP
2
BJ22
U47
VSSADAC
1
2
VCCIO
+VCCA_DAC_1_2
3D3V_S0
1D05V_VTT
AN19
DY
L2301
U48
VCCADAC
2
C2304
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
3D3V_S0
7 OF 10
1
C2303
SC1U6D3V2KX-GP
2
1
C2302
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC10U6D3V5KX-1GP
2
1
D
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
LVDS
6A
C2301
POWER
PCH1G
VCC CORE
1D05V_VTT
2
COUGAR-GP-U2-NF
VCCSPI
(1uFx1)
C2323
SC1U6D3V2KX-GP
The same BIOS SPI ROM power
Table 23.1- LDO Regulator multi-source
VCCVRM(Internal PLL and VRMs):
A.1.5V for Mobile
B.1.8 V for Desktop
co-operate with R2103
A
1D5V_S0
0R3J-0-U-GP 1
Supplier
Description
GMT
G9091-330T11U
Lenovo P/N
N/A
74.09091.J3F
Wistron P/N
RICHTEK
RT9198-33GBR
N/A
74.09198.Q7F
<Core Design>
1D5V_S0_1D8V_S0
A
Wistron Corporation
2 R2310
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (POWER1)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
23
of
94
3
+V3.3S_VCC_CLKF33
2
IND-10UH-66-GP
C2401
C2407
VCCASW
VCCASW
AA24
VCCASW
AA26
VCCASW
AA27
VCCASW
AA29
VCCASW
AA31
VCCASW
AC26
C2402
(22uFx2_0603)
(1uFx3)
VCCASW
AC27
VCCASW
AC29
VCCASW
AC31
VCCASW
AD29
VCCASW
AD31
VCCASW
W21
VCCASW
W23
VCCASW
W24
VCCASW
W26
VCCASW
1D05V_VTT
V5REF_SUS
0.08A+1.05VS_VCCA_A_DPL
VCCSUS3_3
AN23 +VCCA_USBSUS
N16
AN24 +V3.3A_VCCPSUS
V5REF
C2411
1D5V_S0_1D8V_S0
SCD1U10V2KX-5GP
Y49
VCCSUS3_3
N20
VCCSUS3_3
N22
VCCSUS3_3
P20
VCCSUS3_3
P22
3D3V_S5
+V3.3A_VCCPSUS
VCC3_3
AA16
VCC3_3
W16
VCC3_3
T34
BD47
+1.05VS_VCCA_B_DPL
BF47
+VCCDIFFCLK
AF17
AF33
AF34
AG34
0.055A
1
1 0R3J-0-U-GP
0.095A
VCCVRM
+V1.05S_SSCVCC
VCCADPLLA
VCCIO
VCCIO
AH13
VCCIO
AH14
VCCIO
AF14
VCCADPLLB
VCCIO
VCCDIFFCLKN
VCCDIFFCLKN
VCCDIFFCLKN
VCCSSC
1 SCD1U10V2KX-5GP +VCCSST V16
DCPSST
VCCAPLLSATA
C2430
SCD1U10V2KX-5GP
1D05V_VTT
DCPSUS
1
T17
V19
1D05V_VTT
DCPSUS
DCPSUS
C2419
SCD1U10V2KX-5GP
A22
6uA
VCCRTC
HDA
C2418
SCD1U10V2KX-5GP
V_PROC_IO
RTC
2
1
1
RTC_AUX_S5
2
C2417
SC4D7U6D3V3KX-GP
1D05V_VTT
COUGAR-GP-U2-NF
DY
4
5
NC#4
4
G9091-150T11U-GP
DY
C2437
DY
C2416
1D05V_VTT
AK1
DY
VCCVRM
AF11
VCCIO
AC16
VCCIO
AC17
VCCIO
AD17
+V1.05S_VCCAPLL_SATA3 0R3J-0-U-GP 1
2 R2411
1D5V_S0_1D8V_S0
C2434
SC10U6D3V3MX-GP
VCCASW
T21
VCCASW
V21
DY
1D05V_VTT
+V1.05S_VCC_SATA
0R3J-0-U-GP 1
2 R2412
2
C2435
SC1U6D3V2KX-GP
+3VS_+1.5VS_HDA_IO
3D3V_S5 1D5V_S0 1D5V_S5
R2414 1
R2415 1
R2413 1
VCCASW
T19
VCCSUSHDA
P32
+3VS_+1.5VS_HDA_IO
2 0R3J-0-U-GP
DY
DY
2 0R3J-0-U-GP
2 0R3J-0-U-GP
<Core Design>
0.01A
A
Wistron Corporation
C2433
SCD1U10V2KX-5GP
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
1
C2421
SCD1U10V2KX-5GP
VOUT
C2436
Title
C2422
SCD1U10V2KX-5GP
PCH (POWER2)
Size
A3
Date:
5
VIN
GND
EN
C2432
SC1U6D3V2KX-GP
2
1
C2420
SC1U6D3V2KX-GP
2
1
C2413
SC1U6D3V2KX-GP
2
1
1 0R2J-2-GP +V1.05S_SSCVCC
2
R2405 2
BJ8
1
C2412
SC1U6D3V2KX-GP
2
A
0.001A
+VCCDIFFCLK
2
1
1 0R2J-2-GP
CPU
1D05V_VTT
1
2
3
B
1
TP2406
1D5V_S5
U2401
C2431
SCD1U10V2KX-5GP
C2429
SCD1U10V2KX-5GP
1
TPAD14-GP
DY
3D3V_S5
1D05V_VTT
MISC
C2415 2
C
3D3V_S0
AJ2
AF13
DCPRTC
AG33
2
C2414
SC1U6D3V2KX-GP
2 R2410
3D3V_S0
VCC3_3
2 R2407
C2427
SC1U10V2KX-1GP
1
+VCCDIFFCLKN
R2406 2
R2404 2
0R3J-0-U-GP 1
10R2J-2-GP 1
C2428
SC1U6D3V2KX-GP
2
1D05V_VTT
+1.05VS_VCCA_A_DPL
D2402
CH751H-40-1-GP
0.001A
+5VS_PCH_VCC5REF
P34
5V_S0
TPAD14-GP
C2443
SC1U10V2KX-1GP
DY
1
1
C2410
SC1U6D3V2KX-GP
TP2403
1
2
C2445
SC10U6D3V3MX-GP
VCCASW
0.16A (Totally current of VCCVRM
1
1
DY
2
68.1001A.10B
2nd = 68.10010.10T
VCCASW
W33
0.001A
M26 +5VA_PCH_VCC5REFSUS
VCCASW
W31
+VCCRTCEXT
0.08A+1.05VS_VCCA_B_DPL
2
IND-10UH-66-GP
2
L2403
1
W29
C2409
SC1U6D3V2KX-GP
2 R2408
C2426
SCD1U10V2KX-5GP
C2425
SCD1U10V2KX-5GP
2
C2444
SC10U6D3V3MX-GP
1
DY
2
1
68.1001A.10B
2nd = 68.10010.10T
2
2
IND-10UH-66-GP
10R2J-2-GP 1
3D3V_S0
DCPSUS
SATA
L2402
1
A
T26
K
VCCIO
1
P24
1
VCCSUS3_3
3D3V_S5
2
1D05V_VTT
B
DCPSUS
AA21
C2408
VCCSUS3_3
V24
1
68.1001A.10B
2nd = 68.10010.10T
C2406
V23
SC10U6D3V5KX-1GP
2
1
1
SC1U10V2KX-1GP
2
1
2
1R2F-GP
SC10U6D3V3MX-GP
2
1
1
L2401
C2404
SC1U6D3V2KX-GP
2
1
R2402
C2403
SC1U6D3V2KX-GP
2
1
C
SC1U6D3V2KX-GP
2
1
2 0R3J-0-U-GP
SC10U6D3V5KX-1GP
2
1
R2401 1
SC10U6D3V5KX-1GP
2
1
DY
VCCSUS3_3
D2401
CH751H-40-1-GP
C2424
SCD1U10V2KX-5GP
SC1U10V3ZY-6GP
2
1
2
1D05V_VTT
T24
5V_S5
D
1
1
C2442
SC1U6D3V2KX-GP
1.01A (Total current of VCCASW)
3D3V_S0
VCCIO
AA19
DCPSUS
DY
VCCSUS3_3
3D3V_S5
3D3V_S5
2
2
1 0R2J-2-GP
VCCSUS3_3
T23
VCCAPLLDMI2
C2440
SC10U6D3V5KX-1GP
DY
T29
VCC3_3
2
+VCCSUS1 AL24
1
T27
VCCIO
A
DY
TP2402
VCCIO
2
DY
TPAD14-GP
DCPSUSBYP
C2423
SC1U6D3V2KX-GP
K
AL29
P28
2
1+VCCAPLL_CPY_PCH BH23
P26
VCCIO
SC1U10V3ZY-6GP
2
1
TPAD14-GP
1D05V_VTT
TP2404
VCCIO
VCCDSW3_3
1
+V3.3S_VCC_CLKF33 T38
VCCACLK
68.1001A.10B
2nd = 68.10010.10T
R2420 2
V12
N26
1
1DCPSUSBYP
VCCIO
1
TP2405
1D05V_VTT
10 OF 10
Cougar
Point
2
TPAD14-GP
C2439
2 L2404 1
2+VCCAPLL_CPY_PCH
IND-10UH-66-GP
0R3J-0-U-GP
2 0R3J-0-U-GP +VCCPDSW T16
POWER
VCCACLK
1
DY
1 0R2J-2-GP
AD49
PCI/GPIO/LPC
R2419 1
DY
DY
1VCCACLK
Clock and Miscellaneous
2
1
R2417
R2403 1
TP2401
2
1D05V_VTT
TPAD14-GP
1
C2441
3D3V_S5
1
2
DY
SCD1U10V2KX-5GP
1
2
C2438
SCD1U10V2KX-5GP
2
D
+VCCPDSW
DY
SC1U10V2KX-1GP
2
1
1
2 0R3J-0-U-GP
DCPSUSBYP
DY
+VCCSUS1
R2418 1
0.002A
1
PCH1J
3D3V_AUX_S5
2
SSID = PCH
2
2
4
USB
5
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
24
of
94
5
4
3
SSID = PCH
8 OF 10
PCH1H
B
H5
VSS
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Cougar
Point
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
COUGAR-GP-U2-NF
A
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
9 OF 10
PCH1I
D
C
2
Cougar
Point
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
D
C
B
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
COUGAR-GP-U2-NF
PCH (VSS)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
25
of
94
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
Document Number
Reserved
Date: Tuesday, November 09, 2010
5
4
3
Rev
SB
LLW-1 / LGG-1
2
Sheet
26
of
1
94
A
5
4
SSID = KBC
3D3V_AUX_KBC
3
2
1
3D3V_AUX_S5
20100709
3D3V_AUX_KBC
2 0R5J-5-GP
1
VBAT
1 0R3J-0-U-GP
2
R2724
10KR2J-3-GP
2
3D3V_S0
1
1
PX
2
R2741
10KR2J-3-GP
KB_ID1
57,61 USB_PWR_EN
19 AC_PRESENT
DISCRETE_ID
KBC_VCORF
44
AC_IN_KBC
EC_ENABLE
GPIO2
GPIO3/AD6
GPIO4/AD5
GPIO5/AD4
PSL_IN2_GPI6#
GPIO7/AD7
GPIO16
GPIO24
GPIO30
GPIO34/CIRRXL
GPIO36
GPIO41
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO46/CIRRXM/TRST#
GPIO51
PSL_IN1_GPI70
PSL_OUT_GPIO71
VBKUP
GPIO75
GPO76/SHBM
GPIO77
GPIO81
GPO82/IOX_LDSH/TEST#
GPI/O84/IOX_SCLK/XORTR#
GPIO97
4
VDD
GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4
1
1
1
2 0R2J-2-GP
PLT_RST#
CLK_PCI_KBC 18
LPC_FRAME# 21,65,71
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_AD[0..3]
INT_SERIRQ 21,22
PM_CLKRUN# 19
L_BKLT_EN 17
ECSCI#_KBC
PCH_TEMP_ALERT# 22
ECSWI#_KBC
H_A20GATE 22
H_RCIN#
22
27
25
11
10
71
72
BLON_OUT 49
PCIE_RST# 83,85
GSENSE_ON# 79
USB_AO_SEL0 82
TPDATA 69
TPCLK 69
70
69
67
68
119
120
24
28
5,18,32,36,65,66,71,80,82,83
BAT_SCL 39,40
BAT_SDA 39,40
SML1_CLK 20
SML1_DATA 20
USB_PWR_EN2 82
GSENSOR_ID
PROCHOT_EC
F_CS0#
F_SCK
F_SDI/F_SDIO1
F_SDIO/F_SDIO0
49 PANEL_LED
29 KBC_BEEP
1
TP2711
NOTE:
PWM Signal :
1. If unused, select altrnative GPIO function
and enable internal pull-down.
2. Please measure and make sure that the
rise time of VCC_POR is less than 10us.
CHG_ON#
32
118
62
65
81
66
22
16
BRIGHTNESS
40 STOP_CHG#
1
TP2710
FAN1_PWM
69 PAD_RESET#
82 AC_IN_LED
69
PALM_LED
ECRST#
65
65
<------ TP
5,22
1D05V_VTT
AMP_MUTE#
30
77
PECI 13
2 43R2J-GP
2 0R2J-2-GP EC_VTT 12
R2721 1
R2720 1
H_PECI
85
113
111
E51_RxD
E51_TxD
29 AMP_MUTE#
19 PCH_SUSCLK_KBC
<------ BATTERY / CHARGER
<------PCH / eDP
90
92
86
87
EC_SPI_CS#_C
EC_SPI_CLK_C
EC_SPI_DI_C
EC_SPI_DO_C
2
2
2
2
R2736
R2719
R2737
R2722
1
1
1
1
40
33R2J-2-GP
33R2J-2-GP
0R2J-2-GP
33R2J-2-GP
SPI_CS0#_R 21,60
SPI_CLK_R 21,60
SPI_SO_R 21,60
SPI_SI_R 21,60
NOTE:
Locate resistors R2719 and R2722 close
to the NPCE791L.
2 OF 2
U2701B
mSATA_DTCT#_C 31
117
63
64
GPIO56/TA1
GPIO20/TA2/IOX_DIN_DIO
GPIO14/TB1
GPIO1/TB2
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
GPIO15/A_PWM
KBSOUT5/TDO
GPIO21/B_PWM
KBSOUT6/RDY#
GPIO13/C_PWM
KBSOUT7
GPIO32/D_PWM
KBSOUT8
GPIO66/G_PWM
KBSOUT9/SDP_VIS#
GPIO33/H_PWM
KBSOUT10/P80_CLK
GPIO45/E_PWM
KBSOUT11/P80_DAT
GPIO40/F_PWM
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
VCC_POR#
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO87/CIRRXM/SIN_CR
GPI/O83/SOUT_CR/TRIST#
KBSIN0
KBSIN1
GPIO55/CLKOUT/IOX_DIN_DIO
KBSIN2
GPIO0/EXTCLK
KBSIN3
KBSIN4
KBSIN5
PECI
KBSIN6
VTT
KBSIN7
Prevent
1
E
1 10KR2J-3-GP B
PURE_HW_SHUTDOWN#
C
3D3V_AUX_S5
U2702
1
2
GND
3
VCC
RESET#
G690L293T73UF-GP
84.T3906.A11
74.00690.I7B
ECSWI#_KBC
EC_GPIO47 High Active
Q2702
B
G
D
1
DY
R2732
100KR2J-1-GP
D2704
1
EC_SCI#
3
R2712
H_PROCHOT#_EC
R2733 1
2 0R2J-2-GP
H_PROCHOT#
5,42
S
2 0R2J-2-GP
2
R2716 1
EC GPIO standard PH/PL
2N7002K-2-GP
3D3V_AUX_KBC
84.2N702.J31
2nd = 84.2N702.031
RN2701
ECSCI#_KBC
BAT_SCL
BAT_SDA
2
40
3
4
BAS16GP-GP
2
1
SRN4K7J-8-GP
0R0402-PAD
1
DY
R2705
10KR2J-3-GP
C2715
SC1U6D3V2KX-GP
2nd = 84.03906.F11
PROCHOT_EC
AC_IN
DY
Q2701
MMBT3906-4-GP
2
2
1
EC_SWI#
B
2
BIOS data loss solution
2
R2723
2 0R2J-2-GP
3
AC_IN_KBC 1
1 R2728
3D3V_AUX_S5
NOTE:
Pleae place R2711 close to AGND pin.
BAS16GP-GP
22
1mSATA_DTCT#_C 2
10KR2J-3-GP
ECRST#
28,36 PURE_HW_SHUTDOWN#
1 1KR2J-1-GP
2
69
C
1
0R2J-2-GP
2
R2770
KROW[0..7]
TP2709
D2701
AD_OFF
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
69
NOTE:
Please be aware that the SPI interface trace length between
PCH and EC should not exceed 6500mils,. The mismatch
of SPI interface signals between EC and SPI flash should
not exceed 500mils.
EC_AGND
20
54
55
56
57
58
59
60
61
KCOL[0..17]
71.00795.A0G
1
R2711
2
R2740
10KR2J-3-GP
DY
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
C2716
SCD1U16V2KX-3GP NPCE795GA0DX-GP
NOTE:
Connect GND and AGND planes via either
0R resistor or one point layout connection.
EC_AGND
NOTE:
C2712 must place close to VCORF pin.
R2715 1
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
103
18
45
78
89
116
5
71.00795.A0G
R2700
1MR2J-1-GP
2
1
22,66 mSATA_DTCT#
19 PM_PWRBTN#
69 TP4_RESET
19,36,37,47,82 PM_SLP_S3#
21,65,71
R2701 and C2716
Need very close to EC
NPCE795GA0DX-GP
KB_ID1
R2735
PLT_RST#_EC
1
VCORF
C2712
SC1U10V3ZY-6GP
2
1
EC_AGND
102
2
RTC_AUX_S5
65 WIFI_RF_EN
63 BLUETOOTH_EN
19,36 S0_PWR_GOOD
PAD_DETECT#
GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
7
2
3
1
128
127
126
125
8
9
29
124
123
121
122
1
2
R2713
10KR2J-3-GP
D
EC_AGND
2
1
UMA
2
1
TP2708
TP2705
KBC_PWRBTN_EC#
79 GSENSE_Y
69 PAD_DETECT#
82 AD_OFF
29 BEEP_ENABLE
36 S5_ENABLE
66 3G_POWERON
39 BAT_IN#
49 LID_CLOSE#
19 RSMRST#_KBC
19,46,82 PM_SLP_S4#
21 ME_UNLOCK
56 HDD_DTCT#
3D3V_AUX_KBC
DISCRETE_ID
VGA_THRM
1
LRESET#
LCLK
LFRAME#
LAD3
LAD2
LAD1
LAD0
SERIRQ
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
DY
1 OF 2
1
2HDD_DTCT# 1
10KR2J-3-GP
R2727 1
79
95
96
108
93
94
114
6
109
14
15
80
17
20
21
23
26
73
74
75
82
83
84
91
110
112
107
19 SUS_PWR_ACK
79 GSENSE_X
TP2707
28 FAN_ID
3D3V_AUX_S5
R2710
100KR2J-1-GP
2
R2729 1
G Sensor ID:
High: ST
Low:ADI
DY
2
101
105
106
VREF
GND
GND
GND
GND
GND
GND
2PAD_DETECT#
100KR2J-1-GP
2
1
97
98
99
100
PCB_VER_AD
82 USB_AO_SEL1
79 GSENSE_TST
66 3G_EN
3D3V_S0
C2703
SC2D2U10V3KX-1GP
C2711
1
2
SC220P50V2KX-3GP
AGND
104
2 SCD1U10V2KX-5GP
82 ACDC_ID2
79 GSENSE_Z
2 ACDC_ID2
10KR2J-3-GP
R2714 1
C
DY
1
40 AD_IA
AVCC
19
46
76
88
115
U2701A
EC_AGND
C2714
EC_AGND
3D3V_AUX_KBC
GSENSOR_ID
PCB_VER_AD
R2726
100KR2J-1-GP
VCC
VCC
VCC
VCC
VCC
2
1
C2710
SCD1U10V2KX-5GP
1
2
C2709
SC2D2U10V3KX-1GP
2
1
C2708
SCD1U10V2KX-5GP
1
2
C2707
SCD1U10V2KX-5GP
1
2
2
C2706
SCD1U10V2KX-5GP
1
C2705
SCD1U10V2KX-5GP
1
2
C2704
SCD1U10V2KX-5GP
DY
C2702
SCD1U10V2KX-5GP
2
1
SC2D2U10V3KX-1GP
2
1
3D3V_AUX_KBC_VCC
C2701
R2718
100KR2J-1-GP
BOM Ctrl
R2771
2D2R3-1-U-GP
D
1
R2725
R2702
2
3D3V_AUX_KBC
3D3V_S0
DY
BAT_IN#
R2701 2
1 100KR2J-1-GP
2
R2706
100KR2J-1-GP
RN2705
S5_ENABLE
LID_CLOSE#
3D3V_AUX_S5
4
3
3D3V_S0
SML1_CLK
SML1_DATA
1
2N7002KDW-GP
1
1 470R2J-2-GP
SMBC_THERM 28,85
1
2
6
2
1
3
5
1
4
3D3V_S0
RN2702
R2703
82 KBC_PWRBTN#
G2701
GAP-OPEN
SMBD_THERM 28,85
84.2N702.A3F
R2774
100KR2J-1-GP
KBC_PWRBTN_EC#
AMP_MUTE#
PCIE_RST#
4
3
DY
C2717
SC220P50V2KX-3GP
1
2
SRN10KJ-5-GP
E51_RxD
R2708 1
DY
A
2 10KR2J-3-GP
2
FAN_ID
2
1
SRN10KJ-5-GP
2
2
A
1 10KR2J-3-GP
2
3
4
R2709 2
2
1
SMBC_THERM
SMBD_THERM
Q2703
R2717
22KR2J-GP
ECRST#
R2704
10KR2J-3-GP
RN48
3D3V_AUX_S5
1
2
SRN10KJ-5-GP
3D3V_S0
2nd = 84.DM601.03F
BLUETOOTH_EN
R2707 1
DY
<Core Design>
2 10KR2J-3-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
KBC Nuvoton NPCE795
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
27
of
94
5
4
SSID = Thermal
3
2
1
Thermal sensor
T8
2200p close to smsc2103 chip
Close to SO-DIMM side.
THER_UMA_DXN R2813
1
UMA2
REMOTE2-
1
UMA
C2805
SC390P50V2KX-GP
1
1
CPU backside or inside the socket
CPU TEMP:
H_THERMDA and H_THERMDC routing 10mil trace width
and spacing. Locate Capacity near Thermal diode.
2200p close to smsc2103 chip
0R2J-2-GP
2
C2806
SC2200P50V2KX-2GP
THER_UMA_DXP R2814
MMBT3904W T1G-GP
84.03904.R11
2nd = 84.M3904.A11
1
UMA2
0R2J-2-GP
5V_S0
REMOTE2+
1
3D3V_S0
C
R2804
6K8R2J-GP
27
C2801
R2805
10KR2J-3-GP
FAN1
8
C
6
5
4
3
2
FAN_ID
FAN_TACH
2
SHDN_SEL
1
between CPU, VGA and DIMM on bottom side
SC4D7U6D3V3KX-GP
2
1
C
D
2
1
E
UMA
B
C2804
SC2200P50V2KX-2GP
MMBT3904W T1G-GP
84.03904.R11
2nd = 84.M3904.A11
Q2802
C2809
SC390P50V2KX-GP
H_THERMDC
84.03904.R11
2nd = 84.M3904.A11
MMBT3904W T1G-GP
2
B
2
C
2
Q2803
Q2801
C2802
SC390P50V2KX-GP
2
B
E
1
D
2
E
3
1
C
H_THERMDA
SA 0905 change to 390p
20100709_EMI
FAN_PW M
R2806 1
1
B
PX
2 0R2J-2-GP
E
THER_VGA_DXN
1
TP2802
TPAD14-GP
R2812
2
2103_VDD
1
THERM_SCI#
PX
SCD1U10V2KX-5GP
H_THERMDA
H_THERMDC
REMOTE2+
0R2J-2-GP
REMOTE22
R2802 1
2
1
16
15
THERM_SYS_SHDN#
2 0R0402-PADTHERM_SCI#_R
27,85 SMBC_THERM
27,85 SMBD_THERM
2
1
3
4
EC2801
SC1KP50V2KX-1GP
FAN_PW M_C
1
7
DY
EC2802
SC1KP50V2KX-1GP
ACES-CON6-35-GP
SRN10KJ-5-GP
3
C2808
SC390P50V2KX-GP
2
Q2805
MMBT3904W T1G-GP
84.03904.R11
2nd = 84.M3904.A11
1
C2803
1
C
PX
R2811
R2801
68R2-GP
U2801
2 0R0402-PAD
DY
2
THER_VGA_DXP
2
RN2801
PX
2
Close to VGA side.
1
1
3D3V_S0
1
SHDN --> 2N3904 ON External diode
2
3D3V_S0
4
5
TACH
PWM
10
11
TRIP_SET
SHDN_SEL
14
13
GND
GND
12
17
DP1
DN1
DP2/DN3
ND2/DP3
7
6
SYS_SHDN#
ALERT#
9
8
SMCLK
SMDATA
2103_4
2103_5
GPIO1
GPIO2
VDD
1
1
TP2801TPAD14-GP
TP2803TPAD14-GP
D2802
A
K
FAN_TACH
FAN_PW M
5V_S0
FAN_PW M_C
FAN_TACH
FAN_ID
CH551H-30GP-GP
TRIP_SET R2803 1
SHDN_SEL
2 2K05R2F-GP
1
1
1
1
SA 0905
T8 = 105
TP2101
TP2102
TP2103
TP2104
B
B
EMC2103-2-AP-GP
74.02103.A73
3D3V_AUX_S5
3D3V_S0
D2803
BAT54PT-GP
83.00054.T81
Table 28.1- General Purpose Transistors multi-source
1
DY
3
pin6, ALERT# OD
pin7, SYS_SHDN# OD
3D3V_S0
Q2804
S
2
1
2ND = 83.BAT54.D81
3rd = 83.BAT54.S81
R2808 1
D
2
R2810
10KR2J-3-GP
2
DY
1
1
27,36 PURE_HW _SHUTDOW N#
THERM_SYS_SHDN#
G
DY
R2809 1
DY
2
R2807
100KR2J-1-GP
2 0R2J-2-GP
2 0R2J-2-GP
Supplier
Description
Lenovo P/N
Wistron P/N
ON
MMBT3904WT1G
N/A
84.03904.R11
PANJIT
MMBT3904W
N/A
84.M3904.A11
IMVP_PW RGD 36,42
C2807
SCD1U10V2KX-5GP 2N7002K-2-GP
84.2N702.J31
2nd = 84.2N702.031
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
THERMAL SENSOR SMSC EMC2103
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
28
of
94
5
4
3
2
1
AUDIO CODEC
AUD_LDO_OUT_3D3V
AUD_5V
5V_S0
KBC_BEEP
1
DY
C2916
SC22P50V2JN-4GP
PORTB_R
PORTB_L
B_BIAS
BAT54CGP-GP
AUD_PC_BEEP_C C2917 1
2 SCD1U10V2KX-5GP
AUD_PC_BEEP 10
PC_BEEP
C_BIAS
PORTC_R
PORTC_L
1
2 100R2J-2-GP
Q2903
R2905
10KR2J-3-GP
G
27
39
38
37
AMP_MUTE#
NC#25
NC#24
D
S
40
1
DMIC_CLK
DMIC_1/2
AVEE
FLY_N
FLY_P
SCD1U25V2ZY-1GP
2
1
SCD1U25V2ZY-1GP
2
1
C2925
C2930
Port Configuration
Port A:
Port B:
Port C:
Port G:
Port J:
AUD_SENSE_A
36
Headphone jack
Microphone jack
Internal stereo speakers
Internal stereo digital mic
C
35
34
33
32
31
30
AUD_PORTC_R
AUD_PORTC_L
C2922 1
C2923 1
2 SC2D2U10V3KX-1GP
2 SC2D2U10V3KX-1GP
AUD_PORTC_R_C 58
AUD_PORTC_L_C 58
25
24
23
22
21
20
19
JACK DETECT RESISTORS
AUD_PORTA_R 58
AUD_PORTA_L 58
AUD_AVEE
AUD_FLY_N
AUD_FLY_P1
2
C2919
SC2D2U10V3KX-1GP
41
C2920
Close to Pin36
C2921
SENSE PIN A
AUD_SPK_R+
AUD_SPK_R-
AUD_SPK_L-
AUD_SPK_L+
AUD_3D3V
DY
2 0R2J-2-GP
R2911 1
2 0R2J-2-GP
DY
AUD_SPK_R+_L
1
2 0R2J-2-GP
R2910 1
2 0R2J-2-GP
AUD_SPK_R-_L
58
R2913
1
2 0R0805-PAD-1-GP
R2909 1
2 0R2J-2-GP
AUD_SPK_L-_L
58
R2908 1
2 0R2J-2-GP
AUD_SPK_L+_L
58
1
1
R2922
58
R2915
5K11R2F-L1-GP
B
2
B
2 0R0805-PAD-1-GP
1
C2929
SC10U10V5ZY-1GP
2
1
C2928
R2921
R2914
D
Layout Note: Path from +5V to LPWR_5.0 and
RPWR_5.0 must be very low resistance ( <0.01 ohms).
SC10U10V5ZY-1GP
2
1
SCD1U25V2ZY-1GP
2
1
SCD1U25V2ZY-1GP
2
1
C2927
GND
RIGHT+
16
71.20671.A03
14
For EMI issue.
11
CX20671-21Z-GP
LEFT-
C2933
SC33P50V2JN-3GP
RIGHT-
DY
LEFT+
C2934
SC33P50V2JN-3GP
AUD_DMIC_CLK_R
13
DY
2
1
2nd = 84.2N702.031
2 100R2F-L1-GP-U
1
1
84.2N702.J31
PORTA_R
PORTA_L
2
R2907
49 AUD_DMIC_CLK
49 AUD_DMIC_DATA
2N7002K-2-GP
3D3V_S0
SPDIF
GPIO0/EAPD#
GPIO1/SPK_MUTE#
2
27 BEEP_ENABLE
17
15
12
SENSE_A
1
R2906 1
CLASS_D_REF
RPWR_5_0
27
28
AVDD_5V
LPWR_5_0
29
FILT_1_65
AVDD_3_3
VAUX_3_3
VDD_IO
DVDD_3_3
AVDD_HP
2
7
18
26
3
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
C2924
SC10U10V5ZY-1GP
2
1
27
C2915
SC6D8P50V2DN-GP
1
AUD_PC_BEEP_C_R
DY
C2914
SC6D8P50V2DN-GP
2
AUD_SDATA_OUT
1
3
AUD_SDATAIN
2 33R2J-2-GP
DY
5
8
6
4
RESET#
2 0R3J-0-U-GP
AUD_5V
SCD1U25V2ZY-1GP
2
1
R2912 1
HDA_SDIN0
2
2
HDA_SPKR
AUD_SYNC
2
21
D2901
21
U2901
9
21 HDA_CODEC_BITCLK
C2926
C2913
FILT_1_8
C2912
SCD1U25V2ZY-1GP
2
1
R2903
SC10U10V5ZY-1GP
2
1
10KR2F-2-GP
2
1
DY
1
Place bypass caps very close to device.
AUD_CLASSDREF
1
2
AUD_FILT_1D8V
C2911
2 0R5J-5-GP
AUD_3D3V
AU_GND
SCD1U10V2KX-5GP
SCD1U25V2ZY-1GP
2
1
C2910
1
C2904
R2902
C2909
DY
R2901
AU_GND
C2907
21 HDA_CODEC_RST#
C
C2903
SC10U10V5ZY-1GP
2
1
SCD1U25V2ZY-1GP
2
1
SCD1U25V2ZY-1GP
2
1
SC10U10V5ZY-1GP
2
1
C2906
C2902
AUD_3D3V
SC10U10V5ZY-1GP
2
1
SCD1U25V2ZY-1GP
2
1
1
C2908
2
SC1U10V2KX-1GP
AUD_3D3V
C2905
C2901
SC10U10V5ZY-1GP
2
1
AUD_3D3V
D
SCD1U25V2ZY-1GP
2
1
SC1U10V2KX-1GP
2
1
AUD_FILT_1D65V
AUD_SENSE_A
AUD_SENSE_A
58
Should be used at least 20 MIL width copper line for
"AUD_SPK_L+","AUD_SPK_L-", "AUD_SPK_R+", "AUD_SPK_R-
AU_GND
Place R2913/R2914 under CODEC,
and place R2921/R2922 near CODEC
21 HDA_CODEC_SDOUT
1
1
S
1
2
1
2
2
EC2901
SC1KP50V2KX-1GP
Q2902
G
D
AUD_SYNC
2N7002K-2-GP
A
1
1
D
EC2902
SC1KP50V2KX-1GP
DY
2
C2932
SC100P50V2JN-3GP
G
EC2903
SC1KP50V2KX-1GP
Place EMI components
close to audio codec.
2
2
Q2901
2
21 HDA_CODEC_SYNC
R2920
33KR2F-GP
AUD_SDATA_OUT_G
DY
C2931
SC33P50V2JN-3GP
EC2904
SC1KP50V2KX-1GP
DY
R2918
33KR2F-GP
AUD_SYNC_G
2
AUD_3D3V
1
AUD_3D3V
1
AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+
20100705_AUD
S
AUD_SDATA_OUT
2N7002K-2-GP
84.2N702.J31
A
84.2N702.J31
2nd = 84.2N702.031
2nd = 84.2N702.031
R2919 1
2 0R2J-2-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
AUDIO CODEC
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
29
of
94
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
AMP
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
30
of
94
5
4
3
2
1
D
D
3D3V_LAN_S5
R3135 1
DY
2 0R3J-0-U-GP
AO3419L-GP
1
R3133
100KR2J-1-GP
84.03419.031
LAN_PWR_ON_T
C
C3150
SC1U10V2KX-1GP
D
2
D
2
C3152
SCD1U16V2KX-3GP
-1 0114 S
Q3103
G
1
C3151
SCD1U10V2KX-5GP
2
C
2
1
1
3D3V_S5
Q3104
2N7002K-2-GP
84.2N702.J31
S
G
2nd = 84.2N702.031
18 LAN_PWR_ON
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LAN PWR SW
Size
A4
Document Number
Date:
5
4
3
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
2
31
of
1
94
A
5
4
3
3D3V_S0
2
1
3D3V_CARD_S0
R3201
1
2
0R3J-0-U-GP
SC1U10V2KX-1GP
2
1
C3202
C3203
+3.3V_RUN_CARD
U3201
CDR_PCIE_VOUT_VIN
SD_W P
SD_D1
SD_D0
R3202 1
R3203 1
2 0R2J-2-GP SD_D1_U
2 0R2J-2-GP SD_D0_U
74
SD_CLK
R3204 1
2CDR_MFIO5_MEDIA
33R2J-2-GP
74
SD_CMD
R3205 1
74
74
SD_D3
SD_D2
R3206 1
R3207 1
2CDR_MFIO8_MEDIA
0R2J-2-GP
2 0R2J-2-GP SD_D3_U
2 0R2J-2-GP SD_D2_U
RICOH recommends strongly, Trace length Difference
among these SDXC signals are smaller than 0.5 inches.
MDIF_05, SD_CLK
MDIF_08, SD_CMD
MDIF_02, SD_DATA0
MDIF_01, SD_DATA1
MDIF_11, SD_DATA2
MDIF_1O, SD_DATA3
1
Please place these capacitors,
for PCIE_VIN as close to R5U220 as possible.
CDR_SD18C_R
74
C3207
74
74
C3210
SC1U10V2KX-1GP
2
SCD1U10V2KX-5GP
2
1
C3208
C3201
Please place these capacitors
for VCC_3Vx as close to R5U220 as possible
Please apply wide trace for MF_VOUT
between R5U220 and SD Card Slot.
- 2A (W=2mm) Recommended.
- Please consider the number of
vias when layer of MF_VOUT is changed.
C3204
SCD1U10V2KX-5GP
2
1
C3209
C3205
SCD1U10V2KX-5GP
2
1
C
SCD1U10V2KX-5GP
2
1
C3206
SC10U6D3V3MX-GP
2
1
SCD1U10V2KX-5GP
2
1
Please place these capacitors,
for PCIE_VOUT as close to R5U220 as possible.
SCD1U10V2KX-5GP
2
1
D
SCD1U10V2KX-5GP
2
1
D
74
SD_DET#
12
37
48
NCTEST0
NCTEST1
NCTEST2
NCTEST3
NCTEST4
1
4
5
6
7
VCC_3V
VCC_3V
VCC_3V
13
32
47
PCIE_VOUT
PCIE_VOUT
PCIE_VOUT
19
23
PCIE_VIN
PCIE_VIN
36
11
24
22
30
MF_VOUT
TEST
RREF
CPO
SD18C
25
26
27
28
29
31
33
34
35
38
39
40
41
42
43
MDIF0
REFCLKN
MDIF1
REFCLKP
MDIF2
PERST#
MDIF3
RXC
MDIF4
RXN
MDIF5
RXP
MDIF6
TXN
MDIF7
TXP
MDIF8
MDIF9
MDIF10
CLKREQ#/UDIO1
MDIF11SROMEN/SCL/UDIO2
MDIF12
SDA/UDIO3
MDIF13
UDIO4
MDIF14
UDIO5
15
14
10
17
18
16
21
20
8
9
MFCD0#
MFCD1#
GND
46
45
44
2
3
R3208
5K1R2F-2-GP
CDR_RREF_MEDIA
1
2
CDR_CPO_MEDIA1
2
Please apply external parts, R456, C457, R415 for RXC,
CPO, and RREF, as close as possible to R5U220.
C3214
SC8200P25V2JX-GP
PLT_RST#_CR
CDR_RXC_MEDIA 1
SCD022U25V2KX-GP
R3209
2 0R2J-2-GP
1
2
C3213
PCIE_RXN3_C C3212 1
PCIE_RXP3_C C3211 1
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
CDR_UDIO0_MEDIA
CDR_LUDIO2_R 1
2
CLK_PCIE_CR# 20
CLK_PCIE_CR 20
PLT_RST#
5,18,27,36,65,66,71,80,82,83
PCIE_TXN3
PCIE_TXP3
PCIE_RXN3
PCIE_RXP3
R3210
33KR2F-GP
A
Please apply capacitor C3210 for SD18C
as close as possible to R5U220.
Please apply 50 ohm impedance control
for these SDXC signals;
MDIF_05, SD_CLK
MDIF_08, SD_CMD
MDIF_02, SD_DATA0
MDIF_01, SD_DATA1
MDIF_11, SD_DATA2
MDIF_1O, SD_DATA3
MEDIA I/F
MFIO00
MFIO01
MFIO02
MFIO03
MFIO04
MFIO05
MFIO06
MFIO07
MFIO08
MFIO09
MFIO10
MFIO11
MFIO12
MFIO13
MFIO14
MFCD0#
MFCD1#
SD/MMC
SDWP#
SD_D1
SD_D0
(SD_D7)
(SD_D6)
SD_CLK
(SD_D5)
SD_CDM
(SD_D4)
SD_D3
SD_D2
SDDC#
MEMORYSTICK XD
XD_D7
MSBS
XD_D6
MS_D1
XD_D5
XD_D4
XD_D3
(MS_D5)
MSD0
XD_D2
XD_D1
(MS_D4)
XD_D0
XD_WP#
MS_D2
(MS_D6)
XD_WE#
MS_D3
XD_ALE
XD_CLE
XD_CE#
(MS_D7)
XD_RE#
MS_CLK
XD_R/B
XDCD0#
MSINS#
XDCD1#
PCIE_CLK_CR_RQ2#
20
B
3D3V_S0
Q3201
C
R1
B
E
PDTC115TE-GP
Please use Microstrip trace routing
for these SDXC signals
MDIF_05, SD_CLK
MDIF_08, SD_CMD
MDIF_02, SD_DATA0
MDIF_01, SD_DATA1
MDIF_11, SD_DATA2
MDIF_1O, SD_DATA3
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5
C
Please apply AC Coupling capacitors, C455 and C454,
for TXP/TXN as close as possible to R5U220.
Please apply differential impedance control for these
signal pairs
in conformity with Motherboard Design Guide;
CLK_PCIE_CR, CLK_PCIE_CR#
PCIE_TXN3, PCIE_TXP3
PCIE_RXN3_C, PCIE_RXP3_C
PCIE_RXN3, PCIE_RXP3
49
71.5U220.A03
B
20
20
20
20
Please apply equal trace length for these signal pairs;
CLK_PCIE_CR, CLK_PCIE_CR#
PCIE_TXN3, PCIE_TXP3
PCIE_RXN3_C, PCIE_RXP3_C
PCIE_RXN3, PCIE_RXP3
R5U220-QFN48P-1-GP
RICOH recommends strongly, the trace length
for these SDXC signals are less than 6-inches.
MDIF_05, SD_CLK
MDIF_08, SD_CMD
MDIF_02, SD_DATA0
MDIF_01, SD_DATA1
MDIF_11, SD_DATA2
MDIF_1O, SD_DATA3
Please apply capacitors for MF_VOUT
as close as possible to connector
Otherwise
4
3
2
R5U220 (CARD READER)
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
32
of
94
A
B
C
D
E
4
4
3
3
BLANK
2
2
<Core Design>
Wistron Corporation
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
1394
Size
A4
Document Number
Date: Tuesday, November 09, 2010
A
B
C
Rev
SB
LLW-1 / LGG-1
D
Sheet
33
of
E
94
1
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Smart Card Reader
Size
A4
Document Number
Date: Tuesday, November 09, 2010
5
4
3
Rev
SB
LLW-1 / LGG-1
2
Sheet
34
of
1
94
A
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB3.0
Size
A4
Document Number
Date: Tuesday, November 09, 2010
5
4
3
Rev
SB
LLW-1 / LGG-1
2
Sheet
35
of
1
94
A
A
B
D
E
Power Sequence
DY
IMVP_PW RGD R3614 1
C
2 0R2J-2-GP SYS_PW ROK
DY
3D3V_S5
R3609 1
2 0R2J-2-GP
IMVP_PW RGD_R
1
B
19,27 S0_PW R_GOOD
R3610 1
2 0R2J-2-GP
S0_PW R_GOOD_R
2
A
PM_SLP_S3#
5
VCC
R3613 1
4
Y
3
2 0R2J-2-GP
B
2
A
3
19
VCC
5
Y
4
PW R_1D05V_EN 45
4
GND
74LVC1G08GW -1-GP
C3612
SCD01U50V2KX-1GP
2
73.01G08.L04
= 73.7SZ08.DAH
73.01G08.L04
2ND = 73.7SZ08.DAH
2
C3613
2ND
SCD01U50V2KX-1GP
SYS_PW ROK
1
GND
74LVC1G08GW -1-GP
DY
1
19,37,45,46,47 RUNPW ROK
1
4
28,42 IMVP_PW RGD
3D3V_S5
U3609
U3603
Change to Diode??
5V_S5
5V_S0
3D3V_S5
DY
C3607
SCD1U25V3KX-GP
1
1
2
3
4
2
RUN_ENABLE
Q3604
NDS0610-G-GP
S
D
1
1
1
3D3V_AUX_S5
C3606
R3621
330KR2J-L1-GP
PS_S3CNTRL
37
84.04468.037
2
Q3606
2N7002K-2-GP
3D3V_S0
D3602
MMPZ5239BGP-GP
U3607
S
S
S
G
D
D
D
D
3
84.2N702.J31
2nd = 84.2N702.031
3D3V_S5
1
2
3
4
A
2
R3620
10KR2J-3-GP
SCD22U25V3KX-GP
2
1
Z_12V_G3
2
2 330KR2J-L1-GP
1
G
R3618 1
2 100KR2J-1-GP PS_S3CNTRL
8
7
6
5
S
2 10KR2J-3-GP Z_12V
3
R3608 1
AO4468-GP
G
R3619 1
R3626
0R2J-2-GP
8
7
6
5
K
DCBATOUT
D
D
D
D
D
Run Power
U3608
S
S
S
G
PM_SLP_S3#
AO4468-GP
2 10KR2J-3-GP
R3617
100KR2J-1-GP
Z_12V_D4
84.04468.037
RUN_ENABLE_S
2
R3612 1
Q3605
Q3603
G
PM_SLP_S3
D
S
4
3
5
2
6
1D5V_S0
1
2
3
4
1
2N7002KDW -GP
2N7002K-2-GP
84.2N702.J31
84.2N702.A3F
2nd = 84.DM601.03F
2
2nd = 84.2N702.031
1D5V_S3
PM_SLP_S3#
1
19,27,37,47,82 PM_SLP_S3#
2
U3605
S
S
S
G
D
D
D
D
8
7
6
5
SIR460DP-T1-GE3-GP
C3611
SCD01U50V2KX-1GP 84.00460.037
2nd = 84.08039.037
2
1D5V_S0 Total= 15A
MAX Current 3000 mA
Design Current 2100 mA
1D05V_VTT
1 56R2F-1-GP
20100805 V1.8
H_THERMTRIP# 5,22,85
2 1KR2J-1-GP
H_PW RGD_R
R3616 2
1 4K7R2J-2-GP
PM_SLP_S3#
1
2
3
4
VCC
ON
DIS2
GND
NC#9
PG
G1/G2
S/DIS1
D
2
1
1
SLG_RUN_ENABLE
74.55221.0E3
<Core Design>
3
DY
9
8
7
6
5
SLG55221-130010VTR-GP
2
1
3V_5V_EN
PURE_HW _SHUTDOW N#
1
27,28
D3601
BAS16GP-GP
R3603 2
1 2KR2F-3-GP
Wistron Corporation
S5_ENABLE
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
27
Title
R3602
200KR2J-L1-GP
2
POWER SEQUENCE
Size
A3
Date:
A
DY
R3615
0R2J-2-GP
R3632
2K2R2J-2-GP
41
5V_S0 3D3V_S0
5V_S5
U3610
2
PLT_RST#
C3602
SCD1U10V2KX-5GP
5V_S5
Q3601
CHT2222AGP-GP-U
1
5,18,27,32,65,66,71,80,82,83
B
2
DY
C
R3601 1
1
5,22 H_CPUPW RGD
RUN_ENABLE_S
1
DY
E
R3622 2
B
C
D
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
E
36
of
94
5
4
3
2
1
Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
0D75V_S0
1
2
DY
2 0R2J-2-GP
R3704
220R2J-L2-GP
2
D
R3703
22R2J-2-GP
2
DY
D
R3707 1
D
1D5V_S0
1
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
D
Q3708
S
+V_SM_VREF_CNT 9
2
R3705
100KR2J-1-GP
Q3702
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2nd = 84.2N702.031
1
2nd = 84.2N702.031
G
84.2N702.J31
2nd = 84.2N702.031
PM_SLP_S3# 19,27,36,47,82
PS_S3CNTRL
S
G
2N7002K-2-GP
DY
Q3701
2N7002K-2-GP
D
G
2 0R2J-2-GP +V_SM_VREF
S
R3708 1
7,14 M_VREF_DQ_DIMM0
PS_S3CNTRL
Q3704
G
36 PS_S3CNTRL
0D75V_EN
D
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
S
1D5V_S3
C
C
1
2N7002K-2-GP
84.2N702.J31
2nd = 84.2N702.031
1
3D3V_S0
1
S
1
2
3
2 R3711 1
0R0402-PAD
G
0D75V_EN 46
2N7002K-2-GP
S
DY
84.03904.L06
2ND = 84.03904.P11 2N7002K-2-GP
3rd = 84.03904.L06
PM_SLP_S3#
SM_DRAMRST#_D 1
D
0D75V_EN_L
D
Q3706
PMBS3904-1-GP
5 SM_DRAMRST#
1
2
84.2N702.J31
2nd = 84.2N702.031
1
DY
R3716
0R2J-2-GP
R3721
1KR2J-1-GP
2
DDR3_DRAMRST#
14,15
C3702
SC100P50V2JN-3GP
84.2N702.J31
2nd = 84.2N702.031
DY
C3705
SCD1U10V2KX-5GP
DRAMRST_CNTRL_PCH
20
2
C3704
SCD1U10V2KX-5GP
G
S3 Power Reduction Circuit
SM_DRAMRST#
Q3703
1
2
1
DY
2
DY
R3712
10KR2J-3-GP
Q3705
2
1
R3715
4K7R2J-2-GP
2
11.5V_RUN_CPU_EN
R3710
0R2J-2-GP
DY
1.5V_RUN_CPU_EN#
DY
2 R3709
2
R3714
100KR2J-1-GP
1D5V_S0
0R2J-2-GP 1
2
DY
R3706
1KR2J-1-GP
DY
1.05VTT_PW RGD 45,48
2
5V_S5
B
B
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
3D3V_S5
1
C3703 2
3D3V_S5
R3718
200R2F-L-GP
2 0R2J-2-GP
2 0R2J-2-GP
0D75V_EN_1
DY
C3701
SCD1U10V2KX-5GP
1
1
IN B
VCC
5
2
IN A
3
GND OUT Y
4
R3702
200R2F-L-GP
VDDPW RGOOD_R 1
74VHC1G09DFT2G-GP
OD AND gate required
2
R3719
130R2F-1-GP
VDDPW RGOOD 5
2
DY
U3701
2
R3713 1
1
R3701 1
45,48 1.05VTT_PW RGD
2
19,36,45,46,47 RUNPW ROK
1DRAMRST_CNTRL_PCH
SCD047U16V2KX-1-GP
CEKLT V1.0: PCH to 1K,CUP to 200R
2
5,19 PM_DRAM_PW RGD
1D5V_S0
DY
R3720
0R2J-2-GP
73.01G09.AAH
1
2ND =
<Core Design>
A
DY
5,19 PM_DRAM_PW RGD
R3722 2
1VDDPW RGOOD_R
0R2J-2-GP
For U3701 not OD AND gate
R3719 to 64.15015.6DL
R3720 to 64.75005.6DL
R3702 to DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
SM_DRAMPWROK must have a maximum of 15ns rise or fall time
over VDDQ * 0.55± 200mV and the edge must be monotonic
Size
A3
Date:
5
4
3
A
2
ADAPTER OCP / S3 reduction
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
37
of
94
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
DCIN_JACK
LLW-1 / LGG-1
Date: Tuesday, November 09, 2010
5
4
3
2
Sheet
38
Rev
SB
of
1
94
A
5
4
3
2
1
D
D
BT+
1
PC3902
SC2200P50V2KX-2GP
1
2
PC3901
SCD1U50V3KX-GP
2
1
BATTERY CONNECTOR
2
F3901
FUSE-20A24V-1-GP
C
C
BAT1
40 BATT_SENSE
PR3901 1
2 0R2J-2-GP
BT+_F39011
2
BAT_VCC
BAT_VCC
3
4
I2C_CLK
I2C_DATA
5
TEMP
PRN3901
2
TP3901
TP3902
TP3903
TP3904
PC3904
SC10P50V2JN-4GP
1
PL3903
MLVS0402M04-GP
DY
PC3903
SC10P50V2JN-4GP
NP1
NP2
NP1
NP2
GND
GND
6
7
TYCO-CON7-30-GP
20.81506.007
2
DY
PL3902
MLVS0402M04-GP
1
DY
PL3901
MLVS0402M04-GP
2
DY
DY
8
9
2
PC3905
SC1000P50V3JN-GP-U
2
A
PD3901
MMPZ5232BGP-GP
DY
1
1
SRN33J-7-GP
1
BATA_SCL_1
BATA_SDA_1
BAT_IN#_1
1
K
8
7
6
5
2
1
2
3
4
27,40 BAT_SCL
27,40 BAT_SDA
27 BAT_IN#
8
9
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
BAT_IN#_1
BATA_SDA_1
BATA_SCL_1
BT+_F3901
B
B
Table 39.1- Surface Mount Zener ESD multi-source
Supplier
Description
Lenovo P/N
Wistron P/N
CHENMKO
MMPZ5232BGP
N/A
83.5R603.R3F
DIODES
MMSZ5232BS-7-F
N/A
83.5R603.K3F
PANJIT
MMSZ5232BS
N/A
83.5R603.Q3F
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5
4
3
2
BATT_CONN
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
39
SB
of
94
5
4
3
AD+ total power
NEAR
AD+
PU4001
D
D
D
D
S
S
S
G
1
2
3
4
P1403EV8-GP
65w
187k
49.9k
90w
121k
49.9k
AD+ total power
80w
R1
R2
137k
49.9k
DCBATOUT
BT+
PR4002
100KR2J-1-GP
84.P1403.B37
AD+_TO_SYS
1
2
1
2
3
4
AD+
PR4004
D01R3721F-GP-U
2
D
R2
1
1
8
7
6
5
R1
2
PU4002
S
S
S
G
D
D
D
D
8
7
6
5
D
23
PGND
19
CSOP
18
CSON
17
NC#14
1
A
2
PU4005
SIS412DN-T1-GE3-GP
PC4016
2
1
SCD1U50V3KX-GP
74.24745.073
NC#16
16
VFB
15
BT+_R 1
2
D01R3721F-GP-U
PG4003
DY
PC4024
SC470P50V2KX-3GP
DY
PG4004
B
20100518 WAYNE
BATT_SENSE
1
BATT_SENSE 39
MAX8731A_CSIP
PC4015
SCD1U25V2ZY-1GP
MAX8731A_CSIN
2
6 FBO
BQ24745_EAI
5 EAI
BQ24745_EAO
4 EAO
BQ24745_VREF
3
BQ24745_CHG_ON 7 VREF
CE
12 GND
PC4014
SC1U10V3KX-3GP
BQ24745RHDR-GP
PR4019
2D2R3-1-U-GP
84.00412.037
VICM
GND
1
20
1
2
IND-5D6UH-39-GP
68.5R610.10P
24745_LOW _G
29
2 PC4013
2
1
2
SC56P50V2JN-2GP 1
PR4014
1
2BQ24745_FBO
4K7R2J-2-GP
LGATE
BQ24745_LX1
PR4017
GAP-CLOSE-PWR-3-GP
PC4012
PR4016
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
1BQ24745_EAO_RC2
1
8
SDA
PL4001
1
2
PC4017
SCD1U50V3KX-GP
1
9
C
BT+
24745_HIGH_G
SCL
2
BAT_SDA
24
SC1U10V3KX-3GP
1
27,39
UGATE
CH520S-30GP-GP-U
2
10
BQ24745_BST
BQ24745_VDDP
2
BAT_SCL
25
21
PC4006
ACOK
1
27,39
BOOT
VDDP
PC4005
GAP-CLOSE-PWR-3-GP
PC4011
SC220P50V2KX-3GP
84.00412.037
S
S
S
G
B
PC4009
1
2
A
2
PR4011
1
2BQ24745_ACOK 13
0R0402-PAD
CHG_AGND
BQ24745_IINP
SC150P50V2JN-3GP
PC4010
1
2 BQ24745_FBO_RC
PR4015
1
2
200KR2F-L-GP
PD4003
K
D
D
D
D
AD_IA
BQ24745_CSSN
PR4012
BQ24745_ICOUT 1
2STOP_CHG#
PC4023
SCD1U25V2ZY-1GP
2
1
27
26
CSSN
ICOUT
VDDSMB
PU4004
SIS412DN-T1-GE3-GP
SC10U25V5KX-GP
2
1
CSSP
0R2J-2-GP
14
27
1
28
PHASE
PR4013
1
2
0R0402-PAD
2
2
1
CHG_AGND
CHG_AGND
CHG_AGND
SCD1U25V3KX-GP
CHG_AGND
PC4008
SC1U10V3KX-3GP
AC_IN
PC4003
SCD1U50V3KX-GP
DCBATOUT
2
5
6
7
8
1
PC4007
1
SC10U25V5KX-GP
2
1
ACIN
1
5
6
7
8
2
SCD1U50V3KX-GP
2
1
2
DCIN
BQ24745_ACIN
11
2
SCD01U50V2KX-1GP
2
1
49K9R2F-L-GP
2
1
22
27
S
S
S
G
PR4010
BQ24745_DCIN
STOP_CHG#
D
D
D
D
PR4006
316KR3F-2-GP
PR4009
10KR2F-2-GP
PC4004
PC4002
2
1BQ24745_CSSP
83.SMF18.AAH
DY
4
3
2
1
3D3V_AUX_S5
C
2
49K9R2F-L-GP
CHG_AGND
PU4003
1
BQ24745_ACOK
PD4002
SMF18A-GP
4
3
2
1
R2
3D3V_AUX_S5
PG4002
1
1
PC4001
1
PR4008
20100707
CHG_ICREF 2
AD+
PR4007
121KR2F-L-GP
ICREF
5
6
84.2N702.A3F
2nd = 84.DM601.03F
4
DC_IN_D
PQ4001
2N7002KDW -GP
R1
1
SC1U25V5KX-1GP
2
1
3
2
1
K
BQ24745_VREF
GAP-CLOSE-PWR-3-GP
1
PG4001
PD4001
1SS400GGP-GP
GAP-CLOSE-PWR-3-GP
AD+_G_1
P1403EV8-GP
84.P1403.B37
PR4005
470KR2F-GP
A
PR4003
49K9R2F-L-GP
2
PR4001
10KR2F-2-GP
2
2
1
STOP_CHG#
connects to KBC
20100518 WAYNE
AD+
K
AD+_G_2
BT+
1
PC4025
SC10U25V6KX-1GP
PC4022
SCD1U50V3KX-GP
2
1
PC4021
SC10U25V6KX-1GP
2
1
PC4020
SC10U25V6KX-1GP
2
1
PC4019
SC10U25V6KX-1GP
2
3D3V_AUX_S5 BQ24745_VREF
2
PC4018
SC10U25V6KX-1GP
2
1
CHG_AGND
1
CHG_AGND
PRN4001
1
2
3
4
8
7
6
5
CHG_ON#
AC_IN
27
BQ24745_CHG_ON
PQ4002
S
A
BQ24745_CHG_ON
PR4018 1
2
1
SRN100KJ-8-GP-U
2 0R2J-2-GP
<Core Design>
D
DY
CHG_ON#
G
C4001
SCD1U10V2KX-5GP
2N7002K-2-GP
84.2N702.J31
CHG_ON#
Wistron Corporation
27
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AC_IN to KBC
Title
2nd = 84.2N702.031
Size
CHG_AGND
Date:
5
4
3
A
2
Charger_BQ24745
Document Number
Rev
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
40
SB
of
94
5
4
3
2
1
SSID = PWR.Plane.Regulator_5v3p3v
DCBATOUT
PWR_5V_DCBATOUT
1
PG4104
2
GAP-CLOSE-PWR
PG4105
1
2
3D3V_S5
D
3D3V_PWR
DCBATOUT
GAP-CLOSE-PWR
PG4122
1
2
PWR_3D3V_DCBATOUT
PG4106
2
1
1
GAP-CLOSE-PWR
PG4107
2
1
PG4101
2
GAP-CLOSE-PWR
PG4102
1
2
GAP-CLOSE-PWR
PG4108
2
1
GAP-CLOSE-PWR
PG4125
1
2
GAP-CLOSE-PWR
PG4103
1
2
GAP-CLOSE-PWR
PG4109
2
1
D
GAP-CLOSE-PWR
PG4124
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4110
2
1
GAP-CLOSE-PWR
PG4111
2
1
1
GAP-CLOSE-PWR
1
EC4102
SCD1U25V2KX-GP
2
GAP-CLOSE-PWR
PG4115
1
2
SIS406DN-T1-GE3-GP
BOOT1
22
PWR_5V_BOOT1 1
2D2R3J-2-GP
23
PWR_5V_UGATE1
PC4118
1
2
2PWR_5V_BOOT1_1
PR4106
G
GAP-CLOSE-PWR
PG4116
1
2
S
PWR_3D3V_UGATE2
SCD47U25V3KX-1GP
2
HG2
HG1
SCD47U25V3KX-1GP
PL4102
PL4101
1 S
2 S
3 S
4 G
1
S
PWR_3D3V_VOUT2
G
7
FB2
FB1
VO2
VO1
1
2
IND-2D2UH-122-GP
14
PWR_5V_FB1
27
PWR_5V_VOUT1
21
9528EN1 PR4130 2
17
9528ILIM1
G
S
DY
PC4103
SC470P50V2KX-3GP
4
9528ILIM2
EN2
EN1
ILIM2
ILIM1
NC#6
NC#19
DY
5
NC#5
PGOOD
20
PR4114
0R2J-2-GP
3V_5V_POK
1
PWR_5V3D3V_VREF
19
PC4125
SC10U6D3V3MX-GP
DY
PR4136
0R2J-2-GP
PR4132
0R2J-2-GP
2
DY
GAP-CLOSE-PWR-3-GP
PR4134
0R2J-2-GP
PC4126
SC10U6D3V3MX-GP
1 0R2J-2-GP
3D3V_AUX_S5
5V_AUX_S5
DY
A
1 0R2J-2-GP
Table 41.1 - POSCAP multi-source
Description
SANYO
6TPE220MAP
1
PR4133
0R2J-2-GP
1 0R2J-2-GP
5V_PWR_2
PR4123 2
Supplier
2
1
9528MCTL1
9528MCTL2
G9306
2
PR4122 2
PR4139 2
B
Close to VFB Pin (pin2)
PC4130
3D3V_PWR_2
A
5V_AUX_S5
1
PR4131
5V_AUX_S5
2
PR4135
5V_PWR_2
1
1
1
PR4119
21K5R2F-GP
DY
1
2
DY
13
2
1
GAP-CLOSE-PWR-3-GP
29
PG4119
1PWR_5V3D3V_VREG1
3D3V_PWR_2
2
BD95280MUV-GP
Close to VFB Pin (pin5)
9528MCTL2
PR4115
33KR2F-GP
2
AGND
9528MCTL1
16
1
FIN
18
SC1KP50V2KX-1GP
2
1
MCTL2
41K2R2F-GP
2
1
MCTL1
CTL
REG2
33
REF2V
75KR2F-GP
2
1
9
REG1
12
PWR_5V_FB1_R
PC4128
SC18P50V2JN-1-GP
2
PR4137
PC4122
2
DY
PR4110
100KR2J-1-GP
9528FS1
2
15
PG4123
2
Matsuki cap 220uF
6.3V, ESR=17mohm
2
FS1
28
68KR2F-GP
2
1
PR4138
FS2
1PWR_5V3D3V_VREG2
2
PC4131
10
2
PR4116
10KR2F-2-GP
B
DY
SCD22U10V2KX-1GP
2
1
DY
9528FS2
41K2R2F-GP
2
1
1 2
PWR_3D3V_FB2_R
PC4124
SC18P50V2JN-1-GP
1
2
2
PR4112
0R2J-2-GP
SC1KP50V2KX-1GP
2
1
1
DY
1
GAP-CLOSE-PWR
3D3V_S5
19
1
6
PG4120
2
GAP-CLOSE-PWR
1 0R2J-2-GP 3V_5V_EN
1
8
PTC4101
SE220U6D3VM-21-GP
1
2 0R2J-2-GP 9528EN2
PR4109 1
PC4120
SCD1U10V2KX-5GP
2
3V_5V_EN
C
1
36
PR4111
6K65R2F-GP
PG4117
PR4102
2D2R3-1-U-GP
PU4105
SIS406DN-T1-GE3-GP
25
1
DY 68.2R21B.10J
1
1
D
5
6
7
8
PWR_5V_LGATE1
2
PGND1
26
2
PGND2
24
1
DY
PC4102
SC470P50V2KX-3GP
11
LG1
2
2
32
PWR_3D3V_FB2
SW1
LG2
2
1
2
PU4102
SIS412DN-T1-GE3-GP
PR4101
2D2R3-1-U-GP
SW2
S
S
S
G
SANYO cap 220uF
6.3V, ESR=25mohm
D 8
D 7
D 6
D 5
DY
PG4121
31
GAP-CLOSE-PWR
PG4118
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR-3-GP
PTC4102
1
PWR_3D3V_LGATE2
PWR_5V_PHASE1
D
D
D
D
1
D
PWR_3D3V_PHASE2
4
3
2
1
68.3R31A.10V
GAP-CLOSE-PWR-3-GP
PC4119
ST220U6D3VDM-20GP
2
1
1
2
IND-3D3UH-116-GP
NEC-TOKIN
GAP-CLOSE-PWR
PG4114
1
2
DY
5V_PWR
3D3V_PWR
SCD1U10V2KX-5GP
2
1
1
2
1
2
1
5
6
7
8
BOOT2
PC4111
SC4D7U25V5KX-GP
4
3
2
1
2PWR_3D3V_BOOT2 3
2D2R3J-2-GP
PC4114
SC4D7U25V5KX-GP
2
C
PWR_3D3V_BOOT1 1
PR4105
VIN
S
S
S
G
1
2
3
4
PC4115
1
2
G
PU4104
D
S
S
S
G
U4103
S
PC4113
SCD01U50V2KX-1GP
30
2
PU4101
SIS412DN-T1-GE3-GP
PC4101
SC10U25V6KX-1GP
2
1
D
D 8
D 7
D 6
D 5
1
PC4110
SC4D7U25V5KX-GP
2
2
1
1
2
PC4112
SC4D7U25V5KX-GP
D
D
D
D
EC4101
SCD1U25V2KX-GP
PG4112
2
GAP-CLOSE-PWR
PG4113
1
2
PWR_5V_DCBATOUT
DCBATOUT
DY
5V_S5
5V_PWR
PWR_3D3V_DCBATOUT
<Core Design>
Lenovo P/N
Wistron P/N
N/A
77.22271.27L
V0J227M(25)12RE
N/A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
77.C2271.00L
Size
Date:
5
4
3
2
DC/DC 3D3V5V
LLW-1 / LGG-1
Document Number
Tuesday, November 09, 2010
1
Sheet
41
Rev
SB
of
94
5
4
PW R_CPUCORE_DOUT
2
1
1
PW R_CPUCORE_TRBST
2
PC4218
SC3300P50V2KX-1GP
PR4243
24K9R2F-L-GP
1
PR4249
24D9R2F-L-GP
1
PR4244
1K21R2F-2-GP
2
PC4219
SC3300P50V2KX-1GP
2 1
PC4222
1
SC100P50V2JN-3GP
2
2
2 PC4223
SC22P50V2JN-4GP
PC4224
2
1
PR4250
1KR2F-3-GP
2
PR4256
75KR2J-GP
1
2
SC2200P50V2KX-2GP
PR4251
6K19R2F-GPPW R_CPUCORE_COMP
8
1
2
1
PR4257
165KR2F-L-GP
2
2 PC4226
SC470P50V2KX-3GP
PR4253 1
2 PC4225
SC1200P50V2KX-1GP
1
1 PR4231
0R2J-2-GP
2
VSSSENSE
2
1
PW R_CPUCORE_CSCOMP
D
1
PR4258
NTC-220K-5-GP
PW R_CPUCORE_TSN
PC4220
SCD1U25V2KX-GP
2
PR4235
56R2F-1-GP
2
1
1
PR4234
75R2F-2-GP
2
1
C
2
PR4233
130R2F-1-GP
1D05V_VTT
PR4266
0R2J-2-GP
1
H_CPU_SVIDDAT
2
43
2 137KR3-GP
CSP1
43
D
PR4252 1
PR4212
2
1
10R2J-2-GP
CSN1
43
PR4213
2
1
10R2J-2-GP
CSN3
43
1
40
NC#40
41
NC#41
CSREF
IOUT
42
PR4216
24K3R2F-1-GP
2
1
PWR_CPUCORE_IOUT
1
2
43
44
CSSUM
45
PC4205
SCD1U25V2KX-GP
1
PWR_CPUCORE_ILIM
2
46
47
48
49
PWR_CPUCORE_TRBST
CSP3
PC4203
SC1KP50V2KX-1GP
5V_PWR
VSP
CSN2
39
2
TSENSE
CSP2
38
3
VRHOT#
CSN3
37
4
2 137KR3-GP
SDIO
CSP3
2 PR4214
0R2J-2-GP
1
C
CSN3
PC4215
36
1
2
6K98R2-GP
SCD047U25V2KX-GP
1
H_CPU_SVIDCLK
VR_SVID_ALERT#
PR4236
10KR2F-2-GP
5
SCLK
CSN1
35
6
ALERT#
CSP1
34
PC4213
1
2
PW R_CPUCORE_CSP1
1
2
SCD047U25V2KX-GP
1
PW R_CPUCORE_VCC
VCC
VRMP
13
TSENSEA
PWM3/VBOOT
31
PWM2/ISHED
30
IMAX
29
PWMA/IMAXA
28
VBOOTA
27
9 VCC_AXG_SENSE
2 PR4220
0R2J-2-GP
1
5V_PWR
PW R_CPUCORE_IMAX2 PR4210 1
PWR_CPUCORE_PWMA 44
2
TP4202
TPAD14-GP
PR4260
14K7R2F-L-GP
PR4259
53.6K_1%
63.4K_1%
PR4260
13.7K_1%
14.7K_1%
1
1
1
PR4218 1
24.9K_1%
23.2K_1%
PR4211
18.7K_1%
26.1K_1%
1
1
2
2
44
CSPA
44
PR4223
6K98R2-GP
71K5R3F-1-GP 1
2
2 PR4259
CSPA
44
PC4227
SC1200P50V2KX-1GP
PC4228
2
SC330P50V2KX-3GP
2
2
1
2
A
<Core Design>
PR4262
165KR2F-L-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
PR4263
NTC-220K-5-GP
1
2 SC39P50V2JN-1GP
2PR4219_R
PR4219
4K75R2F-1-GP
1
Title
Place close to
VCC_GFXCORE Inductor
2
Size
PC4208
SC2200P50V2KX-2GP
Date:
5
CSNA
2 1KR2F-3-GP
PC4207 1
PR4215
PR4229
0R2J-2-GP
SCD047U25V2KX-GP
PR4261
75KR2J-GP
2
For Discrete only,
UMA need to DY
5V_PWR
PR4246
0R2J-2-GP
PW R_CPUCORE_CSNA
PC4212
1
2
PW R_CPUCORE_CSCOMPA
PC4206
SC100P50V2JN-3GP
1
2PR4217_R 1
GT2_33A_3.9m
2
DY
B
0830
2
PC4204
SCD1U25V2KX-GP
PW R_CPUCORE_CSSUMA
PR4217
10R2J-2-GP
PR4208
10KR2F-2-GP
1
CSPA
CSNA
1
PR4211
26K1R2F-2-GP
1
1
26
25
CSSUMA
PWR_CPUCORE_CSPA
1
2
PR4215
23K7R2F-GP
2
1
24
23
IOUTA
CSCOMPA
22
DROOPA
21
TRBSTA
COMPA
19
DIFFOUTA
17
VSPA
FBA
16
1PWR_CPUCORE_ILIMA
20
ILIMA
0830
0830
2
PC4211
SC1KP50V2KX-1GP
1
GT1_24A_4.6m
43
PWR_CPUCORE_PWM1 43
PR4262_R
2
2
PR4238
0R2J-2-GP
PWR_CPUCORE_COMPA
1
PC4217
SC1KP50V2KX-1GP
2
PR4265
NTC-100K-11-GP
2
1PWR_CPUCORE_TRBSTA
18
2
PWR_CPUCORE_DOUTA
DY
PR4221
0R2J-2-GP
1PWR_CPUCORE_VSPA 15
1
9 VSS_AXG_SENSE
A
CSP1
PWR_CPUCORE_PWM3 43
PWR_CPUCORE_VBTA
NCP6131S52MNR2G-GP-U
1
1
32
43,44
PR4226
6K98R2-GP
2
12
PWR_CPUCORE_IOUTA
PW R_CPUCORE_TSNA
Place close to
VCC_GFXCORE hot spot
PWM1/ADDR
PWR_CPUCORE_DRON
43
43
41K2R2F-GP
PW R_CPUCORE_VRMP
PR4209
1KR2F-3-GP
PR4247
8K25R2F-1-GP
33
PR4207
11 ROSC
1
2 PW R_CPUCORE_ROSC
10KR2F-2-GP
PWR_CPUCORE_FBA
DCBATOUT
B
2
PR4201
2R3J-2-GP
1
2
PC4202
SCD01U50V2KX-1GP
1
2
ENABLE
PR4239 2
0R2J-2-GP
1
10
VR_RDYA
VSNA
PC4201 1
2
SC1U10V2KX-1GP
5V_PWR
PW
R_CPUCORE_RDYA 8
PR4237
10KR2F-2-GP
2 PR4206 PW R_CPUCORE_EN 9
0R2J-2-GP
1
19,48 D85V_PWRGD
2
DRON
VR_RDY
1PWR_CPUCORE_VSNA 14
3D3V_S0
7
CSP3
CSN1
1
PW R_CPUCORE_RDY
2
PC4221
SCD1U25V2KX-GP
2
1
1
28,36 IMVP_PWRGD
43
PR4228
1
2
PW R_CPUCORE_CSP3
2
PR4268
0R2J-2-GP
PW R_CPUCORE_CSREF
1
3D3V_S0
8 H_CPU_SVIDDAT
8 VR_SVID_ALERT#
8 H_CPU_SVIDCLK
53
PU4201
DROOP
H_PROCHOT_R#
CSCOMP
2
ILIM
2
1
COMP
5,27 H_PROCHOT#
1
PR4254
12K4R2F-GP
FB
1D05V_VTT
PG4201
GAP-CLOSE-PW R-3-GP
GND
PWR_CPUCORE_VSP
2
PR4203
75R2F-2-GP
TRBST
2
PWR_CPUCORE_VSN
1
50
PR4264
NTC-100K-11-GP
2
PR4245
8K25R2F-1-GP
VSN
Place close to
VCC_CORE hot spot
1
1
PC4216
SC1KP50V2KX-1GP
51
2
PWR_CPUCORE_DOUT
1
52
1 PR4230
0R2J-2-GP
2
VCCSENSE
DIFFOUT
8
PWR_CPUCORE_FB
PW R_CPUCORE_CSSUM
PR4204
10KR2F-2-GP
2
1
1
1
PR4205
10KR2F-2-GP
2
2
Place close to
VCC_CORE Inductor
2
1
PR4242
10R2J-2-GP
1
3
4
3
2
DC/DC CPU CORE1 _NCP6131
Rev
LLW-1 / LGG-1
SB
Document Number
Tuesday, November 09, 2010
Sheet
1
42
of
94
5
4
3
2
1
DCBATOUT
3
4
S
G
PC4301
1
PW R_VCORE1_HG
PW R_VCORE1_PH
8
7
6
5
PW R_VCORE1_LG
5
4
3
FLAG
9
PC4302
SC1U10V2KX-1GP
DRVH
SW
GND
DRVL
NCP5911MNTBG-GP
2
1
BST
PWM
EN
VCC
S
S
G
5V_PWR
1
2
3
4
1
2
1
2
PG4311
84.06725.030
TP4303
TPAD40-GP
1
GAP-CLOSE-PWR-3-GP
PW R_VCORE1_BT1
1
2PW R_VCORE1_EN
PR4301 49D9R2F-GP
PU4312
IRF6725MTRPBF-GP-U
2
D
D
D
D
PU4301
42 PWR_CPUCORE_PWM1
42,44 PWR_CPUCORE_DRON
2
L-D36UH-1-GP
PG4312
PTC4303
SE330U2D5VDM-1GP
1
PW R_VCORE1_LG 1 PR4313 2 VCORE1_LG
0R0402-PAD
PTC4304
SE330U2D5VDM-1GP
2
SCD22U25V3KX-GP
PL4301
1
1
2
GAP-CLOSE-PWR-3-GP
PR4302
2D2R3-1-U-GP
1
D
VCC_CORE
2
2PW R_VCORE1_BT1_R
7
6
2
1
1
PW R_VCORE1_HG 1 PR4312 2 VCORE1_HG
0R0402-PAD
PW R_VCORE1_PH
PC4305
2
D
PC4304
SC4D7U25V6KX-3GP
84.06721.030
PC4303
1
79.10712.L02
2
2
79.10712.L02
D
D
D
D
PU4313
IRF6721SPBF-GP-U
SC4D7U25V6KX-3GP
1
6
5
2
1
PTC4308
SE100U25VM-L1-GP
SC4D7U25V6KX-3GP
1
DCBATOUT
PTC4301
SE100U25VM-L1-GP
2
1
DCBATOUT
CSN1
42
CSP1
42
PC4306
C
1
2
PW R_VCORE3_BT3_R
PR4303
2D2R3-1-U-GP
1
C
2
SCD22U25V3KX-GP
1
2PW R_VCORE3_EN
PR4304 49D9R2F-GP
PC4307
SC1U10V2KX-1GP
PW R_VCORE3_HG
PW R_VCORE3_PH
8
7
6
5
DRVH
SW
GND
DRVL
PW R_VCORE3_LG
NCP5911MNTBG-GP
2
1
5V_PWR
BST
PWM
EN
VCC
9
42 PWR_CPUCORE_PWM3
42,44 PWR_CPUCORE_DRON
1
2
3
4
FLAG
PU4306
PW R_VCORE3_BT3
PC4310
2
1
2
B
SC4D7U25V6KX-3GP
3
4
S
G
PW R_VCORE3_HG
1 PR4309 2 VCORE3_HG
0R0402-PAD
PW R_VCORE3_PH
PC4309
SC4D7U25V6KX-3GP
1
2
84.06721.030
SC4D7U25V6KX-3GP
6
5
2
1
PC4308
D
D
D
D
PU4307
IRF6721SPBF-GP-U
1
DCBATOUT
B
VCC_CORE
PL4302
1
2
1
TP4301
TPAD40-GP
42
1
1
PTC4306
SE330U2D5VDM-1GP
PTC4307
SE330U2D5VDM-1GP
2
2
PTC4305
SE330U2D5VDM-1GP
2
1
PW R_VCORE3_LG1 PR4308 2 VCORE3_LG
0R0402-PAD
1
GAP-CLOSE-PWR-3-GP
5
4
3
S
S
G
1
84.06725.030
A
GAP-CLOSE-PWR-3-GP
PG4314
2
D
D
D
D
PU4308
PG4313
IRF6725MTRPBF-GP-U
2
7
6
2
1
L-D36UH-1-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CSP3
42
CSN3
Size
Date:
5
A
4
3
2
DC/DC CPU CORE2 _NCP6131
Rev
LLW-1 / LGG-1
SB
Document Number
Tuesday, November 09, 2010
Sheet
1
43
of
94
5
4
DCBATOUT
3
2
1
DCBATOUT_VCC_GFXCORE
1
PG4401
2
GAP-CLOSE-PW R-3-GP
PG4402
1
2
D
GAP-CLOSE-PW R-3-GP
PG4403
1
2
D
GAP-CLOSE-PW R-3-GP
PG4404
1
2
GAP-CLOSE-PW R-3-GP
PG4405
1
2
DCBATOUT_VCC_GFXCORE
1
84.06721.030
VCC_GFXCORE
SW A_HG
C
VREG_SW A
PL4401 1
5
4
3
TP4401
TPAD40-GP
1
PTC4403
ST330U2VDM-4-GP
2
2
PTC4402
ST330U2VDM-4-GP
1
1
S
S
G
1
PG4407
84.06725.030
GAP-CLOSE-PWR-3-GP
D
D
D
D
PU4403
IRF6725MTRPBF-GP-U
2
1
SW A_LG
2
1 PR4404 2
0R0402-PAD
2 L-D36UH-1-GP
7
6
2
1
VREG_SW A_LG
PC4403
SC4D7U25V6KX-3GP
PU4401
IRF6721SPBF-GP-U
PG4408
GAP-CLOSE-PWR-3-GP
C
3
4
1 PR4403 2
0R0402-PAD
S
G
VREG_SW A_HG
PC4402
SC4D7U25V6KX-3GP
2
2
D
D
D
D
PC4401
SC4D7U25V6KX-3GP
2
6
5
2
1
1
GAP-CLOSE-PW R-3-GP
1
GAP-CLOSE-PW R-3-GP
PG4406
1
2
CSNA
CSPA
42
42
B
B
PR4401
2D2R3-1-U-GP
1
2
PC4404
SCD22U25V3KX-GP
VREG_GFX_BOOT_1
1
2
5V_PWR
2VREG_GFX_EN
49D9R2F-GP
BST
PWM
EN
VCC
DRVH
SW
GND
DRVL
8
7
6
5
VREG_SW A_HG
VREG_SW A
VREG_SW A_LG
NCP5911MNTBG-GP
2
PC4405
SC1U10V2KX-1GP
9
PR4402 1
1
42 PWR_CPUCORE_PWMA
42,43 PWR_CPUCORE_DRON
1
2
3
4
FLAG
PU4405
VREG_GFX_BOOT
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5
4
3
2
DC/DC CPU CORE3 _NCP6131
Rev
LLW-1 / LGG-1
SB
Document Number
Tuesday, November 09, 2010
Sheet
1
44
of
94
5
DCBATOUT
1
4
3
2
1
PW R_1D05V_DCBATOUT
PG4501
2
GAP-CLOSE-PW R-3-GP
PG4502
1
2
D
GAP-CLOSE-PW R-3-GP
PG4503
1
2
D
GAP-CLOSE-PW R-3-GP
PG4504
1
2
GAP-CLOSE-PW R-3-GP
D
D
D
D
3D3V_S0
IND-D56UH-27-GP
2
PTC4503
SE330U2D5VDM-1GP
PC4509
SCD1U25V3KX-GP
1
VTT_SENSE_L
1
DY
1
PTC4502
SE330U2D5VDM-1GP
PC4502
SC470P50V2KX-3GP
2
2
PR4507
10KR2F-2-GP
PW R_1D05V_VFB
1
Id=26.5A
Qg=40.6~61nC,
Rdson=2.6~3.2mohm
PR4503
2D2R3-1-U-GP
2
PU4503
S
S
S
G
SIR460DP-T1-GE3-GP
4
3
2
1
2
PC4501
SC1U10V2KX-1GP
2
PR4506
10R2F-L-GP
DY
5
6
7
8
TPS51218DSCR-GP-U1
1
PR4504
470KR2F-GP
1
2
1
5V_S5
D
D
D
D
PR4501
64K9R2F-1-GP
C
1D05V_VTT
PL4501
1
2
PW R_1D05V_LGATE
2
2
2
PR4505
PC4503
2D2R3J-2-GP
SCD1U25V3KX-GP
PW R_1D05V_BOOT 1
2PW R_1D05V_BOOT_R 2
1
PW R_1D05V_UGATE
PW R_1D05V_PHASE
1
11
10
9
8
7
6
2
GND
VBST
DRVH
SW
V5IN
DRVL
Iomax=16A
OCP>24A
1
PGOOD
TRIP
EN
VFB
CCM
PC4508
SC4D7U25V5KX-GP
2
1
2
3
4
5
1
1
PC4505
SC1KP50V2KX-1GP
2
2
PW R_1D05V_TRIP
PW R_1D05V_EN
PW R_1D05V_VFB
PW R_1D05V_CCM
2 0R2J-2-GP
1
PR4502 1
1
19,36,37,46,47 RUNPW ROK
36 PW R_1D05V_EN
4
3
2
1
1
2
37,48 1.05VTT_PW RGD
PC4507
SC4D7U25V5KX-GP
Mag. 0.56uH 10*10*4
DCR=1.6~1.8mohm
Idc=25A, Isat=40A
PU4501
2
C
S
S
S
G
Id=14.3A
Qg=9.2~14nC
Rdson=11~14mohm
PR4512
10KR2J-3-GP
PC4506
SC4D7U25V5KX-GP
1
PU4502
SIR172DP-T1-GE3-GP
5
6
7
8
TPS51218 for 1D05V
PC4504
SC4D7U25V5KX-GP
1
1
PW R_1D05V_DCBATOUT
1
2
PR4508
20K5R2F-GP
VSS_SENSE_L
PR4509
10R2F-L-GP
B
2
B
VTT_SENSE_L
PR4510 1
DY
2 0R2J-2-GP
VCCIO_SENSE
8
PC4510
SC1000P50V3JN-GP-U
2
1
DY
VSS_SENSE_L
PR45111
DY
2 0R2J-2-GP
VSSIO_SENSE 8
Vout=0.704V*(R1+R2)/R2
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5
4
3
2
TPS51218_1D05V
Document Number
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
45
of
Rev
SB
94
5
DCBATOUT
1
4
3
2
PW R_1D5V_DCBATOUT
PG4601
2
1
PW R_1D5V_DCBATOUT
3D3V_S0
1
2
1
2
1
2
Iomax=16A
OCP>24A
1D5V_S3
2
S
S
S
G
PC4602
SC470P50V2KX-3GP
1
PTC4603
SE330U2D5VDM-1GP
2
1
1
PTC4602
SE330U2D5VDM-1GP
PW R_1D5V_VFB
DY
2
4
3
2
1
PR4603
2D2R3-1-U-GP
PC4610
SC1U16V3KX-5GP
2
PU4603
PR4608
11K5R2F-GP
2
PC4601
SC1U10V2KX-1GP
DY
2
IND-D56UH-27-GP
1
2
1
TPS51218DSCR-GP-U1
PR4605
470KR2F-GP
PC4608
SC4D7U25V5KX-GP
PL4601
5V_S5
PW R_1D5V_LGATE
PC4607
SC4D7U25V5KX-GP
D
1
D
D
D
D
PR4601
64K9R2F-1-GP
2
GND
VBST
DRVH
SW
V5IN
DRVL
PC4604
SCD1U25V3KX-GP
1
5
6
7
8
1
1
2
PC4603
SC1KP50V2KX-1GP
PGOOD
TRIP
EN
VFB
CCM
1
PW R_1D5V_TRIP
PW R_1D5V_EN
PW R_1D5V_VFB
PW R_1D5V_CCM
2 0R2J-2-GP
PR4606
2D2R3J-2-GP
PW R_1D5V_BOOT1
2PW R_1D5V_BOOT_R 2
PW R_1D5V_UGATE
PW R_1D5V_PHASE
1
RUNPW ROK
PR4602 1
11
10
9
8
7
6
2
19,36,37,45,47
19,27,82 PM_SLP_S4#
1
2
3
4
5
PC4606
SC4D7U25V5KX-GP
Mag. 0.56uH 10*10*4
DCR=1.6~1.8mohm
Idc=25A, Isat=40A
PU4601
2
2
PR4607
10KR2J-3-GP
4
3
2
1
1
Id=14.3A
Qg=9.2~14nC
Rdson=11~14mohm
DY
EC4601
SCD1U25V2KX-GP
S
S
S
G
GAP-CLOSE-PW R-3-GP
1
D
D
D
D
PU4602
GAP-CLOSE-PW R-3-GP
PG4604
1
2
D
PC4605
SC4D7U25V5KX-GP
SIR172DP-T1-GE3-GP
5
6
7
8
TPS51218 for 1D5V
SIR460DP-T1-GE3-GP
1
2
1
GAP-CLOSE-PW R-3-GP
PG4603
1
2
2
1
GAP-CLOSE-PW R-3-GP
PG4602
1
2
PR4609
10KR2F-2-GP
C
2
C
Id=26.5A
Qg=40.6~61nC,
Rdson=2.6~3.2mohm
Vout=0.704V*(R1+R2)/R2
B
2
RT9026 for 0D75V_S0
1
PC4615
SCD1U10V2KX-5GP
PC4614
SC10U6D3V3MX-GP
B
2
1
1D5V_S3
Iomax=1.2A
OCP>1.8A
PC4612
SC1U10V2KX-1GP
0D75V_S0
0D75V_PW R
2
1
5V_S5
PG4621
1
2
DDR_VREF_S3
1D5V_S3
PU4604
1
PC4616
SC10U6D3V3MX-GP
GAP-CLOSE-PW R-3-GP
PC4617
SC10U6D3V3MX-GP
A
<Core Design>
2
RT9026PFP-GP
GAP-CLOSE-PW R-3-GP
PG4622
1
2
1
2
3
4
5
1
PC4613
SC1U10V2KX-1GP
VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
GND
PC4611
SCD1U10V2KX-5GP
10
9
8
7
6
2
2
A
PW R_0D75V_S5
PW R_0D75V_S3
DDR_VREF_S3
11
2 0R2J-2-GP
1
0D75V_EN
2 0R2J-2-GP
PR4611 1
1
37
PR4610 1
2
19,27,82 PM_SLP_S4#
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51128_1D5V & RT9026_0D75V
Size
Date:
5
4
3
2
Document Number
Tuesday, November 09, 2010
Rev
LLW-1
/ 46LGG-1
Sheet
of
1
SB
94
5
4
3
2
1
D
D
2
3D3V_S5
DY
PR4701
10KR2F-2-GP
RT8015B for 1D8V_S0
1
19,36,37,45,46
RUNPW ROK
PR4708 1
2 0R2J-2-GP
PW R_1D8V_GD
Mag.7*7*3
DCR=28~30mohm, Irating=6A
Isat=13.5A
3D3V_S5
Iomax=3A
PU4701
RT8015BGQW -GP
1D8V_S0
C
11
PC4703
SC1500P50V2KX-2GP
2
PW R_1D8V_FB
PR4703
820KR2F-GP
PC4705
C
1
GAP-CLOSE-PW R-3-GP
PC4708
1
PG4702
2
2
PC4707
GAP-CLOSE-PW R-3-GP
1
PG4703
2
GAP-CLOSE-PW R-3-GP
PR4706
16KR2F-GP
2
1
2PW R_1D8V_COMP_R
1
PW R_1D8V_RT
1
1
COMP
PC4709
2
SHDN/RT
PW R_1D8V_COMP 10
PR4707
20KR2F-L-GP
1
2
2
GND
1
3
FB
2
LX#3
9
1D8V_PW R
1 IND-3D3UH-57GP
1
PGOOD
PL4701 2
1
LX#4
8
PW R_1D8V_LX
PG4701
1
2
2
VDD
4
SCD1U25V2KX-GP
2
1
7
GND
1
2
2
PW R_1D8V_FB
5
SC22U6D3V5MX-2GP
PC4702
SC10U6D3V3MX-GP
PGND
SC100P50V2JN-3GP
PC4701
SC10U6D3V3MX-GP
PVDD
SC22U6D3V5MX-2GP
1
6
PR4702
14KR2F-GP
PC4704 1
2 SC47P50V2JN-3GP
Vo=0.8*(1+(R1/R2))
S
19,27,36,37,82
PM_SLP_S3#
PR4709
0R2J-2-GP
1
2
D
G
B
B
PQ4701
AO7401-GP
84.07401.031
PW R_1D8V_RUN_EN
PC4710
SCD1U10V2KX-5GP
2
1
DY
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5
4
3
2
PWM_1D8V_RT8015B
Document Number
Rev
LLW-1 / LGG-1
Sheet
Tuesday, November 09, 2010
1
47
SB
of
94
5
DCBATOUT
1
4
3
2
1
PW R_VCCSA_DCBATOUT
PG4801
2
GAP-CLOSE-PW R-3-GP
PG4802
1
2
GAP-CLOSE-PW R-3-GP
PG4803
1
2
RT8208A for VCCSA
GAP-CLOSE-PW R-3-GP
D
4
3
2
1
15
EM/DEM
17
GND
PW R_VCCSA_BOOT
UGATE
PHASE
LGATE
12
11
8
PW R_VCCSA_HG
PW R_VCCSA_PH
PW R_VCCSA_LG
G0
FB
G1
D1
D0
7
3
14
5
6
PW R_VCCSA_G0
PW R_VCCSA_FB
PW R_VCCSA_G1
PW R_VCCSA_D1
PW R_VCCSA_D0
VOUT
1
PR4803
2D2R3J-2-GP
1
2 PW R_VCCSA_BOOT_R 1
1
2
1
2
SC4D7U25V6KX-3GP
2
SC4D7U25V6KX-3GP
SC4D7U25V6KX-3GP
VCCSA_PW R
VCCSA_PW R
2
PL4801
1
9
H_FC_C22
9
DY
PR4816
2D2R3-1-U-GP
D
PTC4801
SE390U2D5VM-7GP
PU4803
SIS412DN-T1-GE3-GP
VCCSA_PW R
PC4808
SCD1U25V3KX-GP
GAP-CLOSE-PW R-3-GP
PG4807
1
2
PC4811
SC470P50V2KX-3GP
S
S
S
G
GAP-CLOSE-PW R-3-GP
PG4808
1
2
4
3
2
1
2
Matsuki cap 390uF
2.5V, ESR=10mohm
S
VCCSA_PW R
GAP-CLOSE-PW R-3-GP
PG4809
1
2
1
PR4806
0R2J-2-GP
2
PC4809
SC1U6D3V2KX-GP
PW R_VCCSA_FB_R
1
1
2
1
2
PC4812
SCD1U25V2KX-GP
PR4813
143KR2F-L-1-GP
PWR_VCCSA_D1
2
PR4812
76K8R2F-GP
2
0.8V
1
1
H
PR4811
49K9R2F-L-GP
2
0.9V
B
DY
DY
PWR_VCCSA_D0
L
GAP-CLOSE-PW R-3-GP
VCCSA_SENSE 9
PC4810
SC18P50V2JN-1-GP
PW R_VCCSA_FB
VCCSA_PWR
2 0R2J-2-GP
2
PR4808
10KR2F-2-GP
Vout=0.75*(1+R1/R2)
PR4810 1
DY
1
B
VCCSA_SEL
GAP-CLOSE-PW R-3-GP
PG4810
1
2
PR4809
0R2J-2-GP
2
1
DY
Id=12.5A
Qg=15.4~23nC
Rdson=14.5~17.5mohm
DY
2
37,45 1.05VTT_PW RGD
1
C
GAP-CLOSE-PW R-3-GP
PG4806
1
2
DY
RT8208BGQW -GP
G
0D85V_S0
PG4804
2
GAP-CLOSE-PW R-3-GP
PG4805
1
2
2
VCCSA_SEL
1
1 PR4804 2
0R2J-2-GP
1
2
PR4807
0R2J-2-GP
1
1
2
IND-1D5UH-53-GP
2
1
2
PR4805
18K7R2F-GP
PGOOD
CS
13
D
D
D
D
PW R_VCCSA_EN
4
10
VDD
BOOT
1
PW R_VCCSA_GD
PW R_VCCSA_CS
2
PR4815
0R2J-2-GP
2
TON
VDDP
Iomax=6A
OCP>9A
VCCSA=0.8V/0.9V
2
1
PWR_VCCSA_VDD
16
9
PC4806
Mag. 1.5uH 7*7*3
DCR=14~15mohm
Idc=9A, Isat=18A
1
2
2
1
2
2
19,42 D85V_PW RGD
S
PC4807
SCD1U25V3KX-GP
PU4801
1
C
G
PW R_VCCSA_TON
PC4805
PU4802
SIS412DN-T1-GE3-GP
S
S
S
G
PR4814
100KR2J-1-GP
D
PC4804
D
D
D
D
3D3V_S5
Freq=300KHz
2
249KR2F-GP
SC1U10V2KX-1GP
PC4802
SC1U10V2KX-1GP
S-HR_20100614 V1.1
for CRB board
PR4802
1
5
6
7
8
PC4801
PR4801
2D2R3J-2-GP
5
6
7
8
1
1
2
PC4803
SCD1U25V3KX-GP
5V_S5
1
PW R_VCCSA_DCBATOUT
1
D
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Date:
5
4
3
2
RT8208B_VCCSA
Document Number
Rev
LLW-1 / LGG-1
Sheet
Tuesday, November 09, 2010
1
48
SB
of
94
LCD / Inverter Connector
DCBATOUT
DCBATOUT_LCD
DCBATOUT_LCD
3D3V_S0
F4901
LVDS_DDC_DATA
LVDS_DDC_CLK
C4902
C4903
SCD01U25V2KX-3GP
1
2
2
69.43001.331
2nd = 69.43001.371
1
C4901
SCD01U25V2KX-3GP
SC1U25V3KX-1-GP
1
2
2
1
RN4901
SRN2K2J-1-GP
3
4
1.2A
2
FUSE-3A24V-1-GP
SCD1U25V3KX-GP
1
2
1
C4904
3D3V_S5
R4902 1
2
LCD_PRESENCE#
100KR2J-1-GP
LCD1
41
1
27 LID_CLOSE#
3D3V_AUX_S5
3D3V_S5
R4901
2
1 330R2F-GP
PANEL_LED_P
PANEL_LED_N
17 LVDSA_CLK
17 LVDSA_CLK#
17 LVDSA_DATA2
17 LVDSA_DATA2#
17 LVDSA_DATA1
17 LVDSA_DATA1#
17 LVDSA_DATA0
17 LVDSA_DATA0#
17 LVDS_DDC_DATA
17 LVDS_DDC_CLK
3D3V_S0
F4902
1
FUSE-D5A32V-14-GP
2
LCDVDD
LVDS_DDC_DATA
LVDS_DDC_CLK
3D3V_DDC_S0
LCDVDD
3D3V_S0
U4901
Layout 40 mil
17 LVDS_VDD_EN
1
2
3
EN
GND
OUT
IN#5
5
IN#4
4
1
MIC_DET#
R4914
100KR2J-1-GP
DY
C4909
SCD1U16V2KX-3GP
G5285T11U-GP
C4908
SC4D7U6D3V3KX-GP
74.05285.07F
C4907
SC4D7U6D3V3KX-GP
2
1
1
TP4901
29 AUD_DMIC_DATA
29 AUD_DMIC_CLK
2nd = 74.09724.09F
2
18 USB_PN12
18 USB_PP12
1
FUSE-D75A32V-3-GP
LCD_PRESENCE#
3D3V_CAM_S0
2
2
1
F4903
1
2
27 BLON_OUT
17 L_BKLT_CTRL
18 LCD_PRESENCE#
3D3V_S0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
JAE-CON40-4-GP
20.K0568.040
Q4901
27
PANEL_LED
1
3
R1
R2
PANEL_LED_N
2
Near LCD1
LTC043ZUB-FS8-GP
LID_CLOSE#
AUD_DMIC_CLK
AUD_DMIC_DATA
3D3V_DDC_S0
1
1
1
1
AFTP4901
AFTP4902
AFTP4903
AFTP4904
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LCD CONNECTOR
Size
A3
Date:
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
49
of
94
5
4
3
2
CRT CONNECTOR
1
CRT DDCDATA & DDCCLK level shift
Pull High 5V Design on CRT Board
3D3V_S0
5V_CRT_S0
3D3V_S0_DDC 10KR2J-3-GP
1
5V_CRT_S0
2 R5003
5V_S0
12
15
CRT_R
CRT_G
CRT_B
1
2
3
CRT_VSYNC_CON
CRT_HSYNC_CON
GND
GND
GND
GND
GND
GND
GND
CRT_RED
CRT_GREEN
CRT_BLUE
VSYNC
HSYNC
Near CRT1
3D3V_S0
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_R
CRT_G
CRT_B
5V_CRT_S0
5
6
7
8
10
16
17
AFTP5001
AFTP5002
AFTP5003
AFTP5004
AFTP5006
AFTP5007
AFTP5005
AFTP5008
1
1
1
1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
RN5002
SRN2K2J-1-GP
17 CRT_DDC_DATA
20.20918.015
R5006 1
17 CRT_DDC_CLK
A
5V_CRT_DDC
RN5003
SRN10KJ-5-GP
Q5001
2 0R2J-2-GP
4
3
5
2
6
R5007 1
D
1
2
D-SUB-15-97-GP
500mA
D5001
CH551H-30GP-GP
F5001
3D3V_S0_DDC
4
3
14
13
DDCDATA_ID1
DDCCLK_ID3
4
11
NP1
NP2
K
CRT_DDCDATA_CON
CRT_DDCCLK_CON
NC#4
NC#11
NP1
NP2
4
3
C5012
VCC_CRT
1
2
SCD01U16V2KX-3GP
2
1
9
D
POLYSW-1D1A6V-GP
2
1
CRT1
CRT_DDCDATA_CON
1
2N7002KDW -GP
2 0R2J-2-GP
84.2N702.A3F
CRT_DDCCLK_CON
2nd = 84.DM601.03F
2
1
5V_S0
CRT Hsync & Vsync level shift
2
2
CRT_VSYNC
0R2J-2-GP
17
C5008
SC100P50V2JN-3GP
C5009
SC18P50V2JN-1-GP
DY
1
10R2J-2-GP
CRT_HSYNC_CON
DY
C5010
SC18P50V2JN-1-GP
C
DY
C5011
SC100P50V2JN-3GP
2
R5002
CRT_HSYNC1_2 1
CRT_VSYNC_R 1
R5005
DY
1
8
7
6
5
2
VCC
2OE#
1Y
2A
1
1OE#
1A
2Y
GND
1
R5004 1
CRT_VSYNC_CON 1
R5001
CRT_HSYNC
U5001
1
2
3
4
2
17
0R2J-2-GP
2 CRT_HSYNC_R
2 CRT_VSYNC1_2
10R2J-2-GP
CRT_DDCDATA_CON
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON
2
C
C5007
SCD1U10V2KX-5GP
74AHCT2G125DP-GP
73.2G125.00B
5V_CRT_S0
5V_CRT_S0
D5002
D5006
2
2
3CRT_HSYNC_CON
B
3
1
CH221GP-GP-U
B
CH221GP-GP-U
D5003
D5007
2
2
3CRT_VSYNC_CON
CRT RGB
17
3CRT_GREEN
1
L5001 1
CRT_RED
2 FCM1608CF-220T05-GP
1
CRT_R
CH221GP-GP-U
CH221GP-GP-U
D5004
17
CRT_GREEN
L5002 1
2 FCM1608CF-220T05-GP
CRT_G
2
17
CRT_BLUE
L5003 1
2 FCM1608CF-220T05-GP
CRT_B
1
D5008
2
C5003
C5004
C5005
A
SC10P50V2JN-4GP
2
1
DY
SC10P50V2JN-4GP
2
1
C5002
SC10P50V2JN-4GP
2
1
DY
SC8P250V2CC-GP
2
1
C5001
SC8P250V2CC-GP
2
1
R5010
SC8P250V2CC-GP
2
1
R5009
150R2F-1-GP
2
1
R5008
150R2F-1-GP
2
1
150R2F-1-GP
2
1
3CRT_DDCDATA_CON
DY
CRT_RED
1
3CRT_BLUE
1
CH221GP-GP-U
CH221GP-GP-U
D5005
C5006
2
3CRT_DDCCLK_CON
1
CH221GP-GP-U
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CRT Connector
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
50
of
94
A
B
D
3D3V_S0
1
DY
R5106
1MR2J-1-GP
R5102
20KR2J-L2-GP
Q5102
2
G
HDMI_OE#
HDMI_DETECT_R
1
2N7002K-2-GP
4
1
2
DY
0R2J-2-GP
D
2
R5101
D
S
17 PCH_HDMI_DET
E
HDMI Connector
1
3D3V_S0
C
Q5101
2N7002K-2-GP
R5105
100KR2J-1-GP
HDMI1
20
84.2N702.J31
2nd = 84.2N702.031
DY
D5103
HDMI_TX2+
HDMI_TX2-
S
G
2
84.2N702.J31
2nd = 84.2N702.031
HDMI_A_HPD_CN
1
2
G1
3
4
HDMI_TX1+
HDMI_TX1-
L1#1L1#8
L2#2L2#7
GNDGND
L3#3L3#6
L4#4L4#5
HDMI_TX2+
HDMI_TX2+
HDMI_TX2-
8
7
G2
6
5
HDMI_TX2HDMI_TX1+
HDMI_TX1+
HDMI_TX1-
HDMI_TX1HDMI_TX0+
5V_HDMI_S0
RCLAMP0524P-GP
HDMI_TX0HDMI_TXC+
TP5101
TPAD14-GP
3D3V_S0
C5102
DY
DY
C5121
R5107
R5108
2
11
15
21
26
33
40
46
DY
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U5101
38
39
17 HDMI_DATA2_R
17 HDMI_DATA2_R#
41
42
17 HDMI_DATA1_R
17 HDMI_DATA1_R#
47
48
17 HDMI_CLK_R
17 HDMI_CLK_R#
3D3V_S0
R5112
R5113
44
45
17 HDMI_DATA0_R
17 HDMI_DATA0_R#
Recommended Equalization: [PC1,PC0]=01, 4dB
2
2
DY
PC0
PC1
1 4K7R2J-2-GP
1 4K7R2J-2-GP
3
4
DY
1
3D3V_S0
REXT_HDMI
DY
2
HDMI_OE#
DDC_EN_PS8101
1
R5109
4K7R2J-2-GP
TP5102
TPAD14-GP
HDMI_TXC+
HDMI_TXC-
21
23
RCLAMP0524P-GP
DY
22.10296.511
5V_S0
IN_D1IN_D1+
OUT_D1OUT_D1+
IN_D2IN_D2+
OUT_D2OUT_D2+
IN_D3IN_D3+
OUT_D3OUT_D3+
IN_D4IN_D4+
OUT_D4OUT_D4+
PC0
PC1
SDA
SCL
HPD
REXT
RT_EN#
OE#
DDC_EN
HPD_SINK
SDA_SINK
SCL_SINK
23
22
HDMI_TX2+
HDMI_TX2-
20
19
HDMI_TX1+
HDMI_TX1-
17
16
HDMI_TX0+
HDMI_TX0-
DY
14
13
HDMI_TXC+
HDMI_TXC-
BAV99PT-GP-U
2
3
HDMI_A_HPD_CN
3
1
D5101
83.00099.K11
8
9
7
HDMI_DETECT_R
30
29
28
HDMI_A_HPD_CN
TDMS_A_DAT
TDMS_A_CLK
PCH_HDMI_DATA 17
PCH_HDMI_CLK 17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
R5111
5K1R2F-2-GP
2
DY
6
10
25
32
1 HDMI_A_HPD_CN
DY
PS8101-GP
71.P8101.003
5V_S0
2ND = 71.03360.A0K
D5102
TDMS_A_DAT
TDMS_A_CLK
1
R5110
499R2F-2-GP
1
5
12
18
24
27
31
36
37
43
49
3
HDMI_TXC+
HDMI_TXC-
2 4K7R2J-2-GP
2 4K7R2J-2-GP
1
1
HDMI_TX0+
HDMI_TX0-
8
7
G2
6
5
SKT-HDMI23-26-GP-U
8101_NC35
8101_NC34
DY
L1#1L1#8
L2#2L2#7
GNDGND
L3#3L3#6
L4#4L4#5
4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
35
34
C5119
NC#35
NC#34
DY
SCD1U10V2KX-5GP
2
1
C5101
SCD1U10V2KX-5GP
2
1
SCD1U10V2KX-5GP
2
1
SCD1U10V2KX-5GP
2
1
DY
1
2
G1
3
4
HDMI_TXCHDMI_A_CEC
TDMS_A_CLK
TDMS_A_DAT
DY
D5104
HDMI_TX0+
HDMI_TX0-
3D3V_S0
1
22
1
2K2R2J-2-GP
2K2R2J-2-GP
2
2
1 R5114
1 R5115
5V_HDMI_S0
K
A
CH551H-30GP-GP
2
2
HDMI Passive Level Shifter
HDMI DDC Passive Level Shifter
Close to HDMI Connector
HDMI_DATA2_R
HDMI_DATA2_R#
SRN0J-6-GP 2
1
3
4
RN5103
HDMI_TX2+
HDMI_TX2-
HDMI_DATA1_R
HDMI_DATA1_R#
SRN0J-6-GP 2
1
3
4
RN5104
HDMI_TX1+
HDMI_TX1-
HDMI_DATA0_R
HDMI_DATA0_R#
SRN0J-6-GP 2
1
3
4
RN5108
HDMI_TX0+
HDMI_TX0-
HDMI_CLK_R
HDMI_CLK_R#
SRN0J-6-GP 2
1
3
4
RN5107
HDMI_TXC+
HDMI_TXC-
3D3V_S0
RN5102
SRN680J-1-GP
1
8
2
7
3
6
4
5
1
6
2
5
3
4
2N7002KDW-GP
TDMS_A_DAT
TDMS_A_CLK
84.2N702.A3F
PCH_HDMI_CLK
2nd = 84.DM601.03F
D
RN5101
SRN680J-1-GP
1
8
2
7
3
6
4
5
Q5104
PCH_HDMI_DATA
Q5103
2N7002K-2-GP
1
1
S
<Core Design>
Wistron Corporation
1
3D3V_S0
G
84.2N702.J31
2nd = 84.2N702.031
DY
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R5104
100KR2J-1-GP
Title
2
HDMI
Size
A2
Date:
A
B
C
D
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
E
Sheet
51
of
94
A
B
C
D
E
4
4
3
3
BLANK
2
2
<Core Design>
Wistron Corporation
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DISPLAY PORT CONNECTOR
Size
A4
Document Number
Date: Tuesday, November 09, 2010
A
B
C
Rev
SB
LLW-1 / LGG-1
D
Sheet
52
of
E
94
1
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
53
of
94
A
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
54
of
94
A
A
B
C
D
E
4
4
3
3
2
2
<Core Design>
Wistron Corporation
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
FAN CONTROL
Size
A4
Document Number
Date: Tuesday, November 09, 2010
A
B
C
Rev
SB
LLW-1 / LGG-1
D
Sheet
55
of
E
94
1
A
B
C
D
E
HDD Connector
3D3V_S0
HDD1
4
27
HDD_DTCT#
23
24
GND
GND
NP1
NP2
NP1
NP2
S1
S4
S7
P4
P5
P6
P10
P12
GND
GND
GND
GND
GND
GND
GND
GND
P11
DAS/DSS
V33
V33
V33
P1
P2
P3
3D3V_S0_HDD
V5
V5
V5
P7
P8
P9
5V_S0_HDD
V12
V12
V12
P13
P14
P15
A+
A-
S2
S3
SATA_TXP0_C
SATA_TXN0_C
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
S6
S5
SATA_RXP0_C
SATA_RXN0_C
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
B+
B-
0R3J-0-U-GP 1
0R3J-0-U-GP 1
2 R5610
2 R5611
5V_S0
0R3J-0-U-GP 1
0R3J-0-U-GP 1
4
2 R5608
2 R5609
PW RNC PN5601
PW RNC PN5602
PW RNC PN5603
2
2
1 C5610
1 C5609
1
1
2 C5603
2 C5602
SATA_TXP0
SATA_TXN0
21
21
SATA_RXP0
SATA_RXN0
21
21
SKT-SATA7P-15P-65-GP
DY
C5614
C5613
DY
SC10U10V5ZY-1GP
2
1
C5615
SCD01U25V2KX-3GP
1
2
3
SC10U6D3V3MX-GP
1
2
SCD01U25V2KX-3GP
1
2
22.10300.B31
C5606
3
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil
ODD Connector
Mars:
Exchange ODD and ESATA differential pair each other.
SATA Zero Power ODD
5V_S0
ODD_PW R_5V
ODD1
SATA_TXN4_C
SATA_TXP4_C
2
R5604
10KR2J-3-GP
S1
S4
S7
P5
P6
14
15
GND
GND
GND
GND
GND
GND
GND
BB+
S5
S6
NP1
NP2
SATA_RXN4_C
SATA_RXP4_C
C5611 1
C5612 1
C5607 1
C5608 1
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
2SCD01U16V2KX-3GP
2SCD01U16V2KX-3GP
SATA_TXN4
SATA_TXP4
SATA_RXN4
SATA_RXP4
21
21
100 mil
-1 0114
S
Q5603
SUPPORT ZERO SATA ODD
21
21
C5601
SCD1U10V2KX-5GP
C5604
SCD1U16V2KX-3GP
R5601
100KR2J-1-GP
D
AO3419L-GP
1
S3
S2
5V_S0
C5605
SC1U10V2KX-1GP
2
AA+
2
2 0R3J-0-U-GP
SATA_ODD_PW RGT_T
20100709 V1.4
NP1
NP2
3D3V_S0
D
DY
2 R5603
DY
G
ODD_PW R_5V 0R5J-5-GP 1
1
P2
P3
2
+5V
+5V
1
MD
DP
2
SATA_ODD_DA#_C P4
0R2J-2-GP
P1
1
DY 2
R5602 1
2
R5605 1
1
18 SATA_ODD_DA#
22 SATA_ODD_PRSNT#
DY
1
2
SKT-SATA7P-6P-56-GP
22.10300.B51
Q5602
2N7002K-2-GP
R5606
10KR2J-3-GP
22 SATA_ODD_PW RGT
<Core Design>
Q5601
3D3V_S0
3
2
1
2
1
4
3
1
2N7002KDW -GP
RN5601
SATA_ODD_PW RGT
SATA_ODD_DA#
G
SATA_ODD_DA#_C
4
5
6
1
ODD_PWRGT#
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON
S
2
84.2N702.J31
2nd = 84.2N702.031
84.2N702.A3F
2nd = 84.DM601.03F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-5-GP
Title
SATA_ODD_PW RGT
SATA_ODD_DA#
0707 Modify:
Change Q5601 to DUAL 2N7002 for isolate MD/DA signal between PCH and ODD.
SATA HDD
Size
A3
Date:
A
B
C
D
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
E
56
of
94
A
B
C
D
E
ESATA Connector
USB_PWR1
4
4
DY
RCLAMP0524P-GP
3
ESATA1
U1
VBUS
21
21
SATA_TXP5
SATA_TXN5
SCD01U16V2KX-3GP 2
SCD01U16V2KX-3GP 2
1
1
C5707
C5708
S2
S3
A+
A-
21
21
SATA_RXP5
SATA_RXN5
SCD01U16V2KX-3GP 2
SCD01U16V2KX-3GP 2
1
1
C5705
C5706
S6
S5
B+
B-
U3
U2
D+
D-
18
18
USB_PP8
USB_PN8
USB_PP8
USB_PN8
NP1
NP2
GND
GND
GND
GND
CHASSIS#12
CHASSIS#13
CHASSIS#14
CHASSIS#15
NP1
NP2
S1
S4
S7
U4
12
13
14
15
SKT-ESATA-USB-S7-U4-5-GP-U
Near ESATA1
1
5V_S5
USB_PWR1
AFTP5701 AFTE14P-GP
1
USB_PWR1
GND
IN#2
IN
EN
OUT#8
OUT#7
OUT
OC#
9
D5702
USB_PP8
WIDE PATTERN (MIN 500MA)
PLACE NEAR USB CONNECTOR
3
Table 57.1- USB2.0 PWR SW multi-source
Supplier
Description
Lenovo P/N
Wistron P/N
TI
TPS2065DGN4
54Y9024BA
74.02065.079
ROHM
BD8012FVJ
54Y9024AA
74.08012.07G
Table 57.2- 150U 6.3V POSCAP multi-source
1
2
3
4
27,61 USB_PWR_EN
1
AFTP5702 AFTE14P-GP
AFTP5703 AFTE14P-GP
AFTP5704 AFTE14P-GP
TC5701
U5701
GND
2
1
1
1
C5702
C5704
2
SCD1U10V2KX-5GP
USB_PP8
USB_PN8
C5703
ST150U6D3VBM-1-GP
2
1
1
2
G1
3
4
SCD1U10V2KX-5GP
1
2
L1#8L1#1
L2#7L2#2
GNDGND
L3#6L3#3
L4#5L4#4
SCD1U10V2KX-5GP
1
2
8
7
G2
6
5
D5701
1
2
3
8
7
6
5
Lenovo P/N
Wistron P/N
USB_OC#8_9 18,61
NEC-TOKIN TEPSLB20J157M
N/A
77.C1571.09L
SANYO
6TPE150MAZB
N/A
77.21571.111
HPC
TNCB0J157MTRZTF
N/A
80.15715.12L
<Core Design>
5V_S5
ESD I/O4
VP
ESD I/O3
Description
TPS2065DGN-GP
DY
ESD I/O1
GND
ESD I/O2
2
Supplier
Wistron Corporation
USB_PN8
6
5
4
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ESATA CONNECTOR
IP4223CZ6-GP
Size
A4
Document Number
Date: Tuesday, November 09, 2010
A
B
C
Rev
SB
LLW-1 / LGG-1
D
Sheet
57
of
E
94
1
5
4
3
NEAR HEADPHONE CONN
2
1
JACK SENSE
29 AUD_PORTA_L
R5804 1
2 5D1R2J-1-GP
HP_L_JACK_R
29 AUD_PORTA_R
R5805 1
2 5D1R2J-1-GP
HP_R_JACK_R
2 10KR2F-2-GP
AUD_SENSE_A
29
D
R5808 1
Q5801
2N7002K-2-GP
D
R5802 1
2 39K2R2F-L-GP
AUD_SENSE_A
D
29
S
G
84.2N702.J31
2nd = 84.2N702.031
HP_JACK_SYS
2
D
D
AUD_5V
AU_GND
HP_JACK_SYS
1
1
AFTE14P-GP
AFTE14P-GP
TP5805
TP5806
5
HP_JACK_SYS
1
AFTE14P-GP
TP5807
R5803 1
EC5808 1
2 SCD01U25V2KX-3GP
2 10KR2J-3-GP
AU_GND
1
HP_L_JACK_R
HP_R_JACK_R
AU_GND
C5813
SC1U10V2KX-1GP
AU_GND
2
AGND
S
G
HP_JACK_SYS
MIC_JACK_3
HP_L_JACK
HP_R_JACK
S
SC1U10V2KX-1GP
2
AU_GND
G
C5812
1
2
3
DGND
DGND
NC#6
6
2
8
9
4
PHONE-JK367-GP-U
22.10088.H81
confirm HPMIC1 is NO type's
connector
D5801
AU_GND
R5814
100KR2J-1-GP
D5802
1
1
VCC3MA
NP1
NP2
RSB5D6SGTE61-GP
2
1
D5803
MIC_JACK3
RSB5D6SGTE61-GP
2
1
7
NP1
NP2
1
MIC_JACK_3
RSB5D6SGTE61-GP
2
1
1
AFTE14P-GP
84.2N702.J31
2nd = 84.2N702.031
84.2N702.J31
2nd = 84.2N702.031
1
TP5809
AFTE14P-GP
HPMIC1
TP5808
Q5803
2N7002K-2-GP
Q5804
2N7002K-2-GP
R5810
1KR2J-1-GP
AU_GND
C
C
R5817
0R2J-2-GP
29 AUD_PORTC_L_C
1
1
R5815
0R2J-2-GP
1
R5816
0R2J-2-GP
AUD_LDO_OUT_3D3V
R5811
1KR2J-1-GP
1
2
2
2
2
R5801
2K2R2J-2-GP
2
1
1
29 AUD_PORTC_R_C
DY
EC5809 1
2 SCD01U25V2KX-3GP
EC5806 1
2 SCD01U25V2KX-3GP
EC5807 1
2 SCD01U25V2KX-3GP
AU_GND
C5808
SC10U6D3V3MX-GP
2
MIC_JACK_3
AU_GND
AU_GND
AU_GND
INTERNAL STEREO SPEAKERS
Port G
29 AUD_SPK_L+_L
1
AFTE14P-GP
TP5801
29 AUD_SPK_L-_L
1
AFTE14P-GP
TP5802
1
1
2
EC5802
SC47P50V2JN-3GP
2
Only needed if speaker
connector is physically far from
audio codec. When in doubt, it's
always a good idea to have
population option.
SPK1
5
EC5801
SC47P50V2JN-3GP
1
B
2
3
4
B
6
Place these EMI components
close to speaker connector.
ACES-CON4-29-GP
AFTE14P-GP
TP5803
1
AFTE14P-GP
TP5804
EC5804
SC47P50V2JN-3GP
2
2
EC5803
SC47P50V2JN-3GP
1
1
29 AUD_SPK_R+_L
1
29 AUD_SPK_R-_L
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Audio Jack
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
58
of
94
5
4
3
2
1
D
D
C
C
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A3
Date:
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
59
of
94
5
4
3
2
1
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH
3D3V_SPI
DY
RN6001
SRN4K7J-10-GP
D
C6002
SCD1U10V2KX-5GP
2
C6001
SC10U6D3V5KX-1GP
2
8
7
6
5
1
D
1
3D3V_SPI
1
2
3
4
3D3V_SPI
SPI_HOLD_0#
3D3V_SPI
VDD
HOLD#
SCK
SI
8
7
6
5
SPI_CLK_R
SPI_SI_R
DY
EC6003
SC4D7P50V2CN-1GP
2
SST25VF032B-80-4I-S2AF-GP
1
2
EC6002
SC4D7P50V2CN-1GP
CE#
SO
WP#
VSS
2
R6010
2
DY
1 0R2J-2-GP
1 0R2J-2-GP
21,27
21,27
DY
EC6001
SC4D7P50V2CN-1GP
2
1
2
3
4
SPI_SO
SPI_W P#
DY
1
2 33R2J-2-GP
1
R6001 1
R6011
3D3V_S5
the same page 23 VCCSPI power
U6001
21,27 SPI_CS0#_R
21,27 SPI_SO_R
3D3V_S0
20100622 V1.2
C
C
Table 60.1- SPI Serial Flash Memory multi-source
Supplier
B
Description
Lenovo P/N
Wistron P/N
SST
SST25VF032B-80-4I-S2A
N/A
72.25032.D01
MXIC
MX25L3206EM2I-12G
N/A
72.25320.C01
WINBOND
W25Q32BVSSIG
N/A
72.25Q32.A01
NUMONYX
M25PX32-VMW6F
N/A
72.25P32.C01
B
Table 60.2 - Schottky Barrier Diode multi-source
3D3V_AUX_S5
SSID = RBATT
Q6001
RTC_AUX_S5
2
+RTC_VCC
RTC1
3
Supplier
Description
Lenovo P/N
Wistron P/N
CHENMKO
CH715FGP
N/A
83.R0304.D81
CHENMKO
BAS40CWGP
N/A
83.00040.R81
PANJIT
BAS40CW
N/A
83.00040.E81
2
1
1
3
CH715FGP-GP-U
RTC_PW R
R6002
2 1KR2J-1-GP
1
1
C6003
SC1U6D3V2KX-GP
A
1
2
TP6001
4
ACES-CON2-31-GP
<Core Design>
Width=20mils
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
TPAD14-GP
TP6002
1
+RTC_VCC
Title
Flash/RTC
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
60
of
94
5
4
3
2
1
USB Connector
WIDE PATTERN (MIN 500MA)
PLACE NEAR USB CONNECTOR
R6101
D
Left Rear USB Connector
2 0R3J-0-U-GP
1
USB_PW R2
5V_S5
D
R6102
C6101
C6102
2 0R3J-0-U-GP
1
SKT-USB6-21-GP
TC6101
USB_PW R3
C6105
U6101
1
2
3
4
22.10321.Z61
27,57 USB_PW R_EN
GND
IN
EN1
EN2
GND
3
2
TR6101
ACM2012-900-1GP
2
3
4
5
USB_PW R2
9
DY
SCD1U10V2KX-5GP
2
1
USBPN9_TVS
USBPP9_TVS
ST150U6D3VBM-1-GP
2
1
USB_PP9
SC470P50V2KX-3GP
2
1
USB_PN9
18
SCD1U10V2KX-5GP
2
1
18
6
1
4
1
USB1
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USB_OC#8_9 18,57
USB_OC#0_1 18
TPS2066DGN-GP-U
WIDE PATTERN (MIN 500MA)
PLACE NEAR USB CONNECTOR
R6103
USB_PW R3
C
U6102
Left Front USB Connector
2 0R3J-0-U-GP
1
USBPP9_TVS
R6104
1
2 0R3J-0-U-GP
C6103
C6104
ST150U6D3VBM-1-GP
2
1
TR6102
ACM2012-900-1GP
SC470P50V2KX-3GP
2
1
USB_PP1
SCD1U10V2KX-5GP
2
1
18
ESD I/O1
GND
ESD I/O2
ESD I/O4
VP
ESD I/O3
6
5
4
USBPN9_TVS
C
USBPN1_TVS
IP4223CZ6-GP
USBPN1_TVS
USBPP1_TVS
DY
4
USB_PN1
1
18
1
2
3
USBPP1_TVS
6
1
3
2
USB2
5V_S5
DY
2
3
4
5
SKT-USB6-21-GP
TC6102
22.10321.Z61
Near USB2
1
USB_PW R3
USBPN1_TVS
USBPP1_TVS
AFTP6101 AFTE14P-GP
1
1
1
AFTP6102 AFTE14P-GP
AFTP6103 AFTE14P-GP
AFTP6104 AFTE14P-GP
Table 61.1- USB2.0 PWR SW multi-source
Near USB1
1
USB_PW R2
B
USBPN9_TVS
USBPP9_TVS
Supplier
Description
TI
TPS2066DGN
TI
TPS2066DGN-1
Lenovo P/N
Wistron P/N
B
AFTP6107 AFTE14P-GP
1
1
1
AFTP6105 AFTE14P-GP
AFTP6108 AFTE14P-GP
AFTP6106 AFTE14P-GP
41R0511AA
N/A
74.02066.A71
74.02066.B71
Table 61.2- 150U 6.3V POSCAP multi-source
Supplier
Description
Lenovo P/N
NEC-TOKIN TEPSLB20J157M
N/A
Wistron P/N
77.C1571.09L
SANYO
6TPE150MAZB
N/A
77.21571.111
HPC
TNCB0J157MTRZTF
N/A
80.15715.12L
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB Connector
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
61
of
94
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
62
of
94
A
5
4
3
2
1
D
D
Bluetooth Connector
3D3V_S0
C
2
C
F6301
POLYSW-D5A6V-1-GP
BT1
65 WIFI_BUSY
27 BLUETOOTH_EN
TPAD14-GP
TP1702
1 LED_BDC_IN
4
6
8
10
12
14
NP2
16
1
BT_BUSY
65
3D3V_BT_S0
USB_PP3 18
USB_PN3 18
1
3
5
7
9
11
13
C6301
SC2D2U10V3KX-1GP
2
1
18 BDC_PRESENCE#
15
NP1
2
HRS-CONN14D-1-GP
B
B
BDC_PRESENCE#
WIFI_BUSY
BLUETOOTH_EN
BT_BUSY
3D3V_BT_S0
1
1
1
1
1
TP1106
TP1107
TP1108
TP1109
TP1110
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Bluetooth
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
63
of
94
A
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
FingerPrint
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
64
of
94
A
A
B
C
D
HALF MINI CARD FOR WLAN
E
1D5V_S0
3D3V_S0
3D3V_S0
WLAN1
4
DY
R6511 1
19,82 PCIE_WAKE#
2 0R2J-2-GP
2
R6504~R6509 close to Debug connector
3
5
7
9
11
13
15
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
63 BT_BUSY
63 WIFI_BUSY
20 PCIE_CLK_WLAN_RQ3#
20 CLK_PCIE_WLAN#
20 CLK_PCIE_WLAN
27
27
4
53
NP1
1
2 0R2J-2-GP E51_RXD_R
2 0R2J-2-GP E51_TXD_R
R6501 1
R6502 1
E51_RXD
E51_TXD
20
20
3
PCIE_RXN4
PCIE_RXP4
20 PCIE_TXN4
20 PCIE_TXP4
5V_S5
2 0R3J-0-U-GP +5V_MINI_DEBUG
R6503 1
LPC_AD0_C
LPC_AD1_C
LPC_AD2_C
LPC_AD3_C
LPC_FRAME#_C
1
0R2J-2-GP
1
0R2J-2-GP
1
0R2J-2-GP
1
0R2J-2-GP
1
0R2J-2-GP
DY
DY
DY
DY
DY
2R6505
2R6504
2R6507
2R6506
2R6509
PLT_RST#_WLAN R6510 1
LPC_AD0 21,27,71
LPC_AD1 21,27,71
LPC_AD2 21,27,71
LPC_AD3 21,27,71
LPC_FRAME# 21,27,71
2 0R2J-2-GP
3D3V_S0
PCH_SMBCLK_WLAN
R6512 1
PCH_SMBDATA_WLAN R6513 1
WIFI_RF_EN 27
PLT_RST# 5,18,27,32,36,66,71,80,82,83
2 0R2J-2-GP
2 0R2J-2-GP
PCH_SMBCLK 14,15,20,66
PCH_SMBDATA 14,15,20,66
3
USB_PN11 18
USB_PP11 18
WLAN_LED#
CLK_PCI_LPC_C R6508 2
TP6501
1
1 0R2J-2-GP
CLK_PCI_LPC 18,71
DY
TCN-CONN52A-2-GP
20.F1665.052
2nd = 20.F1517.052
1
C6503
SC10U6D3V5KX-1GP
C6504
SCD1U16V2KX-3GP
2
1
C6502
SCD1U16V2KX-3GP
2
1
C6507
SCD1U16V2KX-3GP
2
2
1
C6506
SCD1U16V2KX-3GP
2
1
C6505
SC10U6D3V5KX-1GP
3D3V_S0
2
2
2
C6501
SCD1U16V2KX-3GP
1
1D5V_S0
5V_S5
1
2
<Core Design>
Wistron Corporation
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
MINI CARD SLOT 1
Size
A4
Document Number
Date: Tuesday, November 09, 2010
A
B
C
Rev
SB
LLW-1 / LGG-1
D
Sheet
65
of
E
94
1
A
B
C
D
E
Mini Card Connector(WWAN)
Place near MINI Card CONN
1D5V_S0
3D3V_S0
3D3V_W W AN
3D3V_W W AN
R6602
W W AN1
1
C6607
SC33P50V2JN-3GP
1
1
2 SCD01U16V2KX-3GP SATA_RXP1_C
2 SCD01U16V2KX-3GP SATA_RXN1_C
C6614
C6615
1
1
2 SCD01U16V2KX-3GP SATA_TXN1_C
2 SCD01U16V2KX-3GP SATA_TXP1_C
18 W W AN_IN
1D5V_S0
3
C6609
SCD047U16V2KX-1-GP
1
C6608
SCD1U16V2KX-3GP
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
C6610
SC33P50V2JN-3GP
4
UIM_CLK
DY
1
4
6
8
10
12
14
16
UIM_PW R
UIM_DATA
UIM_CLK_SIM
UIM_RESET
UIM_VPP
C6605
SC100P50V2JN-3GP
3G_EN
27
PLT_RST# 5,18,27,32,36,65,71,80,82,83
PLT_RST#
3D3V_S0
PCH_SMBCLK_W W AN R6604 1
PCH_SMBDATA_W W AN R6609 1
2 0R2J-2-GP
2 0R2J-2-GP
PCH_SMBCLK 14,15,20,65
PCH_SMBDATA 14,15,20,65
USB_PN4_R
USB_PP4_R
3G_LED#
1 R6603
1 R6601
1
2 0R0402-PAD
2 0R0402-PAD
USB_PN4 18
USB_PP4 18
TP6602 TPAD14-GP
3
TCN-CONN52A-2-GP
20.F1665.052
2nd = 20.F1517.052
2
1
22,27 mSATA_DTCT#
2
2
1
3D3V_S0
0R0402-PAD
2
1
2
1
C6612
C6613
UIM_CLK_SIM
2
3
5
7
9
11
13
15
2
1
21 SATA_TXN1
21 SATA_TXP1
2
1
2
C6604
SC33P50V2JN-3GP
Place near Pin 24
21 SATA_RXP1
21 SATA_RXN1
C6606
SCD047U16V2KX-1-GP
53
NP1
1
DY
3D3V_S5
3D3V_W W AN
2.7A
10A
8
7
6
5
R6605
0R3J-0-U-GP
DY
U6601
SIM1
B
27 3G_POW ERON
R2
PDTC115EE-1-GP
2
2
1
2
C
CD
VCC
RST
CLK
GND
VPP
I/O
GND
GND
CD
NP1
NP2
CARD-PUSH-7P-2-GP
R6608
10KR2J-3-GP
20.I0046.011
2nd = 20.I0123.001
2
R1
UIM_VPP
UIM_DATA
1
2
3
5
6
7
8
9
10
NP1
NP2
DY
DY
Q6601
DY
TP6601
R6607
10KR2J-3-GP
DY
UIM_PW R
UIM_RESET
UIM_CLK
1
1
2
1
C6616
SCD22U10V2KX-1GP
2
R6606
3
DY
4
C6611
SIM Connector
2
TPCF8102-GP
DY
100KR2J-1-GP
2
1
SCD1U10V2KX-5GP
2
1
1
3D3V_S0
1
1D5V_S0
C6603
SC33P50V2JN-3GP
2
1
C6602
SCD047U16V2KX-1-GP
2
1
C6601
SCD047U16V2KX-1-GP
2
TC6601
ST220U6D3VDM-15GP
2
1
4
E
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
MINI CARD SLOT 2
Size
A3
Date:
A
B
C
D
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
E
66
of
94
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
67
of
94
A
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
68
of
94
A
A
B
C
Touch Pad Connector
D
E
Track Point Connector
5V_S0
1
3D3V_FP_FUSE
USB_PN2
USB_PP2
PALM_LED_N
PALM_LED_P
PAD_DETECT#
TP4DATAPAD_R
TP4CLKPAD_R
5V_TP_FUSE
PAD_RESET#
TPCLK_R
TPDATA_R
4
R6908
10KR2F-2-GP
5V_S0
2
5V_S0
TRP1
2
2
2
2
100KR2J-1-GP
1
100KR2J-1-GP
1
100KR2J-1-GP
1
TPAD1
100KR2J-1-GP
1
11
1
2
1
1
1
1
1
1
1
1
1
1
1
1
100KR2J-1-GP
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
FUSE-D5A32V-14-GP
2
1
4
TP6917
TP6915
TP6916
TP6920
TP6919
TP6918
TP6914
TP6913
TP6912
TP6911
TP6910
TP6908
R6901
F6902
R6902
R6904
R6903
R6905
21
1
5V_TP_FUSE
RN6902 SRN0J-6-GP
1
4
2
3
TP4CLKPAD_R
TP4DATAPAD_R
TP4_RESET
TP4MIDDLE
TP4RIGHT
TP4LEFT
TP4CLKPAD
TRP1_PW R
1
2
1 R6906
3D3V_S5
USB_PP2 18
USB_PN2 18
TP6909
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
1
1
1
TRP1_PW R
TP4CLKPAD
TP4LEFT
TP4RIGHT
TP4MIDDLE
TP4_RESET
TP4DATAPAD
3
3D3V_S0
1
KeyBoard Connector
2
1
20.K0392.020
2
TP6921
PTW O-CON20-2-GP-U
AFTE14P-GP
2 0R2J-2-GP
F6901
3D3V_FP_FUSE
AFTE14P-GP
1
5V_S0
R6907 1
TP6907
TP6906
TP6905
TP6904
TP6903
TP6902
TP6901
PAD_DETECT# 27
330R2F-GP
27
20.K0585.010
TP4CLKPAD
TP4DATAPAD
PALM_LED_P
PALM_LED_N
TP4_RESET
ACES-CON10-26-GP
TPDATA 27
TPCLK
27
PAD_RESET# 27
C6902
SC2D2U10V3KX-1GP
1
3
RN6901 SRN0J-6-GP
1
4
2
3
TPDATA_R
TPCLK_R
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
TP4DATAPAD
2
3
4
5
6
7
8
9
10
12
FUSE-D5A32V-14-GP
DY
C6903
SC4P50V2CN-GP
KB1
31
Q6901
27
1
PALM_LED
2
3
R1
R2
PALM_LED_N
2
LTC043ZUB-FS8-GP
1
KROW 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KROW 7
KROW 6
KCOL9
KROW 4
KROW 5
KCOL0
KROW 2
KROW 3
KCOL5
KCOL1
KROW 0
KCOL2
KCOL4
KCOL7
KCOL8
KCOL6
KCOL3
KCOL12
KCOL13
KCOL14
KCOL11
KCOL10
KCOL15
TP4LEFT
TP4MIDDLE
TP4RIGHT
KCOL16
KCOL17
32
Table 69.1- Transistor multi-source
ACES-CON30-8-GP
20.K0524.030
2nd = 20.K0385.030
Supplier
Description
Lenovo P/N
NXP
PDTC143ZU
N/A
84.00143.E1K
ON
DTA114EET1G
N/A
84.DT114.B11
ROHM
LTC043ZUB
N/A
84.00043.011
Title
Panasonic
DRC5143Z0L
N/A
84.05143.011
Size
A3
Wistron P/N
KROW [0..7]
27
KCOL[0..17]
27
TP6949 AFTE14P-GP
1
KROW 1
TP6948
TP6947
TP6946
TP6945
TP6944
TP6943
TP6942
TP6941
TP6940
TP6939
TP6938
TP6937
TP6936
TP6935
TP6934
TP6933
TP6932
TP6950
TP6929
TP6927
TP6928
TP6931
TP6930
TP6924
TP6922
TP6923
TP6926
TP6925
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
KROW 7
KROW 6
KCOL9
KROW 4
KROW 5
KCOL0
KROW 2
KROW 3
KCOL5
KCOL1
KROW 0
KCOL2
KCOL4
KCOL7
KCOL8
KCOL6
KCOL3
KCOL12
KCOL13
KCOL14
KCOL11
KCOL10
KCOL15
TP4LEFT
TP4MIDDLE
TP4RIGHT
KCOL16
KCOL17
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
2
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
TOUCH PAD CONNECTOR
Date:
A
B
C
D
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
E
69
of
94
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
70
of
94
A
5
4
3
2
1
Golden Finger for Debug Board
D
D
(BOTTOM VIEW)
TOP VIEW
C7101
SCD1U10V2KX-5GP
(14) (15)
(25) (26)
2
1
For EMI
....
5V_S0
3D3V_S0
GFDB1
TOP
PLT_RST#
LPC_FRAME#_R
C
PLT_RST#
TP80 TPAD30
1
2
0R0402-PAD
EXT_FWH#
PLT_RST#_DEBUG
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
1
2
3
4
5
6
7
8
9
10
11
12
13
12 13
BOTTOM
02 Do not mirror
CLK_PCI_LPC
R7106
1
2
3
4
5
6
7
8
9
10
11
12
13
2
....
1
14
15
16
17
18
19
20
21
22
23
24
25
26
14
15
16
17
18
19
20
21
22
23
24
25
26
EXT_FWH#
LPC_AD0_R
R7101
LPC_AD1_R
R7102
LPC_AD2_R
R7103
LPC_AD3_R
R7104
PLT_RST#_DEBUG
1
1
1
1
2
2
2
2
LPC_FRAME#_R R7105
1
2 0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
C
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CLK_PCI_LPC 18,65
LPC_FRAME# 21,27,65
PLT_RST#
5,18,27,32,36,65,66,80,82,83
GF-26P-GP-U1
ZZ.80648.026
B
B
3D3V_S0
DY
DB1
21,27,65 LPC_AD0
21,27,65 LPC_AD1
21,27,65 LPC_AD2
21,27,65 LPC_AD3
21,27,65 LPC_FRAME#
5,18,27,32,36,65,66,80,82,83 PLT_RST#
18,65 CLK_PCI_LPC
1
2
3
4
5
6
7
8
9
10
11
12
<Core Design>
Wistron Corporation
MLX-CON10-7-GP
A
20.D0183.110
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4
DEBUG CONN
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
71
of
94
A
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
72
of
94
A
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
73
of
94
A
5
4
3
2
1
Please apply Shield GND for SD_CLK signal between
R5U220 and SD Card Slot to decrease external noise.
D
D
+3.3V_RUN_CARD
1
1
C7402
SC47U6D3V5MX-1-GP
2
+3.3V_RUN_CARD
C7403
SCD01U25V2KX-3GP
2
1
Card Reader Connector
DY
R7401
10KR2J-3-GP
+3.3V_RUN_CARD
4
C
32
32
32
32
SD_D0
SD_D1
SD_D2
SD_D3
SD_D0
SD_D1
SD_D2
SD_D3
7
8
9
1
2
CDR1
VDD
DAT0
DAT1
DAT2
CD/DAT3
CMD
CLK
CD
WP
EMPTY
VSS
VSS
NP1
NP2
NP1
NP2
GND
CD/WP/GND
2
5
10
12
14
SD_CMD
SD_CLK
SD_DET#
SD_WP
SD_CLK
32
32
32
32
+3.3V_RUN_CARD trace = 40mil
C
C7402 lose CDR1
3
6
13
11
CARD-PUSH-14P-1-GP
20.I0078.011
B
B
DY
EC7404
SC12P50V2JN-3GP
1
EC7403
SC12P50V2JN-3GP
DY
EC7405
SC12P50V2JN-3GP
2
DY
1
EC7402
SC12P50V2JN-3GP
SD_CLK
2
1
DY
SD_D3
2
EC7401
SC12P50V2JN-3GP
2
2
DY
SD_D2
1
SD_D1
1
SD_D0
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CARD Reader CONN
Size
A4
Document Number
Date:
5
4
3
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
2
74
of
1
94
A
5
4
3
2
1
SSID = ExpressCard
+1.5V_CARD Max. 650mA, Average 500mA.
+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
New Card
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
75
of
94
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
76
of
94
A
A
B
C
D
E
4
4
3
3
BLANK
2
2
<Core Design>
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPM
Size
Document Number
Custom
Date:
A
B
C
D
Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
77
E
of
94
1
5
4
3
2
1
D
C
D
BLANK
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLANK
Size
A4
Document Number
Date: Tuesday, November 09, 2010
Rev
SB
LLW-1 / LGG-1
Sheet
78
of
94
A
5
4
3
2
1
G-Sensor
D
D
3D3V_S5
VCC3_ACC
R2
B
R1
27 GSENSE_ON#
C7901
C7902
DY
GSENSE_Z_R
R7905
NC#4
2
2
15
8
10
VOUTX
12
NC#11
11
NC#13
13
NC#16
16
GSENSE_Y_R
R7906
1
C7904
SCD1U10V2KX-5GP
NC#9
GSENSE_Y
27
GSENSE_X
27
C7907
SCD1U10V2KX-5GP
ANALOG_AGND
GSENSE_X_R
R7907
1
9
2 56KR2J-L1-GP
1
4
ANALOG_AGND
27
C7906
SCD1U10V2KX-5GP
2
NC#1
VOUTZ
VOUTY
C7905
SCD1U10V2KX-5GP
LIS34ALTR-GP
1
2 56KR2J-L1-GP
1
1
GSENSE_Z
DY
ANALOG_AGND
1
GND
GND
GND
C7903
SCD1U10V2KX-5GP
2
5
6
7
2 56KR2J-L1-GP
C
RES
ST
GND
2
R7904
0R0402-PAD-1-GP
2
R7903
100KR2J-1-GP
2
3
1
DY
2
1
1
27 GSENSE_TST
VDD
U7901
C
14
2
1
R7902
100KR2J-1-GP
1
1
ANALOG_AGND
DY
GSENSE_X
C7908
SCD1U10V2KX-5GP
2
E
Q7901
PDTA114EE-3-GP-U
SCD1U10V2KX-5GP
2
1
2 10R2J-2-GP
SC10U6D3V5KX-1GP
2
1
1
C
VCC3M_Q R7901
ANALOG_AGND
Table 79.1- Transistor multi-source
B
LIS34AL
No Accel
Layout Comment :
(1) Place C7904, C7905, Q7901, R7901, R7902,
C7901, C7902, R7903, R508 close to U7901.
KXTC8-2850
R7902
NO_ASM
ASM
R7903
ASM
ASM
All other
ASM
NO_ASM
(2) Avoid routing under DCDC switching area.
Supplier
Description
Lenovo P/N
Wistron P/N
NXP
PDTA114EE
N/A
84.00114.H1K
ON
DTA114EET1G
N/A
84.DT114.B11
ROHM
LTA014EEB
N/A
84.00014.01H
Panasonic
DRA9114E0L
N/A
84.09114.A11
Table 79.2- Accelerometer multi-source
Supplier
Description
Lenovo P/N
Wistron P/N
ST
LIS34ALTR-GP
41R0828AA
74.00034.0BZ
ROHM-KIONIX
KXTC8-2850-GP
N/A
74.KXTC8.0BZ
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
G-Sensor
Size
Custom
Date:
5
B
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
79
of
94
5
4
3
2
1
RFID
D
3D3V_S5
1
3D3V_S0
D
3D3V_S5
R8001
4K7R2J-2-GP
U8001
R1
E
PDTC115TE-GP
1
2
3
4
NC#1
NC#2
PROT#
GND
VDD
WP
SCL
SDA
8
7
6
5
SMB_CLK 20,82
SMB_DATA 20,82
BUL08-1FVJ-W-GP
PLT_RST#
5,18,27,32,36,65,66,71,82,83
1
B
PROT_EEPROM
C
C8001
2
Q8001
C
SCD01U16V2KX-3GP
2
C
Table 80.1- Transistor multi-source
B
Supplier
Description
Lenovo P/N
Wistron P/N
NXP
PDTC115TE
N/A
84.00115.E1K
ROHM
LTC015EEB
N/A
84.00015.01H
Panasonic
DRC9115T0L
N/A
84.09115.A11
B
Table 80.2- EEPROM multi-source
Supplier
Description
<Core Design>
Lenovo P/N
Wistron Corporation
Wistron P/N
A
ROHM
BUL08-1FVJ-W
54Y9016AA
72.BUL08.00Q
NXP
PCA24S08ADP
N/A
72.24S08.A0Q
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
SANYO
LE26CAP08TT-TLM-H
N/A
Size
A4
72.26C08.00R
Document Number
4
3
Rev
SB
LLW-1 / LGG-1
Date: Tuesday, November 09, 2010
5
RFID
2
Sheet
80
of
1
94
A
5
4
3
2
1
D
D
C
C
BLANK
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
81
of
94
5
4
3
2
1
TO EXP BOARD CONN
3D3V_S0
D
1.3A
3D3V_S5
275mA
650mA
2A
5,18,27,32,36,65,66,71,80,83
PLT_RST#
20,80 SMB_CLK
20,80 SMB_DATA
19,65 PCIE_W AKE#
19,27,36,37,47 PM_SLP_S3#
19,27,46 PM_SLP_S4#
20 PCIE_CLK_NEW _RQ5#
C
TOP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1D5V_S0
5V_S5
GF1
BOTTOM
02 Do not mirror
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
USB_PN13 18
USB_PP13 18
USB_PN10 18
USB_PP10 18
USB_AO_SEL0 27
CLK_PCIE_NEW # 20
CLK_PCIE_NEW 20
PCIE_RXN8 20
PCIE_RXP8 20
USB_AO_SEL1 27
PCIE_TXN8 20
PCIE_TXP8 20
USB_PW R_EN2 27
USB_OC#10_11 18
C
GF-MINIPCI52P-GP
ZZ.00PAD.U71
TO DC BOARD CONN
3D3V_AUX_S5
AD+
1
3D3V_S0 3D3V_LAN_S5
B
R8201
330R2F-GP
42
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
27 KBC_PW RBTN#
TP2
TPAD30
1
41
B
2
DCCN1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
LAN_XI
20
PCIE_W AKE# 19,65
PLT_RST#
5,18,27,32,36,65,66,71,80,83
PCIE_CLK_LAN_RQ0# 20
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_TXN2
PCIE_TXP2
PCIE_RXP2
PCIE_RXN2
AD_OFF
ACDC_ID2
AC_IN_LED_P
20
20
20
20
20
20
27
27
AC_IN_LED_N
2
Q8201
ACES-CONN40A-9-GP
20.F1844.040
2
A
TP8201
TP8202
TP8203
TP8204
TP8205
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
1
3
AC_IN_LED_P
AC_IN_LED_N
ACDC_ID2
AD_OFF
AD+
R1
1
AC_IN_LED 27
R2
<Core Design>
A
LTC043ZUB-FS8-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
IO Board Connector
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
82
of
94
5
4
4 PEG_TXP[0..15]
3
PEG_RXP[0..15] 4
1 OF 8
VGA1A
2
4 PEG_TXN[0..15]
1
CONFIGURATION STRAPS
PEG_RXN[0..15] 4
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
D
PEG_TXP2
PEG_TXN2
W38
V37
PCIE_TX0P
PCIE_TX0N
Y33 PEG_C_RXP0
Y32 PEG_C_RXN0
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33 PEG_C_RXP1
W32 PEG_C_RXN1
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33 PEG_C_RXP2
U32 PEG_C_RXN2
C8301
C8302
C8303
C8304
C8305
C8306
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP0
2 SCD1U6D3V1KX-GP PEG_RXN0
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP1
2 SCD1U6D3V1KX-GP PEG_RXN1
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP2
2 SCD1U6D3V1KX-GP PEG_RXN2
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30 PEG_C_RXP3
U29 PEG_C_RXN3
C8308
C8307
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP3
2 SCD1U6D3V1KX-GP PEG_RXN3
PEG_TXP4
PEG_TXN4
U38
T37
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
T33
T32
PEG_C_RXP4
PEG_C_RXN4
C8309
C8310
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP4
2 SCD1U6D3V1KX-GP PEG_RXN4
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
T30
T29
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP5
2 SCD1U6D3V1KX-GP PEG_RXN5
PCIE_TX6P
PCIE_TX6N
P33 PEG_C_RXP6
P32 PEG_C_RXN6
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP6
2 SCD1U6D3V1KX-GP PEG_RXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
T35
R36
R38
P37
P35
N36
N38
M37
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PEG_TXP9
PEG_TXN9
M35
L36
PCIE_RX9P
PCIE_RX9N
PEG_TXP10
PEG_TXN10
L38
K37
PCIE_RX10P
PCIE_RX10N
PEG_TXP11
PEG_TXN11
K35
J36
PCIE_RX11P
PCIE_RX11N
PEG_TXP12
PEG_TXN12
J38
H37
PCIE_RX12P
PCIE_RX12N
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15
H35
G36
G38
F37
F35
E37
PCI EXPRESS INTERFACE
V35
U36
PEG_TXP6
PEG_TXN6
B
Y35
W36
PCIE_RX0P
PCIE_RX0N
PEG_TXP3
PEG_TXN3
PEG_TXP5
PEG_TXN5
C
AA38
Y37
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_TX7P
PCIE_TX7N
PEG_C_RXP5
PEG_C_RXN5
P30 PEG_C_RXP7
P29 PEG_C_RXN7
C8311
C8312
C8313
C8314
C8316
C8315
1
PX
1
PX
GPIO0
X
1
TX_DEEMPH_EN
GPIO1
PCIE TRANSMITTER DE-EMPHASIS ENABLED
0:Tx de-emphasis disabled 1:Tx de-emphasis enabled
X
1
BIF_GEN2_EN_A
GPIO2
0:Advertises the PCIe device as 2.5GT/s capable at power on.
1:Advertises the PCIe device as 5.0GT/s capable at power on.
0
0
GPIO5_AC_BATT
GPIO5
optional input allow the system to request a fast
power reduction by setting GPIO5 to low.
?
0
GPIO8_ROMSO
GPIO8
RESERVED
0
0
N33 PEG_C_RXP8
N32 PEG_C_RXN8
PCIE_TX9P
PCIE_TX9N
N30 PEG_C_RXP9
N29 PEG_C_RXN9
C8318
C8317
ROMIDCFG[2:0]
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP8
2 SCD1U6D3V1KX-GP PEG_RXN8
C8320
C8319
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP9
2 SCD1U6D3V1KX-GP PEG_RXN9
PCIE_TX10P
PCIE_TX10N
L33
L32
PEG_C_RXP10 C8321
PEG_C_RXN10 C8322
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP10
2 SCD1U6D3V1KX-GP PEG_RXN10
PCIE_TX11P
PCIE_TX11N
L30
L29
PEG_C_RXP11 C8323
PEG_C_RXN11 C8324
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP11
2 SCD1U6D3V1KX-GP PEG_RXN11
PCIE_TX12P
PCIE_TX12N
K33 PEG_C_RXP12 C8325
K32 PEG_C_RXN12 C8326
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP12
2 SCD1U6D3V1KX-GP PEG_RXN12
PCIE_TX13P
PCIE_TX13N
J33
J32
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP13
2 SCD1U6D3V1KX-GP PEG_RXN13
PCIE_TX14P
PCIE_TX14N
K30 PEG_C_RXP14 C8330
K29 PEG_C_RXN14 C8329
1
PX
1
PX
2 SCD1U6D3V1KX-GP PEG_RXP14
2 SCD1U6D3V1KX-GP PEG_RXN14
PCIE_TX15P
PCIE_TX15N
PEG_C_RXP13 C8328
PEG_C_RXN13 C8327
H33 PEG_C_RXP15 C8332
H32 PEG_C_RXN15 C8331
1
PX
1
PX
GPIO21_BB_EN
2
1
2
NC#AJ21
NC#AK21
PWRGOOD
VGA_RST# AA30
PERST#
DY
DY
C8333
MADISON-PRO-2-GP
SC47P50V2JN-3GP
Y30 PCIE_CALRP
R8316 1
PX
2 1K27R2F-L-GP
Y29 PCIE_CALRN
R8318 1
PX
2 2KR2F-3-GP
RESERVED
0
0
RSVD
GENERICC
RESERVED
0
0
AUD[1]
HSYNC
X
1
AUD[0]
VSYNC
X
1
AUD[1:0]:11-Audio for both DisplayPort and HDMI
3D3V_VGA_S0
R8301 1
2 3KR2J-2-GP
PX
85 TX_DEEMPH_EN
R8302 1
85 BIF_GEN2_EN_A
R8303 1
2 10KR2J-3-GP
R8304 1
2 10KR2J-3-GP
85 GPIO8_ROMSO
DY
DY
VGA_DIS
85
CONFIG0
R8306 1
2 10KR2J-3-GP
85
CONFIG1
R8307 1
2 10KR2J-3-GP
85
CONFIG2
R8308 1
PX
1V_VGA_S0
R8313 1
85 GPIO5_AC_BATT
R8314 1
85 GPIO21_BB_EN
R8315 1
DY
DY
DY
DY
DY
85 JTAG_TRST#_VGA
A
DY
PX
86 1D5V_VGA_PW OK
R8319 2
93 1D8V_S0_VGA_PG
R8325 2
PLT_RST#
1
B
2
A
1 0R2J-2-GP
1D8V_S0_VGA_PG_1
1 0R2J-2-GP
2
1
PX
VGA_RST#
0R2J-2-GP
VGA_RST#
84
PX
20,85 JTAG_TCK_VGA
3D3V_VGA_S0
5
Y
4
DY
3
C8334
SCD1U10V2KX-5GP
74LVC1G08GW -1-GP
GND
18 DGPU_HOLD_RST#
1
B
2
A
3
73.01G08.L04
2ND = 73.7SZ08.DAH
VCC
5
Y
4
dGPU mode
H
IGPU
L
IGPU with BACO
H
4
B
2 10KR2J-3-GP
DY
2 10KR2J-3-GP
JTAG SIGNAL OPTION
2 10KR2J-3-GP
Signal
Normal
mode
TESTEN
"1"(PU) "1"(PU)
"0"(PD)
"0"(PD) "1"(PU)
NC
JTAG_TCK
U8302
VCC
R8323 1
2 5K11R2F-L1-GP
TESTEN Vancouver need to 5.1K ohm
Mannhatton need to 1K ohm
2 10KR2J-3-GP
85
PX
1 10KR2J-3-GP
2 10KR2J-3-GP
JTAG_TMS
CLK
Debug
mode
pilot run
mode
"1"(PU)
NC
"1"(PU) "1"(PU)
NC
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
VGA_RST#
Title
GND
GPU_PCIE/STRAPPING(1/5)
74LVC1G08GW -1-GP
Size
A3
73.01G08.L04
2ND = 73.7SZ08.DAH
Date:
5
TESTEN
2 10KR2J-3-GP
DY
R8327 1
PE_GPIO0
3D3V_VGA_S0
U8301
DY
2
2 10KR2J-3-GP
R8322 1
R8326 2
JTAG_TRST#
R8321 1
R8324 1
PX
2 10KR2J-3-GP
85
85 BIOS_ROM_EN
PX
85 JTAG_TMS_VGA
2 3KR2J-2-GP
PX
R8305 1
3D3V_VGA_S0
dGPU reset for PX/SG transitions
PLT_RST#
0
H2SYNC
PX
5,18,27,32,36,65,66,71,80,82
0
X
RSVD
85 TX_PW RS_ENB
2 SCD1U6D3V1KX-GP PEG_RXP15
2 SCD1U6D3V1KX-GP PEG_RXN15
PCIE_CALRP
0
X
VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is connected on the VIP Host interface.
V2SYNC
0
0 0 1
(256MB)
X
0
2
R8320
0R2J-2-GP
RESERVED
PX
PCIE_CALRN
X
0:Disable external BIOS ROM device
1:Enable external BIOS ROM device
PIN STRAPS
PCIE_REFCLKP
PCIE_REFCLKN
AJ21
AK21
PW RGOOD AH16
10KR2F-2-GP
1
27,85 PCIE_RST#
R8317 1
GPIO21
X
D
C
CALIBRATION
PX
GPIO[13:11]
0
BIOS_ROM_EN=1, Config[2:0] defines the ROM type
BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size
BIOS_ROM_EN GPIO_22_ROMCSB
CLOCK
AB35
AA36
20 CLK_PCIE_VGA
20 CLK_PCIE_VGA#
0:VGA Controller capacity enabled
1:The device won't be recognized as the system's VGA controller
GPIO9
VGA_DIS
VIP_DEVICE_STRAP_EN
PCIE_TX8P
PCIE_TX8N
PLATFORM
SETTING
Transmitter Power Savings Enable
0: 50% Tx output swing 1: Full Tx output swing
TX_PWRS_ENB
2 SCD1U6D3V1KX-GP PEG_RXP7
2 SCD1U6D3V1KX-GP PEG_RXN7
RECOMMEND
DESCRIPTION OF DEFAULT SETTINGS
PIN
STRAPS
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
83
of
94
RASA0#
RASA1#
88
89
CASA0#
CASA1#
K20
K17
CASA0#
CASA1#
88
89
CSA0#_0
CSA0#_1
K24
K27
CSA0#_0
88
CSA1#_0
CSA1#_1
M13
K16
CSA1#_0
89
MVREFDA
MVREFSA
CKEA0
CKEA1
K21
J20
CKEA0
CKEA1
88
89
MVREFDB
MVREFSB
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
WEA0#
WEA1#
K26
L15
WEA0#
WEA1#
88
89
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
MAA0_8
MAA1_8
H23
J19
88
88
88
88
89
89
89
89
DDBIA0_0/QSA_0#/WDQSA_0
DDBIA0_1/QSA_1#/WDQSA_1
DDBIA0_2/QSA_2#/WDQSA_2
DDBIA0_3/QSA_3#/WDQSA_3
DDBIA1_0/QSA_4#/WDQSA_4
DDBIA1_1/QSA_5#/WDQSA_5
DDBIA1_2/QSA_6#/WDQSA_6
DDBIA1_3/QSA_7#/WDQSA_7
A34
E30
E26
C20
C16
C12
J11
F8
QSAN_0
QSAN_1
QSAN_2
QSAN_3
QSAN_4
QSAN_5
QSAN_6
QSAN_7
88
88
88
88
89
89
89
89
ADBIA0/ODTA0
ADBIA1/ODTA1
J21
G19
CLKA0
CLKA0#
H27
G27
CLKA1
CLKA1#
J14
H14
RASA0#
RASA1#
91
ODTA0
ODTA1
88
89
CLKA0
CLKA0#
88
88
MAA13
MDB[32..63]
88,89
83
Y12
AA12
AD28
TESTEN
CLKTESTA AK10
CLKTESTB AL10
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
WCKB0_0/DQMB_0
WCKB0#_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0#_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1#_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1#_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSBP_0
QSBP_1
QSBP_2
QSBP_3
QSBP_4
QSBP_5
QSBP_6
QSBP_7
90
90
90
90
91
91
91
91
DDBIB0_0/QSB_0#/WDQSB_0
DDBIB0_1/QSB_1#/WDQSB_1
DDBIB0_2/QSB_2#/WDQSB_2
DDBIB0_3/QSB_3#/WDQSB_3
DDBIB1_0/QSB_4#/WDQSB_4
DDBIB1_1/QSB_5#/WDQSB_5
DDBIB1_2/QSB_6#/WDQSB_6
DDBIB1_3/QSB_7#/WDQSB_7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSBN_0
QSBN_1
QSBN_2
QSBN_3
QSBN_4
QSBN_5
QSBN_6
QSBN_7
90
90
90
90
91
91
91
91
ADBIB0/ODTB0
ADBIB1/ODTB1
MVREFDB
MVREFSB
TESTEN
B
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
T7
W7
90
90
90
90
91
91
91
91
Vancouver
C
ODTB0
ODTB1
90
91
CLKB0
CLKB0#
90
90
CLKB1
CLKB1#
91
91
CLKB1
CLKB1#
AD8
AD7
RASB0#
RASB1#
T10
Y10
RASB0#
RASB1#
90
91
CASB0#
CASB1#
W10
AA10
CASB0#
CASB1#
90
91
90
CSB0#_0
CSB0#_1
P10
L10
CSB0#_0
CSB1#_0
CSB1#_1
AD10
AC10
CSB1#_0
91
CKEB0
CKEB1
U10
AA11
CKEB0
CKEB1
90
91
WEB0#
WEB1#
N10
AB11
WEB0#
WEB1#
90
91
DRAM_RST#
T8
W8
MAB13
PX
AH11 DRAM_RST
R8418 1
1D5V_VGA_S0
DY
R8401
2K2R2J-2-GP
PX
2 10R2J-2-GP
R8420
5K1R2J-4-GP
PX
R8402 1
2 51R2J-2-GP
PX
MEM_RST
C8401
SC120P50V2JN-1GP
88,89,90,91
B
DY
R8419
0R2J-2-GP
3
4
1
2
MADISON-PRO-2-GP
Mannhatton
90,91
PX
RN8401
SRN4K7J-8-GP
PX
D
L9
L8
DY
MADISON-PRO-2-GP
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
CLKB0
CLKB0#
MAB0_8
MAB1_8
CLKTESTA
CLKTESTB
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
2
M12
M27
AH12
K23
K19
QSAP_0
QSAP_1
QSAP_2
QSAP_3
QSAP_4
QSAP_5
QSAP_6
QSAP_7
88
88
88
88
89
89
89
89
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
2
1
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
89
89
C34
D29
D25
E20
E16
E12
J10
D7
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
1
MEM_CALRN0
L27
MEM_CALRN1
N12
MEM_CALRN2 AG12
CLKA1
CLKA1#
A32
C32
D23
E22
C14
A14
E10
D9
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
2
L18
L20
C
WCKA0_0/DQMA_0
WCKA0#_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0#_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1#_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1#_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
1
MVREFDA
MVREFSA
MDA[32..63]
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
2
89
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
4 OF 8
DDR2
GDDR5/GDDR3
DDR3
VGA1D
DDR2
GDDR3/GDDR5
DDR3
MDB[0..31]
1
1
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
90
2
GDDR5
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
GDDR5
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
D
3
3 OF 8
DDR2
GDDR5/GDDR3
DDR3
VGA1C
DDR2
GDDR3/GDDR5
DDR3
MDA[0..31]
MEMORY INTERFACE A
88
4
MEMORY INTERFACE B
5
basic topology should be used for DRAM_RST for
** This
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
PX
C8402
SCD1U10V2KX-5GP
PX
R8415
100R2F-L1-GP-U
Rb
DDR3/GDDR3 Memory Stuff Option(Mad/Park)
A
1
2
2
1
1
C8403
SCD1U10V2KX-5GP
PX
Rb
R8416
100R2F-L1-GP-U
PX
C8404
SCD1U10V2KX-5GP
PX
R8417
100R2F-L1-GP-U
Rb
1
R8414
100R2F-L1-GP-U
Rb
1
1
1
PX
MEM_CALRP2
243R2F-2-GP
MVREFSB
PX
C8405
SCD1U10V2KX-5GP
2
2
MVREFDB
2
R8409 1
PX
R8413
40D2R2F-GP
Ra
1
PX
MVREFSA
PX
R8412
40D2R2F-GP
2
MEM_CALRN2
243R2F-2-GP
MEM_CALRP0
243R2F-2-GP
MVREFDA
Ra
are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
1D5V_VGA_S0
PX
R8411
40D2R2F-GP
2
2
2
PX
Ra
R8410
40D2R2F-GP
2
R8406 1
R8408 1
1D5V_VGA_S0
1
PX
MEM_CALRN1
243R2F-2-GP
PX
MEM_CALRP1
243R2F-2-GP
2
2
2
1
R8405 1
R8407 1
PX
Ra
PX
2
PX
MEM_CALRN0
243R2F-2-GP
2
2
1
PX
2
1D5V_VGA_S0
R8403 1
1D5V_VGA_S0
1
1D5V_VGA_S0
2
Madison: MEM_CALRP[0,2] signals are used.
Park: MEM_CALRP1 and MEM_CALRN1 are used
DDR3/GDDR3 Memory Stuff Option(M92/M96)
GDDR5
GDDR3
DDR3
MVDDQ
1.5V
1.8V/1.5V
1.5V
MVDDQ
GDDR3
DDR3
1.8V/1.5V
Ra
40.2R
40.2R
40.2R
1.5V
Ra
40.2R
100R
Rb
100R
100R
100R
Rb
100R
100R
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU Memory(2/5)
Size
Custom
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
84
of
94
4
3
AU24
AV23
TXCAP_DPA3P
TXCAM_DPA3N
MUTI GFX
DPA
AT15
AR14
TX0P_DPC2P
TX0M_DPC2N
1
GPIO17_VGA
10KR2J-3-GP
R8521 1
124R2F-U-GP
2
XTALIN
1
20,83 JTAG_TCK_VGA
Voltage Swing:1.8V
DY
2
R8519
150R2F-1-GP
1D8V_VGA_S0
1HDMI_HPD_GPU
TP8521
AK24
SCL
SDA
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
DAC1
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCS#
GPIO_23_CLKREQ#
JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DAC2
GENERICF
GENERICG
G
G#
B
B#
2
GPU_VREFG
AH13
R8516
249R2F-GP
2
DPLL_PVDD
C8514
SCD1U10V2KX-5GP
AN31
XTALIN
AV33
XTALOUT AU34
PX
C8518
SCD1U10V2KX-5GP
2
1
SC1U6D3V2KX-GP
2
1
SC4D7U6D3V3KX-GP
2
1
DPLL_VDDC
(1.0V@125mA DPLL_VDDC)
(1.1V@150mA DPLL_VDDC For M96/M92)
C8517
TP8516
1 TPAD14-GP
XO_IN
PX
AW34
AW35
C8519
VGA_DPLUS
VGA_DMINUS
TP8517
TP8529
1
1
TP8511
1 TPAD14-GP VGA_TS_FDO
AF29
AG29
AK32
TSVDD
R8504 1
PX
C8524
2
1
2
C8525
XTALOUT
2
1
XTAL-27MHZ-65-GP-U
SC10P50V2JN-4GP
1
C8521
SC1U6D3V2KX-GP
PX
C8522
SCD1U10V2KX-5GP
MADISON-PRO-2-GP
2 0R0402-PAD
VDD1DI
PX
C8506
SC1U6D3V2KX-GP
R8506
1
2
0R0402-PAD
VDD2DI
(1.8V@50mA VDD2DI)
R8507 1
2 0R2J-2-GP
DY
C8508
SCD1U10V2KX-5GP
VDD2DI
A2VDDQ
R8525 1
R8526 1
2 0R2J-2-GP
2 0R2J-2-GP
A2VDD
RBS
A2VDDQ
RBS
C8510
SCD1U10V2KX-5GP
B
AF33
3D3V_VGA_S0
AA29 R2SET R8517 1
715R2F-GP
AM26
AN26
DDC1CLK
DDC1DATA
A2VDD
(3.3V@130mA A2VDD)
2
R8509 1
RBS
VGA_CRT_DDCCLK
VGA_CRT_DDCDATA
1
1
2 0R2J-2-GP
RBS
TP8527
TP8528
DY
C8513
SCD1U10V2KX-5GP
AM27
AL27
AUX1P
AUX1N
AM19
AL19
AN20
AM20
AL30
AM30
DDC1/DDC2/DDC6 have 5V-tolerant
AL29
AM29
DDCCLK_AUX4P
DDCDATA_AUX4N
AN21
AM21
DDCCLK_AUX5P
DDCDATA_AUX5N
AJ30
AJ31
DDC6CLK
DDC6DATA
AK30
AK29
DDCCLK_AUX7P
DDCDATA_AUX7N
TSVDD
TSVSS
(1.8V@100mA VDD1DI)
PX
A
2
1
PX
AVSSQ
VDD1DI
SRN150F-1-GP
<Core Design>
PX
X8501
1
C8520
SC4D7U6D3V3KX-GP
C8503
SCD1U10V2KX-5GP
AD33
TS_FDO
TS_A
8
7
6
5
2 499R2F-2-GP
AVDD
RBS
AUX2P
AUX2N
THERMAL
VGA_CRT_RED
1
VGA_CRT_GREEN 2
VGA_CRT_BLUE
3
4
AG33
XO_IN
DPLUS
DMINUS
TP8525
TP8526
1
1
PX
(1.8V@1.5mA A2VDDQ)
AG31
AG32
DDC2CLK
DDC2DATA
XO_IN2
R8514 1
PX
RN8502
2 10MR2J-L-GP
PX
XTALIN
AJ32
AJ33
DY
2
1
2
PX
AD29
AC29
H2SYNC
V2SYNC
DPLL_PVDD
DPLL_PVSS
PLL/CLOCK
PX
+3.3V tolerant
VGA_CRT_HSYNC
VGA_CRT_VSYNC
C
2 0R0402-PAD
RBS
R2SET
XTALIN
XTALOUT
AVDD
(1.8V@65mA AVDD)
R8502 1
AC32
AD32
AF32
C
Y
COMP
A2VDDQ
DPLL_VDDC
1D8V_VGA_S0
AF30
AF31
B2
B2#
VREFG
(1.8V@20mA TSVDD)
A
TP8524
1
AVSSQ
DDCCLK_AUX3P
DDCDATA_AUX3N
AL31
1D8V_VGA_S0
L8504 PX
1
2
BLM15BD121SS1D-GP
TP8523
VGA_CRT_BLUE
AD30
AD31
G2
G2#
HPD1
1V_VGA_S0
DY
VGA_CRT_GREEN 1
AF37
AE38
AC30
AC31
PX
AM32
AN32
AN36
AP37
AVSSQ
R2
R2#
DDC/AUX
L8506 1
2
BLM18PG471SN1D-GP
AE36
AD35
AC33
AC34
A2VSSQ
PX
1
C8516
SCD1U10V2KX-5GP
AP35
AR35
R8524 1
A2VDD
PLACE VREFG DIVIDER AND CAP CLOSE TO ASIC
PX
TP8522
AD34
AE34
VDD1DI
VSS1DI
1
PX
1
AB34 GPU_RSET
RSET
AVDD
AVSSQ
VDD2DI
VSS2DI
2
C8515
SC1U6D3V2KX-GP
1
PX
2
C8505
SC4D7U6D3V3KX-GP
1
DY
2
1
L8501 1
2
BLM18PG471SN1D-GP
VGA_CRT_RED
AC36
AC38
HSYNC
VSYNC
R8515
499R2F-2-GP
(1.8V@75mA DPLL_PVDD)
PX
AD39
AD37
PX
DPLL_PVDD
AR37
AU39
MADISON-PRO-2-GP
R
R#
1
1D8V_VGA_S0
2
B
PX
AT23
AR22
TX5P_DPD0P
TX5M_DPD0N
TXOUT_L3P
TXOUT_L3N
AW37
AU35
2
DY
C
AU22
AV21
TX4P_DPD1P
TX4M_DPD1N
GENERAL PURPOSE I/O
AH20
AH18
RN8501 PX
SRN0J-6-GP
AN16
1
4GPIO_VGA_03_DATA AH23
2
3GPIO_VGA_04_CLK
AJ23
AH17
AJ17
AK17
AJ13
83 GPIO8_ROMSO
AH15
83
VGA_DIS
AJ16
AK16
83
CONFIG0
AL16
83
CONFIG1
AM16
83
CONFIG2
VPIO14_VGA
1
AM14
TP8506
AM13
92 PWRCNTL_0
1GPIO16_SSIN
AK14
GPIO17_VGA
TP8502
AG30
1GPIO18_VGA
AN14
THERMTRIP_VGA AM17
TP8507
AL13
92 PWRCNTL_1
AJ14
83 GPIO21_BB_EN
AK13
83 BIOS_ROM_EN
AN13
20 PEG_CLKREQ#
AM23
83 JTAG_TRST#_VGA
TP8501
1JTAG_TDI_VGA
AN23
AK23
20,83 JTAG_TCK_VGA
AL24
83 JTAG_TMS_VGA
TP8503
1JTAG_TDO_VGA AM24
AJ19
AK19
GENERICC
TP8512
1
AJ20
TP8513
1GENERICD
AK20
TP8509
1GENERICE_HPD4 AJ24
TP8514
1GENERICF
AH26
TP8515
1GENERICG
AH24
83 TX_PWRS_ENB
83 TX_DEEMPH_EN
83 BIF_GEN2_EN_A
27,28 SMBD_THERM
27,28 SMBC_THERM
83 GPIO5_AC_BATT
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AP34
AR34
1
AK26
AJ26
R8520 2
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AT21
AR20
TX3P_DPD2P
TX3M_DPD2N
PX
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AU20
AT19
TXCDP_DPD3P
TXCDM_DPD3N
I2C
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AT17
AR16
TX2P_DPC0P
TX2M_DPC0N
3D3V_VGA_S0
AF35
AG36
LVTMDP
AU16
AV15
TX1P_DPC1P
TX1M_DPC1N
DPD
AG38
AH37
2
C8526
SCD1U10V2KX-5GP
TXOUT_U3P
TXOUT_U3N
AH35
AJ36
1
DY
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AU14
AV13
TXCCP_DPC3P
TXCCM_DPC3N
D
AJ38
AK37
1
1 0R2J-2-GP
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AT33
AU32
TX5P_DPB0P
TX5M_DPB0N
DPC
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AR32
AT31
TX4P_DPB1P
TX4M_DPB1N
RN8503
SRN10KJ-5-GP
AK35
AL36
2
5,22,36
DPB
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AV31
AU30
TX3P_DPB2P
TX3M_DPB2N
AK27 VGA_LBKLT_CTL
AJ27 VGA_LCDVDD_EN
PX
AR30
AT29
TXCBP_DPB3P
TXCBM_DPB3N
VARY_BL
DIGON
1
H_THERMTRIP#
AT27
AR26
TX2P_DPA0P
TX2M_DPA0N
2
1
R8503
10KR2J-3-GP
2
R8510
10KR2J-3-GP
2
2
DY
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
1
2
2
1
1
1
2
R8512
10KR2J-3-GP
DY
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
LVDS CONTROL
2
1
1
1
2
1
1
2
VRAM_1G
3
2
1
R8501
10KR2J-3-GP
2
DY
DY
Hynix
R8518
10KR2J-3-GP
Q5801_2
27,83 PCIE_RST#
R8508 2
R8511
10KR2J-3-GP
1 0R2J-2-GP
1
VGA_RST#
83
R8505
10KR2J-3-GP
2
THERMTRIP_R
5
R8523
10KR2J-3-GP
Q8501
2N7002KDW-GP
R8522 2
R8513
10KR2J-3-GP
MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
DY
6
DY
THERMTRIP_VGA
4
D
PX
7 OF 8
VGA1G
AU26
AV25
TX1P_DPA1P
TX1M_DPA1N
PX
LVDS Interface
AT25
AR24
TX0P_DPA2P
TX0M_DPA2N
1
2
1D8V_VGA_S0
SAMSUNG VRAM_2G
1
2 OF 8
VGA1B
DVPDATA [3:0]
0111
2Gbit Hynix-H5TQ2G63BFR-12C (800MHz) (Whistler-LP 2G / Seymour-XT 1G)
1111
2Gbit Samsung-K4W2G1646C-HC12 (800MHz) (Whistler-LP 2G / Seymour-XT 1G)
0011
1Gbit Hynix-H5TQ1G63BFR-12C
(800MHz) (Whistler-LP 1G)
1011
1Gbit Samsung-K4W1G1646E-HC12 (800MHz) (Whistler-LP 1G)
2
4
3
5
DVPDATA [3:2:1:0] for VRAM type
selection H/W strap
Should provide VRAM Table for VBios request
SC10P50V2JN-4GP
Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or
b) 27MHz (1.8V) oscillator connected to XTALIN or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
85
of
94
5
4
3
1
1D8V_VGA_S0
(1.8V@504mA PCIE_VDDR)
MEM I/O
1D5V_VGA_S0
2
5 OF 8
VGA1E
For DDR3/GDDR5, MVDDQ = 1.5V
C8673
PX
C8674
M20
M21
NC_VDDRHA
NC_VSSRHA
V12
U12
NC_VDDRHB
NC_VSSRHB
MPV18
PLL
AB37
PX
SC4D7U6D3V3KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SCD1U10V2KX-5GP
2
1
SC1U6D3V2KX-GP
2
1
C8633
1FB_VDDCI
TPAD14-GP
FB_VDDC
AG28
FB_VDDCI
ISOLATED
CORE I/O
PX
C8680
92
GND_SENSE
AH29
FB_GND
C8634
D
C8648
PX
C8649
PX
C8669
C8641
PX
C8670
PX
C8642
PX
C8671
SC1U6D3V2KX-GP
2
1
PX
SC1U6D3V2KX-GP
2
1
C8640
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
PX
PX
C8643
PX
C8644
PX
C8672
U8601
AO3400A-GP
BIF_VDDC
VGA_CORE
BIF_VDDC_CORE
D
VGA_CORE
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
PX
84.03400.B37
R8603
1KR2J-1-GP
PX
Mode
BIF_VDDC
0
Normal
VGA_Core
1
BACO
1V_VGA
PX_EN#
BACO mode
R8601
1
2 1D5V_VGA_PWOK_R
0R2J-2-GP
1D5V_VGA_PWOK
DY
PX
3D3V_VGA_S0
U8605
1
83 1D5V_VGA_PWOK
(GDDR3/DDR3 1.12V@4A VDDCI)
2
92 8209A_EN/DEM_VGA
VGA_CORE
PX
Q8601
PX
C8681
PX
C8682
PX
C8683
PX
C8684
PX
C8685
PX
C8686
87
PX_EN
B
Q8602
5
VCC
A
4
Y
1D5V_VGA_PWOK_R
GND
PX_EN##
4
3
5
2
6
1
PX_EN#
74LVC1G08GW-1-GP
73.01G08.L04
2ND = 73.7SZ08.DAH
G
PX
D
2N7002KDW-GP
84.2N702.A3F
C8687
2nd = 84.DM601.03F
S
2N7002K-2-GP
VGA_CORE
B
PX
C8655
PX
C8656
PX
C8657
PX
C8658
PX
C8659
PX
C8660
PX
C8661
PX
C8662
PX
C8663
1D5V_VGA_PWOK
3D3V_S5
3D3V_VGA_S0
PX
PX
PX
R8606
10KR2J-3-GP
2
2
PX
Q8603
PX
G
C8690
D
1D5V_VGA_PWOK
PX
1
Q8604
MMBT3904-4-GP
B
2
2N7002K-2-GP
84.2N702.J31
2nd = 84.2N702.031
2
MPV18
1
PX
DY
C8693
SCD1U10V2KX-5GP
E
PX
R8608
2K2R2J-2-GP
83
S
1D5V_VGA_S0
(M97, Broadway and Madison: 1.8V@150mA MPV18)
(Park: 1.8V@75mA MPV18)
PX
C
C8689
SCD1U10V2KX-5GP
2
1
PX
84.03418.031
PX_EN##
R8607
10KR2J-3-GP
SC1U6D3V2KX-GP
2
1
SC4D7U6D3V3KX-GP
2
1
C
84.03418.031
R8604
1KR2J-1-GP
PX
L8604 1
2
BLM15BD121SS1D-GP
C8688
1V_VGA_S0
S
G
PX
84.03400.B37
(1.8V@75mA SPV18)
PX
D
1
CHECK!!
PX_EN
BIF_VDDC_1V
D
3D3V_VGA_S0
3D3V_VGA_S0
SPV18
PX
PX
U8604
AO3418-GP
AO3418-GP
S
2 R8605
55mA in BACO mode
SC1U6D3V2KX-GP
2
1
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
PX U8602
BIF_VDDC
S
G
DY
U8603
AO3400A-GP
D
G
0R3J-0-U-GP 1
S
1
MADISON-PRO-2-GP
PX
SC10U6D3V3MX-GP
2
1
PX
C8639
SC1U6D3V2KX-GP
2
1
TP8602
VGA_SENSE
C8602
SC10U6D3V3MX-GP
2
1
C8647
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
PX
PX
SC1U6D3V2KX-GP
2
1
SPVSS
AF28
PX
SC4D7U6D3V3KX-GP
2
1
PX
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
C8632
SC1U6D3V2KX-GP
2
1
PX
C8679
C8638
SC1U6D3V2KX-GP
2
1
AN10
SCD1U10V2KX-5GP
2
1
SC1U6D3V2KX-GP
2
1
PX
PX
SCD1U10V2KX-5GP
2
1
SPV10
VOLTAGE
SENESE
C8678
PX
3
SPV18
AN9
92
SC4D7U6D3V3KX-GP
2
1
B
C8646
C8637
SC1U6D3V2KX-GP
2
1
AM10
(120mA SPV10)
L8603 1
2
BLM15BD121SS1D-GP
C8631
(GDDR5 1.12V@16A VDDCI)
SPV10
PX
PX
PX
BIF_VDDC
C8677
(For M97, Broadway, Madison and Park SPV10 = 1.0V)
1V_VGA_S0
C8645
C8636
SC1U6D3V2KX-GP
2
1
C8676
MPV18
MPV18
PX
PX
SC1U6D3V2KX-GP
2
1
C8675
PCIE_PVDD
H7
H8
PX
VGA_CORE
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
SC1U6D3V2KX-GP
2
1
PX
SCD1U10V2KX-5GP
2
1
PX
SPV18
C8630
2
PX
VDDR4
VDDR4
VDDR4
VDDR4
PX
G
AD12
AF11
AF12
AG11
C8629
1
VDDR4
VDDR4
VDDR4
VDDR4
PX
2
C8668
(1.8V@40mA PCIE_PVDD)
SC4D7U6D3V3KX-GP
2
1
L8602 1
2
BLM15BD121SS1D-GP
SC1U6D3V2KX-GP
2
1
PX
AF13
AF15
AG13
AG15
PX
C8628
1
PCIE_PVDD
VDDR3
VDDR3
VDDR3
VDDR3
PX
SCD1U10V2KX-5GP
2
1
C8667
1V_VGA_S0
SC1U6D3V2KX-GP
2
1
PX
SCD1U10V2KX-5GP
2
1
C8666
SC1U6D3V2KX-GP
2
1
PX
SC1U6D3V2KX-GP
2
1
C8665
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC4D7U6D3V3KX-GP
2
1
C
PX
C8617
SC10U6D3V3MX-GP
2
1
AF23
AF24
AG23
AG24
PX
SC10U6D3V3MX-GP
2
1
I/O
3D3V_VGA_S0
C8616
SC1U6D3V2KX-GP
2
1
C8654
SC1U6D3V2KX-GP
PX
SC10U6D3V3MX-GP
2
1
PX
VDD_CT
VDD_CT
VDD_CT
VDD_CT
2
2
C8652
SC1U6D3V2KX-GP
1
PX
1
1
2
C8650
SC4D7U6D3V3KX-GP
POWER
PX
AF26
AF27
AG26
AG27
C8615
SC1U6D3V2KX-GP
2
1
LEVEL
TRANSLATION
VDDC_CT
(1.8V@110mA VDD_CT)
L8601 1
2
BLM15BD121SS1D-GP
PX
SC1U6D3V2KX-GP
2
1
1D8V_VGA_S0
PX
C8614
SC1U6D3V2KX-GP
2
1
C8635
PX
SC1U6D3V2KX-GP
2
1
PX
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
CORE
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
SCD1U10V2KX-5GP
2
1
PX
C8627
C8613
(1.0V@1920mA PCIE_VDDC)
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
SC1U6D3V2KX-GP
2
1
C8612
PX
SC1U6D3V2KX-GP
2
1
PX
C8626
SC1U6D3V2KX-GP
2
1
C8611
PX
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
SC1U6D3V2KX-GP
2
1
PX
C8625
PX
SC1U6D3V2KX-GP
2
1
PX
C8624
C8610
SC1U6D3V2KX-GP
2
1
C8609
PX
SC1U6D3V2KX-GP
2
1
PX
C8623
SC1U6D3V2KX-GP
2
1
C8608
PX
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
PX
SC1U6D3V2KX-GP
2
1
PX
C8622
SC1U6D3V2KX-GP
2
1
C8607
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
PX
C8621
SCD1U10V2KX-5GP
2
1
PX
C8620
C8606
PX
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
SCD1U10V2KX-5GP
2
1
C8603
C8605
PX
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
SC1U6D3V2KX-GP
2
1
PX
PX
SCD1U10V2KX-5GP
2
1
PX
C8619
SC1U6D3V2KX-GP
2
1
C8604
SC1U6D3V2KX-GP
2
1
PX
SC10U6D3V3MX-GP
2
1
PX
C8618
SC1U6D3V2KX-GP
2
1
C8601
SC1U6D3V2KX-GP
2
1
PX
SC10U6D3V3MX-GP
2
1
D
SCD1U10V2KX-5GP
2
1
SC1U6D3V2KX-GP
2
1
PCIE
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
84.T3904.C11
2ND = 84.03904.P11
3rd = 84.03904.L06
PX
C8691
PX
C8692
SCD1U10V2KX-5GP
2
1
A
SC1U6D3V2KX-GP
2
1
SC4D7U6D3V3KX-GP
2
1
L8605 1
2
BLM15BD121SS1D-GP
PX
C8664
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_POWER(4/5)
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
86
of
94
5
4
3
1D8V_VGA_S0
1
DPA_VDD18
0831
8 OF 8
VGA1H
DPA_VDD18
C8708
AP20
AP21
1V_VGA_S0
PX SCD1U10V2KX-5GP
R8704
2
0R2J-2-GP
DPA_VDD10
DPA_VDD10
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPD_VDD18
DPD_VDD18
DPB_VDD18
DPB_VDD18
DPD_VDD10
DPD_VDD10
DPB_VDD10
DPB_VDD10
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
1V_VGA_S0
C8719
AP22
AP23
C8720
SCD1U10V2KX-5GP
1
2
0R2J-2-GP
1
PX
AN27
AP27
AP28
AW24
AW26
C8703
PX
D
0831
DPA_VDD18
DPD_VDD18
1V_VGA_S0
C8702
2
AP31
AP32
0831
AP25
AP26
DPA_VDD10
1
PX
PX R8715
(1.0V@110mA DPA_VDD10)
AN17
AP16
AP17
AW14
AW16
(1.8V@130mA DPD_VDD18)
PX
DPC_VDD10
DPC_VDD10
AN24
AP24
DPA_VDD10
AP13
AT13
2
PX
DPA_VDD18
DPA_VDD18
(1.0V@110mA DPC_VDD10)
0831
DPD_VDD18
1
DPC_VDD18
DPC_VDD18
2
2
PX
DP A/B POWER
SC1U6D3V2KX-GP
1
1
C8707
SC1U6D3V2KX-GP
PX
DP C/D POWER
DPD_VDD18
(1.8V@130mA DPA_VDD18)
2
0R2J-2-GP
SCD1U10V2KX-5GP
2
1
R8710
1
SC1U6D3V2KX-GP
2
1
(1.0V@110mA DPD_VDD10)
AP14
AP15
AN19
AP18
AP19
AW20
AW22
0831
R8701 PX
1
2DPCD_CALR AW18
150R2F-1-GP
DPF_VDD18
LVDS mode
DPCD_CALR
DPAB_CALR
(1.0V@110mA DPB_VDD10)
AN33
AP33
AN29
AP29
AP30
AW30
AW32
R8703
AW28DPAB_CALR
1
PX 2
150R2F-1-GP
0831
DPA_VDD18
(1.8V@200mA DPE_VDD18)
(1.8V@20mA DPA_PVDD)
DP PLL POWER
DP E/F POWER
AH34
AJ34
DPE_VDD18
DPE_VDD18
DPA_PVDD
DPA_PVSS
DPE_VDD10
DPE_VDD10
DPB_PVDD
DPB_PVSS
AU28
AV27
DPA_VDD18
LVDS mode
DPF_VDD10
(1.8V@20mA DPB_PVDD)
(1.0V@120mA DPE_VDD10)
AL33
AM33
AV29
AR28
DPD_VDD18
(1.8V@20mA DPC_PVDD)
AN34
AP39
AR39
AU37
PX
1
R8708
2
0R2J-2-GP
PX_EN
86
LVDS mode
AF34
AG34
DPF_VDD18
(1.8V@200mA DPF_VDD18)
DPC_PVDD
DPC_PVSS
PX
PX
R8713
1
2
0R0603-PAD
(1.8V@20mA DPE_PVDD)
1
DPF_PVDD
DPF_PVSS
DPF_VDD10
LVDS mode
(1.0V@120mA DPF_VDD10)
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
AM37
AN38
AL38
AM35
PX
DPF_PVDD_1
DPF_PVSS
1
PX
1
(1.8V@20mA DPF_PVDD)
R8706
2
0R2J-2-GP
R8707
2
0R2J-2-GP
1V_VGA_S0
PX
R8714
1
2
0R0402-PAD
AM39
PX
C8730
2DPEF_CALR
PX_EN is tri-state before internal PWRGOOD
is asserted and PERSTb is de-asserted.
DPF_VDD10
DPF_VDD10
C8726
SCD1U10V2KX-5GP
AF39
AH39
AK39
AL34
AM34
AV19
AR18
DPF_VDD18
DPF_VDD18
DPF_VDD18
AK33
AK34
C
(1.8V@20mA DPD_PVDD)
DPE_PVDD
DPE_PVSS
PX
AU18
AV17
DPD_VDD18
1D8V_VGA_S0
2
PX_EN_R
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPD_PVDD
DPD_PVSS
1
PX
DPEF_CALR
MADISON-PRO-2-GP
PX
R8705
150R2F-1-GP
1
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
SCD1U10V2KX-5GP
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND/PX_EN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
C
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
R8709
2
1
10KR2J-3-GP
D
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
2
6 OF 8
VGA1F
B
For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
VSS_MECH
VSS_MECH
VSS_MECH
A39 VSS_MECH1
AW1 VSS_MECH2
AW39VSS_MECH3
1
1
1
TP8701
TP8702
TP8703
MADISON-PRO-2-GP
PX
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU_DPPWR/GND(5/5)
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
87
of
94
5
4
3
2
1D5V_VGA_S0
1
1D5V_VGA_S0
2
VRAM_ZQ1
243R2F-2-GP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,89
84,89
84,89
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
CKEA0
DQMA2
DQMA0
WTL
84
84
84
W EA0#
CASA0#
RASA0#
DQSL
DQSL#
F3
G3
ODT
K1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
DMU
DML
L3
K3
J3
WE#
CAS#
RAS#
QSAP_2 84
QSAN_2 84
SC1U6D3V2KX-GP
2
1
C8819
WTL WTL
WTL
1
C8821
1
R8802
WTL
2
1
C8820
VRAM1_2_VREF
QSAP_0 84
QSAN_0 84
ODTA0
C8818
SCD1U10V2KX-5GP
2
1
WTL WTL WTL
2
C7
B7
C8816
SC1U6D3V2KX-GP
2
1
DQSU
DQSU#
WTL
1
MDA20
MDA19
MDA23
MDA16
MDA22
MDA17
MDA21
MDA18
C8814
C8817
SCD1U10V2KX-5GP
2
1
D7
C3
C8
C2
A7
A2
B8
A3
WTL
SC1U6D3V2KX-GP
2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
WTL
C8815
SC1U6D3V2KX-GP
2
1
MDA2
MDA7
MDA1
MDA3
MDA6
MDA4
MDA0
MDA5
C8822
SC1U6D3V2KX-GP
2
1
E3
F7
F2
F8
H3
H8
G2
H7
CKE
D3
E7
2
2
WTL
84
84
84
K9
WTL
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFDQ
VREFCA
ZQ
84
CSA0#_0 84
MEM_RST 84,89,90,91
K8
K2
N1
R9
B2
D9
G7
R1
N9
H1
M8
2VRAM_ZQ2 L8
243R2F-2-GP
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,89
84,89
84,89
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
84
84
CLKA0
CLKA0#
J7
K7
CK
CK#
CKE
84
CKEA0
K9
84
84
DQMA1
DQMA3
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS#
84
84
84
W EA0#
CASA0#
RASA0#
H5TQ2G63BFR-12C-GP WTL
2
1
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
GPU_CLKA0_T
C8802
SCD01U16V2KX-3GP
H1
M8
L8
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
R8803
56R2F-1-GP
WTL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VRAM2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
C8823
SCD1U10V2KX-5GP
2
1
1
WTL
A8
A1
C1
C9
D2
E9
F1
H9
H2
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
1
R8804
56R2F-1-GP
B
C8804
CLKA0
CLKA0#
1
84
84
WTL
1 SC1U6D3V2KX-GP
2
1
1
2
1
R8801
SC10U6D3V5KX-1GP
C8801
WTL
WTL
2
C8813
SC1U6D3V2KX-GP
2
1
WTL WTL WTL WTL
VRAM1_2_VREF
C
C8812
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
2
1
1
C8810
K8
K2
N1
R9
B2
D9
G7
R1
N9
MDA[0..31] 84
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
2
WTL WTL WTL
D
C8811
SC1U6D3V2KX-GP
2
C8809
SC1U6D3V2KX-GP
2
1
C8808
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
2
1
C8807
C8806
SCD1U10V2KX-5GP
2
1
VRAM1
MDA[0..31] 84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA29
MDA27
MDA28
MDA31
MDA25
MDA26
MDA30
MDA24
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA13
MDA14
MDA10
MDA15
MDA11
MDA9
MDA8
MDA12
DQSU
DQSU#
C7
B7
QSAP_1 84
QSAN_1 84
DQSL
DQSL#
F3
G3
QSAP_3 84
QSAN_3 84
ODT
K1
ODTA0
CS#
RESET#
L2
T2
CSA0#_0 84
MEM_RST 84,89,90,91
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
D
84
C
H5TQ2G63BFR-12C-GP WTL
72.52G63.00U
B
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
1
1D5V_VGA_S0
R8805
2K1R2F-GP
2
WTL
1
1
VRAM1_2_VREF
C8803
SCD1U10V2KX-5GP
2
R8806
WTL
2K1R2F-GP
2
WTL
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM1,2 (1/4)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
88
of
94
5
4
3
2
1D5V_VGA_S0
1
1D5V_VGA_S0
WTL
VRAM3_4_VREF
1
R8903
C
VREFDQ
VREFCA
ZQ
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,88
84,88
84,88
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
84
CKEA1
K9
84
WTL 84
DQMA5
DQMA4
D3
E7
DMU
DML
W EA1#
CASA1#
RASA1#
L3
K3
J3
WE#
CAS#
RAS#
1
R8907
56R2F-1-GP
R8908
56R2F-1-GP
WTL
84
84
84
2
C8903
SCD01U16V2KX-3GP
1
GPU_CLKA1_T
DQSL
DQSL#
F3
G3
ODT
K1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
C8918
WTL
VRAM3_4_VREF
QSAP_4 84
QSAN_4 84
ODTA1
WTL
WTL WTL WTL WTL
C8916
QSAP_5 84
QSAN_5 84
C8914
SC1U6D3V2KX-GP
2
1
C7
B7
C8915
SC1U6D3V2KX-GP
2
1
DQSU
DQSU#
C8922
SCD1U10V2KX-5GP
2
1
MDA45
MDA43
MDA47
MDA40
MDA44
MDA41
MDA46
MDA42
WTL WTL WTL
C8923
SCD1U10V2KX-5GP
2
1
D7
C3
C8
C2
A7
A2
B8
A3
C8920
SC1U6D3V2KX-GP
2
1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C8921
SC1U6D3V2KX-GP
2
1
MDA35
MDA38
MDA33
MDA37
MDA34
MDA39
MDA32
MDA36
C8917
SCD1U10V2KX-5GP
2
1
E3
F7
F2
F8
H3
H8
G2
H7
CKE
2
2
WTL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
2VRAM_ZQ3 L8
243R2F-2-GP
CLKA1
CLKA1#
1
84
84
WTL
A8
A1
C1
C9
D2
E9
F1
H9
H2
VRAM4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SC10U6D3V5KX-1GP
2
1
C8907
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC10U6D3V5KX-1GP
2
1
1
1
WTL
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C8905
2
WTL WTL WTL WTL WTL
K8
K2
N1
R9
B2
D9
G7
R1
N9
MDA[32..63] 84
C8919
SCD1U10V2KX-5GP
2
1
C8912
SC1U6D3V2KX-GP
2
1
C8913
SC1U6D3V2KX-GP
2
1
C8910
SC1U6D3V2KX-GP
2
1
C8911
SC1U6D3V2KX-GP
2
1
WTL WTL
2
D
C8908
SC1U6D3V2KX-GP
2
1
WTL
C8909
SC1U6D3V2KX-GP
2
1
C8906
SC1U6D3V2KX-GP
2
1
C8902
SC1U6D3V2KX-GP
2
1
VRAM3
1
R8904
WTL
WTL
84
84
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
2VRAM_ZQ4 L8
243R2F-2-GP
VREFDQ
VREFCA
ZQ
84
CSA1#_0 84
MEM_RST 84,88,90,91
K8
K2
N1
R9
B2
D9
G7
R1
N9
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,88
84,88
84,88
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
CKE
CLKA1
CLKA1#
84
CKEA1
K9
84
84
DQMA6
DQMA7
D3
E7
DMU
DML
84
84
84
W EA1#
CASA1#
RASA1#
L3
K3
J3
WE#
CAS#
RAS#
MDA[32..63] 84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA61
MDA60
MDA63
MDA57
MDA59
MDA58
MDA62
MDA56
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA50
MDA55
MDA49
MDA53
MDA48
MDA54
MDA51
MDA52
DQSU
DQSU#
C7
B7
QSAP_6 84
QSAN_6 84
DQSL
DQSL#
F3
G3
QSAP_7 84
QSAN_7 84
ODT
K1
ODTA1
CS#
RESET#
L2
T2
CSA1#_0 84
MEM_RST 84,88,90,91
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
WTL
WTL
D
84
C
B
B
1
1D5V_VGA_S0
R8901
2K1R2F-GP
2
WTL
1
R8902
WTL
2K1R2F-GP
C8901
SCD1U10V2KX-5GP
2
1
VRAM3_4_VREF
2
WTL
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM3,4 (2/4)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
89
of
94
5
4
3
2
1D5V_VGA_S0
1
1D5V_VGA_S0
C9007
PX
VRAM5_6_VREF
1
R9004
C
20090902
VRAM_ZQ5
243R2F-2-GP
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,91
84,91
84,91
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
1
PX 84
84
DQMB3
DQMB1
D3
E7
DMU
DML
84
84
84
W EB0#
CASB0#
RASB0#
L3
K3
J3
WE#
CAS#
RAS#
2
CKEB0
PX
2
R9007
56R2F-1-GP
84
R9008
56R2F-1-GP
K9
1
2
PX
DQSL
DQSL#
F3
G3
ODT
K1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
PX
PX
PX
C9013
PX
QSBP_3 84
QSBN_3 84
PX
C9014
PX
VRAM5_6_VREF
QSBP_1 84
QSBN_1 84
ODTB0
C9020
SCD1U10V2KX-5GP
2
1
C7
B7
PX
C9019
SC1U6D3V2KX-GP
2
1
DQSU
DQSU#
PX
C9017
SC1U6D3V2KX-GP
2
1
MDB26
MDB27
MDB30
MDB24
MDB31
MDB25
MDB29
MDB28
PX
C9018
SC1U6D3V2KX-GP
2
1
D7
C3
C8
C2
A7
A2
B8
A3
CKE
GPU_CLKB0_T
C9003
SCD01U16V2KX-3GP
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
PX
C9016
SCD1U10V2KX-5GP
2
1
VREFDQ
VREFCA
ZQ
MDB14
MDB13
MDB12
MDB15
MDB11
MDB8
MDB9
MDB10
C9015
SC1U6D3V2KX-GP
2
1
H1
M8
L8
E3
F7
F2
F8
H3
H8
G2
H7
C9011
SC1U6D3V2KX-GP
2
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
CLKB0
CLKB0#
1
84
84
2
PX
A8
A1
C1
C9
D2
E9
F1
H9
H2
VRAM6
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SC10U6D3V5KX-1GP
2
1
PX
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC10U6D3V5KX-1GP
2
1
C9005
PX
K8
K2
N1
R9
B2
D9
G7
R1
N9
MDB[0..31] 84
C9012
SC1U6D3V2KX-GP
2
1
PX
SC10U6D3V5KX-1GP
2
1
PX
C9010
SC1U6D3V2KX-GP
2
1
C9023
SC1U6D3V2KX-GP
2
1
C9022
SC1U6D3V2KX-GP
2
1
PX
SC10U6D3V5KX-1GP
2
1
PX
C9021
SC1U6D3V2KX-GP
2
1
PX
C9008
SCD1U10V2KX-5GP
2
1
D
PX
C9009
SC1U6D3V2KX-GP
2
1
PX
C9006
SCD1U10V2KX-5GP
2
1
C9002
SC1U6D3V2KX-GP
2
1
VRAM5
1
R9006
2
PX
VRAM_ZQ6
243R2F-2-GP
84
CSB0#_0 84
MEM_RST 84,88,89,91
84
84
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,91
84,91
84,91
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
CKE
CLKB0
CLKB0#
84
CKEB0
K9
84
84
DQMB0
DQMB2
D3
E7
DMU
DML
84
84
84
W EB0#
CASB0#
RASB0#
L3
K3
J3
WE#
CAS#
RAS#
MDB[0..31] 84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB16
MDB18
MDB20
MDB19
MDB22
MDB17
MDB23
MDB21
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB1
MDB5
MDB2
MDB4
MDB3
MDB7
MDB0
MDB6
DQSU
DQSU#
C7
B7
QSBP_0 84
QSBN_0 84
DQSL
DQSL#
F3
G3
QSBP_2 84
QSBN_2 84
ODT
K1
ODTB0
CS#
RESET#
L2
T2
CSB0#_0 84
MEM_RST 84,88,89,91
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
PX
PX
D
84
C
B
B
1
1D5V_VGA_S0
R9001
2K1R2F-GP
2
PX
1
R9002
2K1R2F-GP
C9001
SCD1U10V2KX-5GP
2
PX
PX
2
1
VRAM5_6_VREF
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM5,6 (3/4)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
90
of
94
5
4
3
2
1D5V_VGA_S0
1
1D5V_VGA_S0
VRAM7_8_VREF
1
R9103
C
VRAM_ZQ7
243R2F-2-GP
VREFDQ
VREFCA
ZQ
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,90
84,90
84,90
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
1
CLKB1
CLKB1#
1
84
84
2
PX
H1
M8
L8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
R9107
56R2F-1-GP
R9108
56R2F-1-GP
2
PX
2
PX
84
CKEB1
84
84
DQMB4
DQMB5
D3
E7
DMU
DML
84
84
84
W EB1#
CASB1#
RASB1#
L3
K3
J3
WE#
CAS#
RAS#
PX
2
C9103
SCD01U16V2KX-3GP
1
GPU_CLKB1_T
B
DQSL
DQSL#
F3
G3
QSBP_5 84
QSBN_5 84
ODT
K1
ODTB1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
PX
PX
C9115
PX
20100712 V1.5
QSBP_4 84
QSBN_4 84
C9123
SCD1U10V2KX-5GP
2
1
C7
B7
PX
C9122
SC1U6D3V2KX-GP
2
1
DQSU
DQSU#
PX
C9121
SC1U6D3V2KX-GP
2
1
MDB36
MDB35
MDB39
MDB32
MDB37
MDB33
MDB38
MDB34
PX
C9120
SC1U6D3V2KX-GP
2
1
D7
C3
C8
C2
A7
A2
B8
A3
PX
C9119
SCD1U10V2KX-5GP
2
1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
PX
C9118
SC1U6D3V2KX-GP
2
1
MDB40
MDB43
MDB47
MDB44
MDB41
MDB45
MDB42
MDB46
C9117
SC1U6D3V2KX-GP
2
1
E3
F7
F2
F8
H3
H8
G2
H7
PX
SC10U6D3V5KX-1GP
2
1
C9106
PX
PX
20100712 V1.5
A8
A1
C1
C9
D2
E9
F1
H9
H2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SC10U6D3V5KX-1GP
2
1
C9105
PX
VRAM8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MDB[32..63] 84
C9114
SC1U6D3V2KX-GP
2
1
PX
SC10U6D3V5KX-1GP
2
1
PX
K8
K2
N1
R9
B2
D9
G7
R1
N9
C9113
SC1U6D3V2KX-GP
2
1
C9112
SC1U6D3V2KX-GP
2
1
C9111
SCD1U10V2KX-5GP
2
1
PX
SC10U6D3V5KX-1GP
2
1
PX
C9110
SCD1U10V2KX-5GP
2
1
PX
C9109
SC1U6D3V2KX-GP
2
1
PX
C9108
SC1U6D3V2KX-GP
2
1
PX
D
C9107
SC1U6D3V2KX-GP
2
1
C9102
SC1U6D3V2KX-GP
2
1
VRAM7
C9116
PX
VRAM7_8_VREF
1
R9104
2
PX
VRAM_ZQ8
243R2F-2-GP
84
CSB1#_0 84
MEM_RST 84,88,89,90
84
84
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
84,90
84,90
84,90
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
CLKB1
CLKB1#
84
CKEB1
K9
CKE
84
84
DQMB7
DQMB6
D3
E7
DMU
DML
84
84
84
W EB1#
CASB1#
RASB1#
L3
K3
J3
WE#
CAS#
RAS#
MDB[32..63] 84
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB53
MDB51
MDB55
MDB49
MDB54
MDB48
MDB52
MDB50
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB61
MDB62
MDB58
MDB59
MDB63
MDB56
MDB57
MDB60
DQSU
DQSU#
C7
B7
QSBP_7 84
QSBN_7 84
DQSL
DQSL#
F3
G3
QSBP_6 84
QSBN_6 84
ODT
K1
ODTB1
CS#
RESET#
L2
T2
CSB1#_0 84
MEM_RST 84,88,89,90
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
H5TQ2G63BFR-12C-GP
H5TQ2G63BFR-12C-GP
72.52G63.00U
72.52G63.00U
2nd = 72.42164.C0U
2nd = 72.42164.C0U
PX
PX
D
84
C
B
1
1D5V_VGA_S0
R9101
2K1R2F-GP
2
PX
20100712 V1.5
1
R9102
2K1R2F-GP
C9101
SCD1U10V2KX-5GP
2
PX
PX
2
1
VRAM7_8_VREF
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM7,8 (4/4)
Size
A3
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
91
of
94
5
4
3
2
1
SSID = PWR.Plane.Regulator_GFX
VGA_CORE
PW R_DCBATOUT_VGA_CORE
PG9201
1
2
PG9206
1
2
GAP-CLOSE-PW R-3-GP
PG9204
1
2
PW R_DCBATOUT_VGA_CORE
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9210
PG9220
1
2
1
2
1
PX
PX
PC9211
SC10U25V5KX-GP
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9211
PG9221
1
2
1
2
2
PC9210
SC10U25V5KX-GP
2
PC9205
SC10U25V5KX-GP
1
1
PX
2
PC9207
SC10U25V5KX-GP
2
1
PX
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9212
PG9222
1
2
1
2
6
5
2
1
D
D
D
D
5V_PW R
2 249KR2F-GP
7
6
2
1
PU9204
IRF6725MTRPBF-GP-U
84.06725.030
PW R_VGA_CORE_VOUT
2
RT8208BGQW -GP
RT8208B:74.08208.A73
3D3V_VGA_S0
1
PX
2 0R2J-2-GP
2
YES
L: 1.00V
H: 0.90V
Park==>R9209=33K (64.33025.6DL)
Madison==>R9209=71.5K (64.71525.6DL)
NVVDD_ALTV1 NVVDD_ALTV0
H
L
PARK XT
+VGA_CORE
6
PX
R9209
33KR2F-GP
GPIO TABLE
GPU VOLTAGE
GPU VOLTAGE
H
H
1.12V or 1V
4
2
PQ9206_3
A
PX
Wistron Corporation
PR9213
10R2J-2-GP
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
0.9V
RT8208B_+VGA_CORE
Size
A3
Date:
5
8209A_EN/DEM_VGA
<Core Design>
OUT=(R9208+R9210)/R9210
L: 1.12V
H: 0.90V
DY
PR9215
100R2J-2-GP
R9211
49K9R2F-L-GP
PX
2
Inter
Pull Low
2nd = 84.DM601.03F
PC9209
R9210
49K9R2F-L-GP
OUT=[R9208+(R9210//R9209)}/(R9210//R9209)
I/O
DY
84.2N702.A3F
DY
DY
1
O
GPIO TABLE
PC9208
B
VGA_CORE_PW R
PWR_VGA_CORE_D1
PX
PC9201
SC1KP50V2KX-1GP
DY
PWR_GND_SENSE_1
NVVDD_ALTV0
2
DY
PWR_VGA_CORE_D0
1
PR9212
0R2J-2-GP
GPU VOLTAGE
GPU VOLTAGE
PW R_VGA_CORE_EN_R#
PQ9201
2N7002KDW -GP
1
PW R_VGA_CORE_FB
PR9207 1
1
86 VGA_SENSE
DGPU_PW ROK 22,93
2
2
R9214
PX 0R0402-PAD
C9212
SC100P50V2JN-3GP
2
1
1
PR9208
10KR2F-2-GP
1
PW R_VGA_CORE_PGOOD
PX
2
C9211
SCD1U10V2KX-5GP
MADSION PRO
Inter
Pull Low
3D3V_AUX_S5
PR9214
100KR2J-1-GP
1
PX
86 GND_SENSE
I/O
PTC9203
2
PX
DY
2
1
DY
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PX
PR9206
10R2J-2-GP
R9213
10KR2J-3-GP
8209A_EN/DEM_VGA 86
CH551H-30GP-GP
Vout=0.75V*(R1+R2)/R2
1
A
PTC9202
DY
2
93 DGPU_PW R_EN
1
2
D9201
PX
PW R_VGA_CORE_VOUT
2
0R0402-PAD
2
1
3D3V_VGA_S0
PX
R9212
10KR2F-2-GP
K
PC9206
PR9202
1
B
TP9201
TPAD40-GP
1
PX
1
1
PG9205
4
VOUT
PX
1
GND
85
2
EM/DEM
17
85
PW RCNTL_1
S
S
G
15
PW RCNTL_0
5
4
3
C9202 86 8209A_EN/DEM_VGA
PW R_VGA_CORE_D1
PW R_VGA_CORE_D0
5
PX
PW R_VGA_CORE_FB
3
7
3
14
5
6
PGOOD
CS
D
D
D
D
PW R_VGA_CORE_PGOOD 4
2PW R_VGA_CORE_CS
10
2 L-D36UH-1-GP
2
G0
FB
G1
D1
D0
PL9201 1
C
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9227
PG9226
1
2
1
2
SE470UF2VDM-GP
2
1
VDD
PX
SE470UF2VDM-GP
2
1
12
11
8
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9215
PG9225
1
2
1
2
VGA_CORE_PWR
SCD1U10V2KX-5GP
2
1
2
PX
SC1U10V2KX-1GP
2
1
BOOT
UGATE
PHASE
LGATE
TON
VDDP
PX
PR9204
PC9203
PW R_VGA_CORE_BOOT1
2PW R_VGA_CORE_BOOT_C 1
2
2R3J-2-GP
PR9201
PW R_VGA_CORE_UGATE
SCD1U25V3KX-GP1
2
PW R_VGA_CORE_PHASE
0R0402-PAD
PW R_VGA_CORE_LGATE
SC10P50V2JN-4GP
2
1
PW R_VGA_CORE_VDD
PX
13
Design Current = 21.94A
24.14A<OCP< 28.53A
1
PU9201
16
9
PR9205
6K34R2F-GP
1
3
4
1
PX
2
R9201
10R2F-L-GP
2
1
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9214
PG9224
1
2
1
2
S
G
PX
C9201
SC1U10V2KX-1GP
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9213
PG9223
1
2
1
2
84.06721.030
SCD1U10V2KX-5GP
2
1
PR9203 1
PU9202
IRF6721SPBF-GP-U
GAP-CLOSE-PWR-3-GP
PW R_VGA_CORE_TON
PX
PX
PX
A
D
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9209
PG9219
1
2
1
2
GAP-CLOSE-PW R-3-GP
C
VGA_CORE
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9208
PG9218
1
2
1
2
GAP-CLOSE-PW R-3-GP
PG9203
1
2
2
D
VGA_CORE_PW R
PG9216
1
2
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG9207
PG9217
1
2
1
2
GAP-CLOSE-PW R-3-GP
PG9202
1
2
1
DCBATOUT
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
92
of
94
5
4
3
2
1
20100629 V1.3
1D5V_VGA_S0
1D5V_VGA_S0
77.C1071.081
2nd = 77.21071.07L
2
PX
D
RUNON_R
1
D9301
K
92 DGPU_PWR_EN
R9306
100KR2J-1-GP
A
CH551H-30GP-GP
3.3V_RUN_VGA_1
Discharge Circuit
R9307
330KR2J-L1-GP
20100805 V1.8
RUNON_R_1
DIS_EN_1D5_RUN
Reserved PD9301 connect DGPU_PWR_EN to
PWR_1D5V_EN for power down sequence.
PX
D
R9308
10KR2F-2-GP
1
2
DIS_EN_1D5_RUN
PX
5V_S5
5V_S5
1
84.2N702.A3F
2nd = 84.DM601.03F
PX
R9305
330KR2J-L1-GP
C9303
SCD1U10V2KX-5GP
2
3
2
2
DY
1
PX
20100629 V1.3
Q9301
2N7002KDW-GP
DIS_EN_1D5_RUN_R
2
PX
2
1
R9304
100R2J-2-GP
PX
2
G
1
4
5
6
PX
1
PX
2
PX
R9303
20KR2F-L-GP
1D5V_VGA_S0
DY
D
DGPU_PWR_EN
2
PX
C9304
SC1U10V3ZY-6GP
2N7002K-2-GP
1
2
3
4
VCC
ON
DIS2
GND
NC#9
PG
G1/G2
S/DIS1
D
9
8
7
6
5
SLG_RUN_ENABLE_VGA
SLG55221-130010VTR-GP
74.55221.0E3
2
S
22,92 DGPU_PWROK
2 10KR2F-2-GP
DIS mode:R9309,R9311 follow Old Sequence
PX_Muxless :R9310,C9308,R9320,C9304 value
need fine tune for BACO sequecne
92
S
PX
R9320 1
22,92 DGPU_PWROK
20100629 V1.3
R9322
0R2J-2-GP
U9304
84.2N702.J31
2nd = 84.2N702.031
2 0R2J-2-GP
G
Q9305
G
DY
9025_PGOOD_1V R9309 1
1
DGPU_PWR_EN
Q9304
2N7002K-2-GP
PX
D
S
S
G
84.02130.031
2ND = 84.03413.A31
1
Q9306
2N7002K-2-GP
84.2N702.J31
2nd = 84.2N702.031
RUNON_R_1
Q9303
NDS0610-G-GP
1
G
1
G
2
DIS_FBVDD
2nd = 79.33719.20D
RUN_ENABLE
PX
Q9302
DMP2130L-7-GP
3.3V_ALW_1
18 DGPU_PWR_EN#
R9321
470R2J-2-GP
D
D
PX
3D3V_S0
77.C3371.10L
PX
RUNON_R_1
S
D
R9302
100KR2J-1-GP
TC9301
ST330U2D5VDM-13GP
D
3D3V_VGA_S0
1
1
PX
TC9302
ST100U6D3VBM-5GP
2
SIR460DP-T1-GE3-GP
PX
C9302
SCD1U16V2KX-3GP
2
2 0R5J-5-GP
PX
2
R9301 1
C9301
SC10U6D3V5KX-1GP
1
2
3
4
2
1
PX
S
S
S
G
1
8
7
6
5
U9301
D
D
D
D
1
PX
PX
3D3V_S0
1D5V_VGA_S0
1D5V_S3
+3VS to 3.3V_DELAY Transfer
84.2N702.J31
2nd = 84.2N702.031
C
C
RT9025 for 1V_VGA
1D5V_S3
PX
1
1
C9306
SC10U6D3V5KX-1GP
C9307
SC1U10V3ZY-6GP
2
2
Reserved PD9302 connect DGPU_PWR_EN to
PWR_1V_EN for power down sequence.
5V_S5
PX
C9305
SC10U6D3V5KX-1GP
2
1
PX
92 DGPU_PWR_EN
DY
D9302
K
Iomax=1.5A
A
1DV_M92_PWR
1V_VGA_S0
CH551H-30GP-GP
R9312
5K1R2F-2-GP
RT9025-25GSP-GP
1
1
9025_FB
PX
R9313
2K2R2J-2-GP
DIS mode:R9309,R9311 follow Old Sequence
PX_Muxless :R9310,C9308,R9320,C9304 value
need fine tune for BACO sequecne
9025_PGOOD_1V
PX
C9309
PX
C9310
PX
1
GAP-CLOSE-PWR
G9302
2
1
C9311
GAP-CLOSE-PWR
G9303
2
1
GAP-CLOSE-PWR
PX
R9314
20KR2F-L-GP
2
B
PX
SC10U6D3V5KX-1GP
2
1
3D3V_VGA_S0
C9308
SCD1U25V3KX-GP
5
6
7
8
SC10U6D3V5KX-1GP
2
1
PX
NC#5
VOUT
ADJ
GND
2
2
R9310
10KR2F-2-GP
VDD
VIN
EN
PGOOD
SC100P50V2JN-3GP
2
1
4
3
2
1
2
PX
2
B
2
1
3D3V_VGA_S0
U9302
2 9025_EN
0R2J-2-GP
1
22,92 DGPU_PWROK
DY
GND
R9311 1
G9301
1
PX
9
20100629 V1.3
Vo=0.8*(1+(R1/R2))
RT9025 for 1D8V_VGA
3D3V_S5
2
1
C9313
SC10U6D3V5KX-1GP
PX
1
20100629 V1.3
C9312
SC10U6D3V5KX-1GP
2
1
5V_S5
PX
DY
C9314
SC1U6D3V2KX-GP
Iomax=1A
OCP>1.35A
2
Reserved PD9303 connect DGPU_PWR_EN to
PWR_1D8V_EN for power down sequence.
DY
1D8V_VGA_S0
D9303
K
G9304
A
2
CH551H-30GP-GP
83 1D8V_S0_VGA_PG
RT9025-25GSP-GP
1
C9316
SC100P50V2JN-3GP
PX
C9317
SC10U6D3V5KX-1GP
DY
GAP-CLOSE-PWR
G9305
2
1
Supplier
Description
Lenovo P/N
Wistron P/N
GAP-CLOSE-PWR
GMT
G9661-25ADJF11U
N/A
74.09661.07D
RICHTEK
RT9025-25GSP
N/A
74.09025.A3D
C9318
SC10U6D3V5KX-1GP
A
2
R9316
18KR2F-GP
DY
2
PX
1
1
GND
5
6
7
8
<Core Design>
9025_ADJ_VGA
PX
R9317
10KR2F-2-GP
PX
Wistron Corporation
R9318
14K3R2F-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
2
PX
1D8V_S0_VGA_PG
NC#5
VOUT
ADJ
GND
1
1
3D3V_VGA_S0
R9319
0R2J-2-GP
1
2
VDD
VIN
EN
PGOOD
2
C9315
SCD1U10V2KX-5GP
A
4
3
2
1
Vo(cal.)=1.8069V
2
DY
1
PX
R9315
0R2J-2-GP
Table 93.1- Adjustable LDO Regulator multi-source
1D8V_LDO_VGA
PX
U9303
9025_EN_VGA
2
1
2
1
9
9025_PGOOD_1V
1
92 DGPU_PWR_EN
9025_PGOOD_VGA
Title
DISCRETE VGA POWER
Vo=0.8*((R1+R2)/R2)
Size
C
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
Sheet
1
93
of
94
5
4
CPU
ZZ.SCREW.091
1
ZZ.SCREW.091
ZZ.SCREW.091
1
H6
HOLET157B276R134-GP
1
H5
HOLET157B276R134-GP
1
H4
HOLET157B276R134-GP
1
ZZ.SCREW.091
2
VGA
H3
HOLET157B276R134-GP
1
H2
HOLET157B276R134-GP
1
H1
HOLET157B276R134-GP
3
ZZ.SCREW.091
ZZ.SCREW.091
D
D
H9
HT85X105B85R26-S-GP
H10
HT85X105B85R26-S-GP
H11
HOLE237R95-GP
H12
HOLE237R95-GP
H13
HT6BE75R24-U-45-GP
ZZ.00PAD.921
H17
STF256R117H221-GP
ZZ.00PAD.921
ZZ.00PAD.921
H18
HOLE315R95-GP
H19
HOLE315R95-GP
H20
HOLE315R95-GP
ZZ.00PAD.911
H25
GNDPADSR197
ZZ.00PAD.911
1
LGG Use
ZZ.00PAD.911
H26
GNDPADSR197
H27
HT85X105B85R26-S-GP
H28
HT6BE75R24-U-45-GP
ZZ.NDPAD.XXX
KN1.PAD.01
ZZ.NDPAD.XXX
H31
HOLE237R95-GP
ZZ.NDPAD.XXX
1
1
1
1
1
H30
HOLE315R95-GP
1
H24
GNDPADSR197
1
34.4B804.001
H23
GNDPADSR197
1
1
34.4B804.001
1
34.4C408.001
H22
HOLE197R67X146
1
H21
HOLE197R67X146
1
ZZ.00PAD.921
ZZ.00PAD.971
1
H16
STF256R117H221-GP
1
1
ZZ.SCREW.191
1
H15
STF217R113H119-GP
H14
HOLE237R95-GP
ZZ.SCREW.191
1
1
1
1
1
1
H8
HOLE237R95-GP
ZZ.NDPAD.XXX
KN1.PAD.01
ZZ.SCREW.191
ZZ.00PAD.971
ZZ.00PAD.911
ZZ.00PAD.921
C
C
EMI CAP
1
EC9718
SCD1U25V2ZY-1GP
2
1
EC9717
SCD1U25V2ZY-1GP
2
1
2
1
EC9722
SCD1U25V2ZY-1GP
1
EC9728
SCD1U25V2ZY-1GP
B
2
1
EC9727
SCD1U25V2ZY-1GP
2
1
EC9726
SCD1U25V2ZY-1GP
2
1
EC9725
SCD1U25V2ZY-1GP
2
1
EC9724
SCD1U25V2ZY-1GP
2
1
EC9723
SCD1U25V2ZY-1GP
2
1
2
1
EC9714
SCD1U25V2ZY-1GP
1
EC9744
SCD1U25V2ZY-1GP
EC9745
SCD1U25V2ZY-1GP
2
1
EC9743
SCD1U25V2ZY-1GP
2
1
EC9742
SCD1U25V2ZY-1GP
2
1
EC9741
SCD1U25V2ZY-1GP
2
1
EC9740
SCD1U25V2ZY-1GP
2
1
EC9739
SCD1U25V2ZY-1GP
2
1
EC9738
SCD1U25V2ZY-1GP
2
1
EC9737
SCD1U25V2ZY-1GP
2
1
EC9736
SCD1U25V2ZY-1GP
2
1
EC9735
SCD1U25V2ZY-1GP
2
1
EC9734
SCD1U25V2ZY-1GP
2
1
EC9733
SCD1U25V2ZY-1GP
2
1
EC9732
SCD1U25V2ZY-1GP
2
1
EC9731
SCD1U25V2ZY-1GP
2
1
EC9730
SCD1U25V2ZY-1GP
2
1
EC9729
SCD1U25V2ZY-1GP
2
1
EC9716
SCD1U25V2ZY-1GP
2
1
5V_S0
2
1
2
EC9713
SCD1U25V2ZY-1GP
2
1
EC9720
SCD1U25V2ZY-1GP
2
1
EC9719
SCD1U25V2ZY-1GP
5V_S5
EC9715
SCD1U25V2ZY-1GP
EC9721
SCD1U25V2ZY-1GP
2
1
EC9712
SCD1U25V2ZY-1GP
1D5V_S0
2
1
EC9711
SCD1U25V2ZY-1GP
2
1
EC9707
SCD1U25V2ZY-1GP
2
1
EC9706
SCD1U25V2ZY-1GP
2
1
EC9705
SCD1U25V2ZY-1GP
1D8V_S0
2
1
EC9710
SCD1U25V2ZY-1GP
2
1
EC9709
SCD1U25V2ZY-1GP
1D5V_VGA_S0
2
EC9704
SCD1U25V2ZY-1GP
2
1
3D3V_S5
B
EC9708
SCD1U25V2ZY-1GP
2
1
EC9703
SCD1U25V2ZY-1GP
1D05V_VTT
2
1
EC9702
SCD1U25V2ZY-1GP
2
1
3D3V_S0
2
EC9701
SCD1U25V2ZY-1GP
2
1
DCBATOUT
1
EC9750
SCD1U25V2ZY-1GP
EC9751
SCD1U25V2ZY-1GP
2
1
EC9749
SCD1U25V2ZY-1GP
2
1
EC9748
SCD1U25V2ZY-1GP
2
1
EC9747
SCD1U25V2ZY-1GP
2
1
EC9746
SCD1U25V2ZY-1GP
2
2
1
1D5V_S3
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
UNUSED PARTS/EMI Capacitors
Size
A2
Date:
5
4
3
2
Document Number
Rev
SB
LLW-1 / LGG-1
Tuesday, November 09, 2010
1
Sheet
94
of
94