Uniprocessor View
• Performance depends heavily on
memory hierarchy
CS 258
Parallel Computer Architecture
Lecture 13
– Managed by hardware
– Sizes varied to optimize speed/locality
• Time spent by a program
Shared Memory Multiprocessors
– Timeprog(1) = Busy(1) + Data Access(1)
– Divide by cycles to get CPI equation
P
• Data access time can be reduced
100
by:
–
–
Optimizing machine
» bigger caches, lower latency...
Optimizing program
» temporal and spatial locality
Data-local
Busy-useful
75
Time (s)
March 10, 2008
Prof John D. Kubiatowicz
http://www.cs.berkeley.edu/~kubitron/cs258
50
25
3/10/08
Same Processor-Centric Perspective
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.2
What is a Multiprocessor?
• A collection of communicating processors
100
100
Data-remote
75
– Goals: balance load, reduce inherent communication and extra work
Synchronization
Busy-overhead
75
Data-local
Busy-useful
50
Time (s)
Time (s)
P
25
P
...
• A multi-cache, multi-memory system
50
– Role of these components essential regardless of programming model
– Prog. model and comm. abstr. affect specific performance tradeoffs
25
P
(a) Sequential
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P
0
P1
P
2
P
3
...
(b) Parallel with four processors
Kubiatowicz CS258 ©UCB Spring 2008
P
Lec 13.3
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P
P
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.4
Relationship between Perspectives
Parallelization step(s)
Artifactual Communication
Pr ocessor time component
Performance issue
Decomposition/
assignment/
or chestration
Load imbalance and
synchr onization
Decomposition/
assignment
Extra work
Busy-overhead
Decomposition/
assignment
Inher ent
communication
volume
Data-r emote
Or chestration
Artifactual
communication
and data locality
Data-local
Or chestration/
mapping
Communication
structur e
Synch wait
– This can either be fundamental to computation or “overhead”
• Inherent Communication: Fundamental
Busy(1) + Data(1)
Speedup <
Busyuseful(p)+Datalocal(p)+Synch(p)+Dataremote(p)+Busyoverhead(p)
3/10/08
• Accesses not satisfied in local portion of memory
hierarchy cause “communication”
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.5
Back to Basics
– Required part of computation
– implicit or explicit
» determined by program
– Inherent communication is what occurs with unlimited capacity,
small transfers, and perfect knowledge of what is needed.
• Artifactual communication
–
–
–
–
–
–
determined by program implementation and arch. interactions
poor allocation of data across distributed memories
unnecessary data in a transfer
unnecessary transfers due to system granularities
redundant communication of data
finite replication capacity (in cache or main memory)
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.6
Natural Extensions of Memory System
• Parallel Architecture =
Computer Architecture +Communication Architecture
• Small-scale shared memory
Pn
P1
Scale
Switch
(Interleaved)
First-level $
– extend the memory system to support multiple processors
– good for multiprogramming throughput and parallel computing
– allows fine-grain sharing of resources
(Interleaved)
Main memory
• Naming & Synchronization
P1
Pn
$
$
Interconnection network
– communication is implicit in store/load of shared address
– synchronization is performed by operations on shared addresses
Shared Cache
• Latency & Bandwidth
Mem
Mem
Centralized Memory
Dance Hall, UMA
– utilize the normal migration within the storage to avoid long
latency operations and to reduce bandwidth
– economical medium with fundamental BW limit
⇒ focus on eliminating unnecessary traffic
Pn
P1
Mem
$
Mem
$
Interconnection network
Distributed Memory (NUMA)
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.7
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.8
Caches are Critical for Performance
Bus-Based Symmetric Shared Memory
• Reduce average latency
– automatic replication closer to processor
Pn
P1
• Reduce average bandwidth usage
$
$
– Accesses satisfied by cache
Bus
• Much “simpler” to share data
among processors
I/O devices
Mem
• Dominate the server market even now
– Just pass a pointer
– Building blocks for larger systems; arriving to desktop
Fine-grain resource sharing
Uniform access via loads/stores
Automatic data movement and coherent replication in caches
Cheap and powerful extension
• Question: what actually happens when loads and
stores executed on different processors?
– Key is extension of memory hierarchy to support multiple processors
Kubiatowicz CS258 ©UCB Spring 2008
P
– store reg --> mem
– load reg <-- mem
• Normal uniprocessor mechanisms to access data
3/10/08
P
• Data is logically transferred
from producer to consumer through memory
• Attractive as throughput servers and for parallel programs
–
–
–
–
P
– Issues of Coherence and Consistency arise
Lec 13.9
Example Cache Coherence Problem
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.10
Caches and Cache Coherence
• Caches play key role in all cases
P2
P1
u=?
$
3
u= ?
4
$
– Reduce average data access time
– Reduce bandwidth demands placed on shared interconnect
P3
5
• private processor caches create a problem
$
u :5 u= 7
u :5
– Copies of a variable can be present in multiple caches
– A write by one processor may not become visible to others
» They’ll keep accessing stale value in their caches
⇒ Cache coherence problem
I/O devices
1
u:5
• What do we do about it?
2
– Organize the mem hierarchy to make it go away
– Detect and take actions to eliminate the problem
Memory
• Things to note:
– Processors see different values for u after event 3
– With write back caches, value written back to memory depends on
happenstance of which cache flushes or writes back value when
» Processes accessing main memory may see very stale value
– Unacceptable to programs, and frequent!
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.11
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.12
Advantages
Disadvantages
• Cache placement identical to single cache
• Fundamental BW limitation
• Increases latency of all accesses
– only one copy of any cached block
• fine-grain sharing
– communication latency determined level in the storage hierarchy
where the access paths meet
» 2-10 cycles
P1
Pn
Switch
» Cray Xmp has shared registers!
• Potential for positive interference
– one proc prefetches data for another
• Smaller total storage
P1
Pn
Switch
– X-bar
– Larger cache
– L1 hit time determines proc. cycle time !!!
(Interleaved)
Cache
• Potential for negative interference
(Interleaved)
Main Memory
– one proc flushes data needed by another
(Interleaved)
Cache
• Many L2 caches are shared today
(Interleaved)
Main Memory
– only one copy of code/data used by both proc.
• Can share data within a line without “ping-pong”
– long lines without false sharing
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.13
Intuitive Memory Model
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.14
Snoopy Cache-Coherence Protocols
P
State
Address
Data
L1
100:67
Pn
P1
Bus snoop
$
$
L2
100:35
Mem
Memory
Disk
– relevant transaction if for a block it contains
– take action to ensure coherence
» invalidate, update, or supply value
– depends on state of the block and the protocol
– except for I/O
• Cache coherence problem in MPs is more pervasive
and more performance critical
Kubiatowicz CS258 ©UCB Spring 2008
Cache-memory
transaction
• Bus is a broadcast medium & Caches know what
they have
• Cache Controller “snoops” all transactions on
the shared bus
100:34
• Reading an address should return the last value
written to that address
• Easy in uniprocessors
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I/O devices
Lec 13.15
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.16
Example: Write-thru Invalidate
Architectural Building Blocks
• Bus Transactions
P2
P1
u=?
$
4
$
– fundamental system design abstraction
– single set of wires connect several devices
– bus protocol: arbitration, command/addr, data
=> Every device observes every transaction
P3
3
u=?
5
$
u :5 u= 7
u :5
• Cache block state transition diagram
– FSM specifying how disposition of block changes
» invalid, valid, dirty
I/O devices
1
u:5
2
Memory
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.17
Design Choices
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Kubiatowicz CS258 ©UCB Spring 2008
Write-through Invalidate Protocol
• Basic Bus-Based Protocol
• Controller updates state of
blocks in response to processor
and snoop events and generates
bus transactions
• Snoopy protocol
– Each processor has cache, state
– All transactions over bus snooped
Processor
– set of states
– state-transition diagram
– actions
Lec 13.18
Ld/St
• Writes invalidate all other
caches
Cache Controller
State Tag Data
– can have multiple simultaneous readers
of block,but write invalidates them
°°°
State Tag Data
Pn
P1
$
Bus
– as in uniprocessor
– state of a block is a p-vector of states
– Hardware state bits associated with
blocks that are in the cache
– other blocks can be seen as being in
invalid (not-present) state in that cache
• Basic Choices
– Write-through vs Write-back
– Invalidate vs. Update
$
I/O devices
Mem
• Two states per block in each
cache
Snoop
State Tag Data
PrRd/ -PrWr / BusWr
V
BusWr / -
PrRd / BusRd
I
PrWr / BusWr
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.19
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.20
Write-through vs. Write-back
Invalidate vs. Update
• Basic question of program behavior:
• Write-through protocol is simple
– Is a block written by one processor later read by others
before it is overwritten?
– every write is observable
• Every write goes on the bus
• Invalidate.
⇒ Only one write can take place at a time in any processor
– yes: readers will take a miss
– no: multiple writes without addition traffic
» also clears out copies that will never be used again
• Uses a lot of bandwidth!
Example: 200 MHz dual issue, CPI = 1,
15% stores of 8 bytes
⇒ 30 M stores per second per processor
⇒ 240 MB/s per processor
State Tag Data
• Update.
– yes: avoids misses on later references
– no: multiple useless updates
» even to pack rats
Pn
P1
$
1GB/s bus can support only about
4 processors without saturating
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State Tag Data
$
Bus
Mem
I/O devices
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.21
Intuitive Memory Model???
⇒Need to look at program reference patterns and
hardware complexity
⇒Can we tune this automatically????
but first - correctness
3/10/08
Lec 13.22
Coherence?
• Caches are supposed to be transparent
• What would happen if there were no caches
• Every memory operation would go “to the memory
location”
P
L1
100:67
L2
– may have multiple memory banks
– all operations on a particular location would be serialized
» all would see THE order
100:35
Memory
Disk
Kubiatowicz CS258 ©UCB Spring 2008
100:34
• Interleaving among accesses from different
processors
• Reading an address should return the last value
written to that address
• What does that mean in a multiprocessor?
– within individual processor => program order
– across processors => only constrained by explicit
synchronization
• Processor only observes state of memory system
by issuing memory operations!
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.23
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.24
Definitions
Is 2-state Protocol Coherent?
• Memory operation
• Assume bus transactions and memory operations
are atomic, one-level cache
– load, store, read-modify-write
• Issues
– all phases of one bus transaction complete before next one
starts
– processor waits for memory operation to complete before
issuing next
– with one-level cache, assume invalidations applied during bus
xaction
– leaves processor’s internal environment and is presented to the
memory subsystem (caches, buffers, busses,dram, etc)
• Performed with respect to a processor
– write: subsequent reads return the value
– read: subsequent writes cannot affect the value
• All writes go to bus + atomicity
• Coherent Memory System
– there exists a serial order of mem operations on each location
s. t.
» operations issued by a process appear in order issued
» value returned by each read is that written by previous
write in the serial order
=> write propagation + write serialization
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.25
– Writes serialized by order in which they appear on bus (bus
order)
⇒ invalidations applied to caches in bus order
• How to insert reads in this order?
– Important since processors see writes through reads, so
determines whether write serialization is satisfied
– But read hits may happen independently and do not appear on
bus or enter directly in bus order
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Ordering Reads
Determining Orders More Generally
• Read misses
• mem op M2 is subsequent to mem op M1
(M1⇒M2) if
– appear on bus, and will “see” last write in bus order
• Read hits: do not appear on bus
Lec 13.26
– the operations are issued by the same processor and
– M2 follows M1 in program order.
– But value read was placed in cache by either
» most recent write by this processor, or
» most recent read miss by this processor
– Both these transactions appeared on the bus
– So reads hits also see values as produced bus order
• write W ⇒ read R if
– read generates bus xaction that follows that for W.
• read or write M ⇒ write W if
– M generates bus xaction and the xaction for W follows that
for M.
• read R ⇒ write W if
– read R does not generate a bus xaction and
– is not already separated from write W by another bus xaction.
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.27
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.28
Ordering
Write-Through vs Write-Back
• Write-thru requires high bandwidth
P0:
R
P1:
R
P2:
R
R
R
R
R
W
R
R
R
R
• Write-back caches absorb most writes as cache
hits
⇒ Write hits don’t go on bus
R
R
W
R
R
– But now how do we ensure write propagation and serialization?
– Need more sophisticated protocols: large design space
R
• But first, let’s understand other ordering issues
•
•
Writes establish a partial order
Doesn’t constrain ordering of reads, though bus will
order read misses too
–
3/10/08
any order among reads between writes is fine, as long as in
program order
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.29
Setup for Mem. Consistency
3/10/08
Lec 13.30
Example
• Coherence ⇒ Writes to a location become
visible to all in the same order
• But when does a write become visible?
P1
P2
/*Assume initial value of A and ag is 0*/
A = 1;
while (flag == 0); /*spin idly*/
flag = 1;
•
How do we establish orders between a write and
a read by different procs?
–
typically use more than one location!
–
Kubiatowicz CS258 ©UCB Spring 2008
use event synchronization
print A;
• Intuition not guaranteed by coherence
• expect memory to respect order between accesses
to different locations issued by a given process
– to preserve orders among accesses to same location by
different processes
• Coherence is not enough!
– pertains only to single location
Conceptual
Picture
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.31
3/10/08
Pn
P1
Kubiatowicz CS258 ©UCB Spring 2008
Mem
Lec 13.32
Another Example of Ordering?
P1
Memory Consistency Model
• Specifies constraints on the order in which memory
operations (from any process) can appear to execute
with respect to one another
P2
/*Assume initial values of A and B are 0 */
(1a) A = 1;
(2a) print B;
(1b) B = 2;
(2b) print A;
– What orders are preserved?
– Given a load, constrains the possible values returned by it
• What’s the intuition?
– Whatever it is, we need an ordering model for clear semantics
» across different locations as well
» so programmers can reason about what results are possible
– This is the memory consistency model
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.33
Sequential Consistency
Processors
P1
issuing memory
references as
per pr ogram or der
• Without it, can’t tell much about an SAS program’s
execution
• Implications for both programmer and system
designer
– Programmer uses to reason about correctness and possible results
– System designer can use to constrain how much accesses can be
reordered by compiler or hardware
• Contract between programmer and system
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.34
What Really is Program Order?
P2
• Intuitively, order in which operations appear in
source code
Pn
– Straightforward translation of source code to assembly
– At most one memory operation per instruction
The “switch” is randomly
set after each memory
reference
• But not the same as order presented to hardware
by compiler
• So which is program order?
Memory
• $ Total order achieved by interleaving accesses
from different processes
– Depends on which layer, and who’s doing the reasoning
– We assume order as seen by programmer
– Maintains program order, and memory operations, from all
processes, appear to [issue, execute, complete] atomically w.r.t.
others
– as if there were no caches, and a single memory
• “A multiprocessor is sequentially consistent if the result of
any execution is the same as if the operations of all the
processors were executed in some sequential order, and the
operations of each individual processor appear in this
sequence in the order specified by its program.”
[Lamport, 1979]
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.35
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.36
SC Example
Implementing SC
• Two kinds of requirements
P2
P1
– Program order
» memory operations issued by a process must appear to
execute (become visible to others and itself) in program
order
– Atomicity
» in the overall hypothetical total order, one memory operation
should appear to complete with respect to all processes
before the next one is issued
» guarantees that total order is consistent across processes
– tricky part is making writes atomic
/*Assume initial values of A and B are 0*/
(1a) A = 1;
(2a) print B;
(1b) B = 2;
A=0 (2b) print A;
B=2
• What matters is order in which operations appear to execute, not
the chronological order of events
• Possible outcomes for (A,B): (0,0), (1,0), (1,2)
• What about (0,2) ?
– program order ⇒ 1a->1b and 2a->2b
– A = 0 implies 2b->1a, which implies 2a->1b
– B = 2 implies 1b->2a, which leads to a contradiction (cycle!)
• Since there is a cycle⇒no sequential order that is consistent!
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.37
Sequential Consistency
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Happens Before: arrows are time
• Memory operations from a proc become visible
(to itself and others) in program order
• There exist a total order, consistent with this partial
order - i.e., an interleaving
– the position at which a write occurs in the hypothetical total order
should be the same with respect to all processors
• How can compilers violate SC?
– Architectural enhancements?
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.39
P0:
R
P1:
R
P2:
R
R
R
R
R
W
R
R
R
R
R
R
W
R
R
R
•
Tricky part is relationship between nodes with
respect to single location
•
Easy topological sort comes up with sequential
ordering assuming:
•
3/10/08
Lec 13.38
3/10/08
–
Program order adds relationship between locations
–
–
All happens-before relationships are time
Then – can’t have time cycles (at least not inside classical
machine in normal spacetime ☺).
Unfortunately, writes are not instantaneous
–
What do we do?
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.40
Ordering: Scheurich and Dubois
Write-back Caches (Uniprocessor)
• 2 processor operations
PrRd/—
PrWr/—
– PrRd, PrWr
P0:
R
P1:
R
P2:
R
R
R
R
• 3 states
R
W
R
R
Exclusion Zone
– invalid, valid (clean), modified (dirty)
– ownership: who supplies block
R
R
R
PrW
• 2 bus transactions:
R
“Instantaneous” Completion point
– every process issues mem operations in program order
– after a write operation is issued, the issuing process waits
for the write to complete before issuing next memory
operation
– after a read is issued, the issuing process waits for the read
to complete and for the write whose value is being returned
to complete (gloabaly) before issuing its next operation
Kubiatowicz CS258 ©UCB Spring 2008
V
– read (BusRd), write-back (BusWB)
– only cache-block transfers
⇒ treat Valid as “shared” and
Modified as “exclusive”
⇒ introduce one new bus
transaction
• Sufficient Conditions
3/10/08
M
Replace/BusWB
Replace/-
PrRd/BusRd
PrRd/—
BusRd/—
PrWr/BusRd
I
– read-exclusive: read for purpose of
modifying (read-to-own)
Lec 13.41
MSI Invalidate Protocol
3/10/08
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.42
Example: Write-Back Protocol
• Three States:
PrRd/—
– “M”: “Modified”
– “S”: “Shared”
– “I”: “Invalid”
PrWr/—
PrRd U
P0
PrRd U
P1
U S
5
U S
7
P4
PrRd U
PrWr U 7
M
• Read obtains block in “shared”
– even if only cache copy
• Obtain exclusive ownership
before writing
– BusRdx causes others to invalidate
(demote)
– If M in another cache, will flush
– BusRdx even if hit in S
» promote to M (upgrade)
PrWr/BusRdX
BusRd/Flush
U S
M
7
5
PrWr/BusRdX
S
BusRd U
BusRdX/Flush
BusRdx U
PrRd/BusRd
• What about replacement?
I/O devices
BusRd U
BusRdX/—
PrRd/—
BusRd/—
BusRd
u:57
Memory
Flush
I
– S->I, M->I as before
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.43
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.44
Correctness
Write Serialization for Coherence
• When is write miss performed?
• Writes that appear on the bus (BusRdX) are
ordered by bus
– How does writer “observe” write?
– How is it “made visible” to others?
– How do they “observe” the write?
– performed in writer’s cache before other transactions, so
ordered same w.r.t. all processors (incl. writer)
– Read misses also ordered wrt these
• When is write hit made visible?
• Write that don’t appear on the bus:
– P issues BusRdX B.
– further mem operations on B until next transaction are from P
» read and write hits
» these are in program order
– for read or write from another processor
» separated by intervening bus transaction
• Reads hits?
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.45
Sequential Consistency
3/10/08
• Sufficient Conditions
– issued in program order
– after write issues, the issuing process waits for the write to
complete before issuing next memory operation
– after read is issues, the issuing process waits for the read to
complete and for the write whose value is being returned to
complete (globally) before issuing its next operation
– Mj subsequent to Mi if
» (I) follows in program order on same processor,
» (ii) Mj generates bus xaction that follows the memory
operation for Mi
• In segment between two bus transactions, any
interleaving of local program orders leads to
consistent total order
• w/i segment writes observed by proc P serialized as:
• Write completion
– can detect when write appears on bus
• Write atomicity:
– if a read returns the value of a write, that write has already
become visible to all others already
– Writes from other processors by the previous bus xaction P issued
– Writes from P by program order
Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.46
Sufficient conditions
• Bus imposes total order on bus xactions for all
locations
• Between xactions, procs perform reads/writes
(locally) in program order
• So any execution defines a natural partial order
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.47
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.48
Summary
• Shared-memory machine
– All communication is implicit, through loads and stores
– Parallelism introduces a bunch of overheads over uniprocessor
• Memory Coherence:
– Writes to a given location eventually propagated
– Writes to a given location seen in same order by everyone
• Memory Consistency:
– Constraints on ordering between processors and locations
• Sequential Consistency:
– For every parallel execution, there exists a serial interleaving
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Kubiatowicz CS258 ©UCB Spring 2008
Lec 13.49