COMPUTER ENGINEERING PROGRAM
California Polytechnic State University
CPE 169
Experiment 5
Introduction to the Logic Analyzer and the Xilinx Design Methodology
Learning Objectives
1.
Digital Systems Design
 To develop an understanding of the basic function and operation of the Logic Analyzer
2.
Xilinx Design Methodology
 To learn the basic approach to designing and implementing circuits on a programmable logic
device.
 To learn to implement digital circuits using VHDL dataflow modeling
Introduction and Overview
You should be able to recall from Experiment 3 that the implementation of a simple function using SSI
logic and discrete gates was both tedious and error prone. These undesirable factors grow exponentially as
the circuit you’re implementing becomes more complex. Implementing circuits on a programmable logic
device provides a solution to this dilemma. The down-sides of this approach is that you’ll need to learn a
language that is used to describe digital circuits (VHDL) and you’ll need to become familiar with the
approach used to transfer the circuit from a description form to the actual hardware (Xilinx Design
Methodology). The good news is that you’ll be directly using what you learn in this experiment in each of
the remaining experiments in CPE 169 as well as other classes and laboratories that follow.
As an added feature in this experiment, you’ll also be learning about the basic operation of the Logic
Analyzer (LA). The LA is primarily a tool that allows for the testing and verification of digital circuits. The
circuits you’ve been working with so far in CPE 169 have been relatively simple. This will gradually
change as you become more familiar with VHDL and the Xilinx Design Methodology. Developing skills in
these areas allows you to design more complicated and thus, more useful circuits. And as your circuits
become more complicated, they will more likely need some type of debugging help from instruments such
as the Logic Analyzer.
This experiment uses the LA to analyze the output of a digital circuit. This circuit is presented as a blackbox where the only thing that is known about the circuit is the number of inputs and outputs. The
relationship between the inputs and outputs is derived with help from the LA. Once this input/output
relationship is established, a circuit that contains the same functionality is designed and generated using the
Xilinx Design Methodology. Testing of the final circuit is done by using the input and output devices on a
development board.
The Logic Analyzer
The Logic Analyzer is a useful tool which aids in the debugging of digital circuits. Recall, the B2 Spice
A/D Lite software was used to simulate a circuit (meaning the circuit does not need to be implemented), but
the LA is used to test the functioning of an implemented, physical circuit. While the simulation relies on
the models of circuit devices, the LA tests the actual devices in a circuit setting.
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Experiment 5 (Xilinx 13.2)
An overview of the theory behind the LA is found in the document entitled An Intuitive Description of the
Logic Analyzer which can be found on the CPE-169 website. You should read this document before
proceeding with this experiment. Some of details of how the LA is used can be found in the procedure
portion of this and other experiments; but having an intuitive feel for the device will help you understand
the big picture. The LA operates in two modes: timing mode and state mode. For this experiment, you’ll
only be using the timing mode.
The Xilinx Design Methodology
Although the term “Xilinx Design Methodology” sounds somewhat intimidating, the working definition is
rather simple. This term refers to the steps required to model, simulate, and implement a digital circuit
using the Xilinx ISE software. Your design is specified using VHDL, simulated using the ModelSim XE
simulator, and downloaded onto the FPGA on the development board using the Digilent ExPort software.
Each of these steps is described in greater detail later in this experiment. Figure 1 shows a block diagram
and brief description of the Xilinx design flow (another name for the Xilinx Design Methodology). Read
over the steps in the design flow and try to get a feel for the approach. Keep in mind that you’re essentially
using Xilinx ISE software to describe and implement a circuit such as the one you spent so much time
wiring in Experiment 2.
1) VHDL source code is used to generate a description of your circuit design.
2) The VHDL source code generated in step 1) is translated into a form which
can be used by other software used in the design flow.
3) The Test Bench Waveform software is used to generate signals which are
used to verify proper circuit operation in the ModelSim XE simulator.
4) The circuit inputs and outputs are internally “mapped” to FPGA pins which
are externally hardwired to input and output devices on the development
board.
5) The circuit design is downloaded into the FPGA.
6) Proper operation of the circuit is verified.
Figure 1: The Xilinx Design Methodology.
VHDL Overview
VHDL is an acronym for Very high speed integrated circuit Hardware Description Language. As the
name implies, VHDL provides a language that can be used to describe digital circuits. This description can
then be used to generate simulations of the circuit as well as the actual circuit on the FPGA. Like most
computer-type languages, VHDL is relatively easy to use for simple applications. On the other hand,
VHDL can also be used to design large and complicated circuits.
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CPE 169
Experiment 5 (Xilinx 13.2)
For this experiment, you’ll be designing a relatively simple circuit which fits in nicely with the fact that this
is most likely your first experience with VHDL. Remember, the bigger point to the experiment lies with the
use of the Logic Analyzer and traversal of the Xilinx Design Methodology. The more you know about
VHDL, the better off you’ll be in this and subsequent digital courses. If you take every opportunity to
approach VHDL with an open and inquisitive mind, you’ll no doubt be awed by its descriptive powers.
Procedures
Procedure Overview: The procedure in this experiment can be divided into the two sections listed below.
This experiment represents your first dealing with both the LA and the Xilinx software. Although both of
these items will soon become second nature to you, working with new tools is always somewhat
challenging.
1) Use the Logic Analyzer to analyze the outputs of a given "mystery" circuit.
2) Implement a circuit that has the same functionality as the given circuit using VHDL and the Xilinx
Design Methodology.
Procedure 1: Black-box Analysis Using the Logic Analyzer
In this procedure, you be using the Logic Analyzer to display and analyze the output of a digital circuit.
The black-box diagram of the circuit shown in Figure 2 indicates the number and names of circuit inputs
and outputs. This information represents all you know about the circuit. The A, B, C, D inputs are used to
step through all the possible combinations of the input variables. These inputs are also available as outputs
which will enable you to analyze the two listed output functions. The labels listed in parenthesis are the
signal names on the development board.
Figure 2: Black-box diagram from provided circuit
Refer to the reference guide for the particular Logic Analyzer at your lab station for instructions on how to
connect and configure the Logic Analyzer to display the signals from your development board.
PROCEDURES
1. Apply power to the Logic Analyzer.
2. Connect the development board to the Logic Analyzer Interface.
3. Prepare the development board for testing.
a. The file exp5_functions.bit contains the circuit you’ll be analyzing. This file is located on
the CPE 169 website.
4. Configure the LA to capture and display the output waveforms.
5. Capture and display the timing waveforms.
6. Analyze the F1 and F2 Signals from the timing waveforms.
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Experiment 5 (Xilinx 13.2)
a.
b.
c.
Enter this data into a truth table and include it in your report. Use the values of signals
A, B, C, and D as inputs and F1 and F2 as outputs (A, B, C, and D are independent
variables while F1 and F2 are dependent variables).
Generate an output equation for F1 and F2 in compact minterm form.
Write an equation for F1 and F2 in reduced SOP form. You’ll use these two equations to
develop a circuit that implements these equations in the next section.
Procedure 2: Implementing a Circuit Using the Xilinx Design Methodology
In this procedure, you’ll use the Xilinx ISE Software to implement a circuit using the programmable logic
device on a development board. The circuit that you’ll implement is essentially a copy of the circuit that
you analyzed in the first procedure of this experiment. The circuit in the first procedure of this experiment
was presented in black-box form. Your analysis of this circuit yielded equations for its output; and these
equations will be used in this procedure to produce a functionally equivalent copy of that circuit.
Figure 3: Interface specifications for circuit to be implemented.
The Xilinx ISE software will be the primary tool for implementing circuits in this experiment as well as all
the experiments that follow. This software tool is also used in CPE 229/269, CPE 329, and CSC 315. The
more you learn about both the Xilinx ISE environment and VHDL modeling techniques, the better off
you’ll be in this and later classes. The procedure outlined below represents a brief introduction to the Xilinx
ISE software and the Xilinx Design Methodology. You’ll be adding skills in both of these areas as you
progress through this and other classes.
Refer to the information on Creating VHDL Projects in Xilinx ISE posted on the CPE-169 website for
detailed procedures to use with the latest version of Xilinx tools running on your lab computers.
Since this is your first time using the tools, be sure to follow all of the steps, in the order given. Skipping
steps may result in horrendously hideous outcomes that you really don’t want to experience. (A confused
CAD tool is not a happy CAD tool!) Be sure to read the Explanations as you proceed, so that you begin to
understand why you are doing what you are doing. So, go for it!...See what happens…Ask questions when
things don’t make sense…and have fun!
PROCEDURES:
1. Launch the Xilinx ISE software.
2.
Start a new VHDL Project and create a new VHDL Source Code Module.
3.
Enter the F1 and F2 equations you derived in Procedure 1 into the VHDL Source Code Module.
4.
Synthesize your VHDL source code.
5.
Create input signals to test your circuit design using a VHDL Test Bench file.
6.
Simulate your circuit using the Test Bench input signals to verify that it operates properly.
7.
Map your circuit to the pins on the FPGA on your development board.
Signal
F1
F2
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LD7
LD6
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Experiment 5 (Xilinx 13.2)
Signal
A
B
C
D
Nexys Device
SW7
SW6
SW5
SW4
Table 1: I/O assignments for Experiment 5 using the Nexys development board.
8.
Generate the Configuration File for programming the FPGA.
9.
Download the circuit to the development board.
10. Verify proper circuit operation:
a) Set the switches on the development board to test each of the possible input
combinations. For each input combination, verify that the outputs have the expected
values from your original equations.
11. Demonstrate your properly functioning circuit to the lab instructor or lab assistant.
12. Be sure to provide a copy of your VHDL source code and a blackbox diagram of your circuit
(including test connections to switches / LEDs) with your final report.
13. Save a Copy of your ISE Project; preferably to your own USB drive.
a)
YOU CAN NOT COUNT ON ANY OF YOUR FILES REMAINING INTACT ON THE LOCAL
C: DRIVE OF THE LAB COMPUTER AFTER YOU LEAVE THE LAB.
b)
From this point on, you will often be reusing or modifying VHDL code from previous labs.
Therefore, it is imperative that you save your ISE projects to a location that you are sure you can
control and access in the future.
Questions
1.
Describe the number of ICs that would be required to implement the two functions if discrete logic ICs
had been used in this experiment rather than the FPGA on the development board. Use only inverters
and 4-input NAND gates in your solution and include the inverters as part of the gate count. Clearly
state any assumptions you make in your solution.
2.
What effect, if any, does the development board’s system clock have on the Logic Analyzer’s ability to
store data samples. Briefly but clearly support your answer.
3.
Does the sampling frequency of the Logic Analyzer affect the number of samples it can store? Fully
explain your answer.
4.
Does the timing display on the Logic Analyzer have the ability to display a different number of
samples for a given set of captured data samples? Briefly explain your answer.
5.
There was one major difference between the original logic circuit you analyzed (Procedure 1) and the
circuit you designed and implemented on the development board (Procedure 2). Briefly explain what
this difference was. HINT: Consider what you would see on the Logic Analyzer display if you were to
reconnect it and used it to test the circuit you designed and implemented on the development board.
6.
If the design simulation timing diagram output did not match the Logic Analyzer’s display for a given
circuit, would it necessarily indicate that the circuit has been incorrectly implemented?
7.
Xilinx Field-Programmable Gate Arrays (FPGAs) implement combinational logic functions using
Configurable Logic Blocks (CLBs), with each CLB containing eight look-up tables (LUT). Each look-
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Experiment 5 (Xilinx 13.2)
up table produces one output signal from up to four different input signals. These look-up tables are
simply programmed to output the correct logic function values for all 16 (24) possible combinations of
input signal logic levels (rather than connecting together specific AND and OR gates to implement the
Boolean function).
Programmable logic device sizes are typically compared in terms of the number of equivalent logic
cells that they contain; where a logic cell is roughly equivalent to one of the look-up tables in the
Spartan 3 FPGA. How many equivalent logic cells are available in the particular FPGA used on your
development board (Spartan 3 FPGA on the Nexys Board or the Spartan 3E on the Nexys-2 Board)?
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