ECE-599 PHASE LOCKED LOOPS-I
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ECE-599:Low Power, Adaptive Bandwidth Tracking
Phase Locked Loop Design
Guanghua Shu, Romesh Kumar Nandwana
Abstract—A low power, adaptive bandwidth tracking Phase
Locked Loop (PLL) is presented in this paper. Designed PLL
operates over a wide frequency range of 250MHz to 1GHz with
a fixed multiplication factor of 8. PLL is optimized for 0.2% UI
of r.m.s. jitter over the whole frequency range with bandwidth
tracking to keep the power consumption minimum. In addition,
a multiplier block is used to increase the input frequency by
two, which further increases the power efficiency of the PLL.
The circuit is designed and simulated using 0.18µm process with
supply voltage of 1.8V.
Index Terms—Phase Locked Loop, Voltage Controlled Oscillator, Phase Noise, Multiplier, Bandwidth Tracking.
Figure 1.
Block Diagram of The Designed PLL
A. Bandwidth Selection:
I. I NTRODUCTION
HASE Locked Loops are one of the most important and
integral part of high speed communication circuits. They
are used as de-facto clock generators, frequency multipliers
and also plays key role in clock distribution network.
This report will detail the design of an analog PLL for
the specifications given in Table I. Designed PLL have the
bandwidth tracking ability to relax the phase noise requirements of the voltage controlled oscillator and have maximum
0.2% of UI r.m.s jitter over the whole operating range. The
first section will discuss the PLL architecture and criteria for
selecting the bandwidth. The following sections will discuss
the design details of each of the sub blocks of the PLL and
summary of results with conclusions.
P
Table I
P HASE L OCKED L OOP D ESIGN R EQUIREMENTS
Parameters
Technology
Supply Voltage
Operating Frequency
Fixed Feedback Divider
Absolute Jitter
Power Consumption
Specified Values
0.18µm
<1.8 V
250MHz-1GHz
8
0.2% of the period(r.m.s.)
Minimum
II. S YSTEM L EVEL D ESIGN
Figure 1 shows the block level diagram of the designed
PLL. In this PLL we have a reference frequency multiplier
which multiplies the input frequency by two. This multiplied
signal is given as input to the PLL. The PLL loop consists
of a phase frequency detector (PFD), charge pump,loop filter,
voltage controlled oscillator (VCO) and a divide by 4 counter
block. For adaptive bandwidth tracking, we control the charge
pump current based on the control voltage of the VCO, which
changes proportionally with the frequency of operation.
For calculating the system level parameters such as PLL
bandwidth,VCO phase noise requirements etc we first check
the specifications provided in table I.
From here we can see that input frequency can vary from
31.25MHz to 125MHz ( fout
8 ). As rule of thumb, the maximum
fref
bandwidth that we can have is 10
from stability point of
view. So in this case we can have maximum bandwidth of
3.125MHz for the lowest operating frequency and 12.5MHz
for highest operating frequency. However if we use a classical
PLL, bandwidth is fixed across all the operating frequencies
to the 3.125MHz. For this bandwidth calculated the phase
noise requirements of the VCO is -103dBc/Hz at 1MHz offset.
Which means that we need a very high spectral purity VCO
and to achieve the specifications it will consume a lot of power.
To make the design power efficient, we need to reduce the
phase noise requirement of the VCO. Within this design, two
ways are provided to reduce the VCO power consumption to
make the PLL more power efficient. One way is to increase the
reference frequency of the PLL, thus in turn we can increase
PLL bandwidth. For this purpose we can use a multiplier
block which can multiply the input signal frequency by 2
without adding significantly high residual phase noise while
consuming minimum power. With the help of this approach,
we can have the bandwidth of 6.25 MHz across all the
frequencies without suffering from stability issues.
With the reference frequency multiplication, only the power
efficiency at the lowest operating frequency is optimized. As
the VCO frequency increases, phase noise also increases, and
we still need to burn more power to meet the jitter requirement
with a fixed bandwidth under the same reason stated above [1],
[6], [7]. However if the bandwidth can increase along with
the reference frequency then the PLL power performance will
be optimum over all the frequency range. For this purpose,
an adaptive bandwidth tracking is also adopted. Simple idea
of bandwidth tracking is that by changing the charge-pump
ECE-599 PHASE LOCKED LOOPS-I
Output Phase Noise of Synthesizer
−80
Detector Noise
VCO Noise
Total Noise
−90
−100
−110
L(f) (dBc/Hz)
current with respect to operating frequency, the bandwidth will
track the changes in operating frequency.
However this approach poses some potential stability issues.
When we increase the charge pump current to increase bandwidth the location of poles and zeros of the loop filter does
not change and it may reduce the phase margin and degrades
stability of PLL loop. But with the careful consideration of
phase margin from the beginning, we can design the circuit
in such a way that the phase margin is always sufficient for
satisfying stability criteria.
Here bandwidth tracking circuit is designed for increasing
the bandwidth from 6.25MHz at 250MHz operating frequency
to 12.5MHz at 1GHz. Just by tracking the bandwidth up
to twice instead of four times, we can make sure that the
phase margin is not degrading significantly. Moreover if the
PLL is optimized at the center (625MHz) of the operating
frequency range of 250MHz to 1GHz, equal phase margin
degradation at both the corners of operating frequency range
could be ensured, which is a more optimal design compared
to optimizing the PLL at low operating frequency in terms of
phase margin.
2
−120
−130
−140
−150
−160
−170
−180
2
10
3
10
4
10
5
10
Frequency Offset (Hz)
6
10
7
10
8
10
Figure 3.
Calculated Phase Noise Contribution from VCO and Phase
Detector/Charge Pump @ 625MHz
Figure 4. PLL Open Loop Gain and Phase for Output Frequency of 625MHz
Figure 2. PLL Design Assistant For Calculating Phase Noise and Pole-Zero
Locations
For calculating the noise contribution of all the noise sources
and to calculate the phase noise requirement of the VCO, a
close loop based approach is used instead of open loop based
iterative process. PLL Design Assistant tool, designed by
Michel Perrot, is used as shown in figure 2. All the calculations
are done at the output frequency of 625MHz.
Figure 3 shows the calculated phase noise contribution
different blocks and the overall phase noise plot of the PLL.
Pole and zero location is chosen in such a way that we have
the maximum phase margin of 70◦ at the center frequency of
operation (625MHz). Figure 4 shows the open loop gain and
phase margin plots of the PLL at 625MHz.
Figure 5 shows the phase margin variation with bandwidth.
From here we can see that even with fixed pole and zero
distribution, changing the charge pump current by two times
degrades the phase margin to 68.70◦ which poses negligible
threat to the stability of the system.
With the parameter values calculated by PLL Design Assistant, now we run the behavioral simulations on PLL using
CppSim also designed by Michel Perrot. Here the correctness
of the closed loop calculation can be verified, and we can also
see the effect charge pump current variation on PLL jitter .
Table II summarizes the simulated bandwidth variations and
the absolute jitter in each case.
Thus with the above procedure, we can design the PLL with
a sufficient phase margin of 68.70◦ and adaptive bandwidth
of 6.25MHz to 12.5MHz with the phase noise requirement of
-97dBc/Hz @1MHz offset for 625MHz center frequency.
Figure 5. Effect of Bandwidth Variation on Phase Margin Keeping the zero
location same
ECE-599 PHASE LOCKED LOOPS-I
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Table II
C PP S IM S IMULATED J ITTER W ITH A DAPTIVE BANDWIDTH T RACKING
Fout (MHz)
Bandwidth(MHz)
Absolute r.m.s Jitter (%UI)
250
6.25
0.19
625
9.375
0.14
1000
12.5
0.17
Figure 8 shows the phase noise plot of the VCO at 1GHz
reference frequency. From the figure we can see that at 1MHz
offset the phase noise is -97dBc/Hz, which is sufficient for
satisfying the phase noise requirement of the PLL.
III. PLL B LOCK D ESIGN
In this section we will discuss different sub-blocks of the
designed PLL.
A. Voltage Controlled Oscillator
Figure 6 shows the schematic of the VCO [1]. Differential
delay cells with pass transistor based feed forward path are
used for designing the VCO. Output is AC coupled with a
buffer to make the output swing rail to rail across all the
frequencies and this buffer also provides enough strength to
drive the capacitive load of feedback divider .
Figure 8.
VCO Phase Noise Plot @1GHz Reference Frequency
B. Loop Filter
A standard lead-lag filter is used with two capacitors and
one resistor. Figure 9 shows the loop filter schematic and the
component values for optimum pole-zero distribution.
Figure 6.
Voltage Controlled Oscillator Schematic
Figure 7 shows the output frequency and Kvco variation
with control voltage. From here we can see that output
frequency variation with control voltage is linear and variation
in Kvco is up to ±25% from the nominal value of 1.7 GHz
V .
Figure 7.
VCO Control Voltage Vs Frequency and Kvco Variation
Figure 9.
Loop Filter Schematic
C. Phase Frequency Detector
Figure 10.
Phase Frequency Detector Schematic
ECE-599 PHASE LOCKED LOOPS-I
Figure 10 shows the pass transistor based phase frequency
detector [2]. Here the reset time is set by the NAND gate and
Inverter delay and total reset time can be given as
treset = 2 × tN AN D + tIN V
This circuit topology guarantees that S_RST signal always
comes before M_RST signal and ensures that the overlap time
is not more then the reset time.
D. Charge Pump
Figure 11 shows the charge pump schematic [2], [5]. In
addition to the main charge-pump with a current source
for biasing, it also has an additional section for bandwidth
tracking. In this section, based on the VCO control voltage,
the biasing current changes and the charge-pump current
increases when we increase the frequency. Fixed reference
current source provides about 7 µA current to the charge pump.
While the control voltage changes the total output current from
20 µA to 30 µA. Thus increasing the frequency to 1.5 times
of the nominal frequency. Notice that however the circuit was
designed to increase the charge pump current from 20 µA to
40 µA; yet due to increasing mismatches in the charge pump
at higher frequencies, the circuit is only able to increase the
current up to the 30 µA, while giving the reasonable ripple
on the control voltage. Further simulation using ideal charge
pump shows that bandwidth could be tracked as high as 4
times of the nominal bandwidth, while the ripple on control
voltage is still reasonably small.
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the total charge-pump current is very linear with the control
voltage variation.
E. Divider
Flip-flop based divide by 4 counter is used for the system.
Figure 13 shows the divider schematic. TSPC based flip-flops
are used for designing the divider [3].
Figure 13.
Divider and TSPC flip-flop Schematic
F. Multiplier Block
For multiplying the input frequency by two, an XOR based
multiplier is used with a delay block. Figure 14 shows the
multiplier schematic with the timing waveforms at different
nodes of the circuit. Here if the input duty cycle is not 50%,
we can see high deterministic jitter at the output. However
input signal source for the PLLs is usually a crystal oscillator
which has very high accuracy in duty cycle, and does not vary
much from the nominal value.
Figure 11.
Charge Pump Schematic
Figure 12.
Charge Pump Current Variation with Control Voltage For
Bandwidth Tracking
Figure 12 shows the charge pump current variation with
control voltage. From here we can see that the change in
Figure 14.
Multiplier Block Diagram and Timing Waveforms
ECE-599 PHASE LOCKED LOOPS-I
PLL Power Consumption Pie-Chart @ 250MHz, 650MHz & 1GHz
IV. R ESULTS
After designing the PLL with the above mentioned circuit
blocks, we run the simulation and get the performance parameters. Figure 16 shows the initial transient settling of the
loop at different frequencies. From here we can see that the
maximum control voltage ripple is around 10mV which causes
2% of UI deterministic jitter.
PLL Closed Loop Phase Noise Plot
−80
250 MHz
1 GHz
625 MHz
−90
−100
Magnitude (dBc/Hz)
Figure 15.
5
−110
−120
−130
−140 2
10
3
10
4
10
5
10
Frequency (Hz)
6
7
10
10
Figure 17.
PLL Closed Loop Phase Noise Analysis Plot @ 250MHz,
625MHz and 1GHz
Table IV
PLL P OWER C ONSUMPTION B REAK - DOWN
Figure 16.
Initial Transient Simulation For Locking Behavior
Figure17 shows the closed loop PLL phase noise plots at
250MHz, 625MHz and 1GHz output frequencies. Table III
summarizes the PLL performance at the above mentioned
three frequencies. From here we can see that the worst case
jitter is 0.2% of UI which exactly meets the specification
requirements.
Total power consumption of the PLL varies with the
operating frequency and maximum power consumption of
1.43mW is observed at 1GHz output frequency with 0.197%
UI of random jitter. Figure 15 and table IV shows the power
consumption of different blocks at different frequencies of
operation.
Table III
PLL P ERFORMANCE S UMMARY AT D IFFERENT O UTPUT F REQUENCIES
Fout (MHz)
Charge Pump Current Icp(µA)
Jitter (UI)
VCO Phase Noise
@ 1MHz offset( dBc/Hz)
Total Power (mW)
250
20
0.0020
-97.1
625
25
0.0017
-97.93
1000
30
0.00197
-99.3
0.5760
1.0267
1.4274
Fout (MHz)
Supply Voltage (V)
VCO Current (mA)
Multiplier Block Current (mA)
Divider Current (mA)
PFD Current (mA)
CP Current (mA)
Total Current (mA)
Total Power (mW)
250
1.8
0.1550
0.0506
0.0150
0.0631
0.0363
0.3200
0.5760
625
1.8
0.2011
0.1260
0.0371
0.1580
0.0482
0.5704
1.0267
1000
1.8
0.2900
0.1880
0.0600
0.1950
0.0600
0.7930
1.4274
V. C ONCLUSIONS
An analog PLL has been successfully designed for the given
specifications with the assumption of 50% input duty cycle.
Also there are a few more things to consider such as when
the frequency of the operation changes, Kvco also varies and
effects the bandwidth tracking ability of the circuit. Apart from
these, the circuit have limitations of deterministic jitter due to
charge pump mismatch and static phase offset as a classical
analog PLL.
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ECE-599 PHASE LOCKED LOOPS-I
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