International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 8, August 2012)
Behavioral Simulation of Delta-Sigma Fractional-N PLL
for WiMAX Applications
Gan Leong Kit1, Kong Chooi Yee2, Syed Khaleel Ahmed3, Fazrena Azlee Hamid4
Centre for Micro and Nano Engineering,
Universiti Tenaga Nasional,
Jalan IKRAM-UNITEN
43000 Kajang, Selangor,
MALAYSIA
1
leong_kit0721@yahoo.com
2
elainekcy@yahoo.com
3
syedkhaleel@uniten.edu.my
4
fazrena@uniten.edu.my
The RF chipset used to implement WiMAX radio must be
flexible enough to handle a variety of frequency bands. At
the same time, it is able to meet the growth of wireless
transceiver systems in the worldwide. This is achievable by
looking for creative and innovative ways to meet design
challenges such as improving of the resolution, speed and
lowering the power and area of the circuits. The
PLL_based frequency synthesizer in the wireless
communication system has need of low integrated phase
noise and fast settling time. Thus, undoubtedly it is one of
the most challenging RF blocks. The frequency synthesizer
acts as a Local Oscillator (LO) generation unit that is used
to translate baseband and RF signals by means of mixing. It
frequently determines the overall performance of a radio
communication system. ∑-∆ fractional-N PLL provides
flexibility in terms of frequency resolution. Besides that, it
is able to meet the requirements like low phase noise and
fast settling time. Hence, it is chosen for the WiMAX
system design to ensure the good quality of the frequency
synthesizer.
Abstract— Frequency synthesizer’s behavior affects the
wireless communication system. The quality of the frequency
synthesizer is highly dependent on the type of Phase LockedLoop (PLL) used for the system. It is crucial for the designers
determine the correct type of PLL to achieve high noise
performance, high switching speed, and high resolution in the
wireless communication system. In this paper, several PLLbased frequency synthesizers are reviewed, including the
design options and associated trade-offs. This paper presents
the design and simulation results of a proposed ∑-∆
fractional-N PLL based frequency synthesizer for the Mobile
WiMAX standard. Design requirements in terms of phase
noise, settling time, frequency resolution and frequency of
operation are presented. The behavioral simulation results
using CppSim program (C++ simulator) show settling time
about 17µs and the integrated phase noise is less than 1 °rms
Keywords— Phase locked loop, WiMAX, phase noise,
behavioral simulation
I.
INTRODUCTION
In the communications industry, wireless communication
technology advancements seem to come in waves and have
been highly developed. The next crest that is hitting is the
IEEE 802.16 standard, Worldwide Interoperability of
Microwave Access (WiMAX). WiMAX is a wireless
internet service designed to serve a large number of users
over wide geographical area at low cost.
In this paper, the behavioral simulation on the fractional-N
PLL is implemented using CppSim simulation tool [2].
CppSim is one of the powerful behavior simulators that
helps designer to ensure the good quality of the frequency
synthesizer used. The rest of the paper is organized as
follows. Section II describes the different topologies of
PLL-based frequency synthesizers, while section III
describes the methodology in designing the ∑-∆ fractionalN PLL for WiMAX application. Section IV describes the
specifications for the WiMAX standard. The modeling and
behavioral simulation design approaches is discussed in
detail in section IV. Section V presents the design results
from the simulation and section VI concludes the paper.
Unlike 2G and 3G wireless communication systems with a
fixed channel bandwidth, the Mobile WiMAX standard
enables a variable channel size and multiple frequency
allocation and thereby offers very flexible deployment.As a
result of multi-wideband operation, a high performance RF
front-end has to be employed [1].
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International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 8, August 2012)
II.
With a fixed reference frequency, the PLL output
frequency can be easily varied by changing the value of the
newly added N divider. Phase-frequency detector (PFD) is
an advance comparator. It compares not only the phase of
the two input signals, but also compares their frequencies,
and produces an error proportional to both phase and
frequency. The N divider divides VCO output frequency by
N. This allows the designer to produce an output frequency
N times the reference signal; i.e.
FREQUENCY SYNTHESIS TOPOLOGIES
Frequency synthesizer is important in many electronics
application. There are several topologies of PLL-based
frequency synthesizers that have been developed
throughout the years. In this section, the basic concept of
Phase-Locked Loop will first be discussed, followed by
Integer-N Phase-Locked Loop, Fractional-N Phase-Locked
Loop and finally Sigma-Delta Fractional-N PLL.
A.
Phase-Locked Loop
fVCO  N . f REF
PLL is essentially a closed loop feedback control system
that synchronizes the output phase and frequency of a
controllable oscillator to match the output phase and
frequency of a reference oscillator [4]. Fig. 1 shows a basic
PLL block diagram. It consists of a Phase Comparator
(PC), Low-pass filter (LPF), Amplifier (AMP) and
Voltage-Controlled Oscillator (VCO). The PC compares
two input signals’ phases and produces an error voltage that
proportional to the difference. The high frequency
components are filtered out by the LPF. In practice, the
high frequency components can only be attenuated. The
output quality of the LPF depends on the order and design
methodology (passive or active components). The filtered
error voltage is amplified, and then applied to the VCO
input. The VCO produces a signal whose frequency
depends on the input voltage. When the phase difference
between the reference input and VCO output frequency is
unvarying over time, it implies that both reference and
feedback signals are aligned. Eventually, the PLL system
will be in locked state.
Reference
signal
PC
LPF
In integer-N PLL, the channel spacing, an important
parameter in communication systems, is equal to the
reference frequency, fREF. Therefore, to achieve a smaller
resolution, a low reference frequency should be chosen. In
consequence, the N divider value has to be increased to
keep VCO running at the same frequency. PLL phase noise
is increased while N value getting larger. In addition, PLL
bandwidth must be small relatively to the reference
frequency, and hence, raise the time for PLL to lock. With
a small PLL loop bandwidth, the VCO’s phase noise will
be insufficiently suppressed at low offset frequencies as
well [5].
Reference
signal
PFD
LPF
VCO
N
Fig. 2 Integer-N PLL Block Diagram
AMP
C.
VCO
Fractional-N Phase-Locked Loop
Fractional-N PLL which utilizes a non-integer divider to
replace the N divider helps in obtaining a finer resolution
than the reference frequency supplied. Similarly, with the
N divider, the fractional-N PLL output can easily obtain a
frequency that is different from the reference input. In
addition, fractional-N PLL output can frequency can be a
fractional ratio of the reference frequency. It means the
frequency resolution or channel spacing is finer than the
reference frequency. Given that VCO is running at same
frequency, fractional-N PLL which allows higher reference
frequency needs a lower N as compared to integer-N PLL.
This eventually avoids the circumstance where PLL phase
noise increased due to high N divider value.
Fig. 1 PLL Block Diagram
B.
(1)
Integer-N Phase-Locked Loop
Fig. 2 shows a simplified block diagram of integer-N PLL.
Amplifier is an optional component for integer-N PLL if
the loop filter output managed to cover the VCO tuning
range. Integer-N PLL can be obtained by placing a
programmable divider (N) in the PLL feedback path. This
is an enhanced feature as compared to the phase-locked
loop in section IIA.
447
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Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 8, August 2012)
The fractional division value is achieved by manipulating
the integer dividers in a way that the average division ratio
is the desired fractional value. With fractional-N PLLs,
requirements such as higher loop bandwidth with faster
lock time, are achievable. Fig. 3 shows the block diagram
of the fractional-N PLL. Fractional-N PLL is obtained by
replacing the N divider with a dual-modulus divider,
N/N+1. The dual-modulus divider divides its input by N
when the accumulator does not overflow and divides its
input by N+1 when overflow signal appears in the
accumulator. On average, the divider value will eventually
result in a fractional value, Nfrac between N and N+1.
Reference
signal
PFD
The input K is processed by the ∑-∆ modulator to produce
an encoded sequence, and this sequence is used to alter the
division modulus of the N/N+1 divider. When higher order
∑-∆ modulator is used, the spurious energy is spread out
and shaped to resemble high frequency noise, which is
removed by the low-pass nature of the loop filter. Fine
frequency resolution can be restricted just by sizing the
digital integrators. Fig. 4 illustrates the simplified ∑-∆
fractional-N PLL [7]. The digital noise shaping ∑-∆
modulator is used to randomize the instantaneous loop
divide ratio. This can be achieved by controlling the
frequency division ratio in the PLL via ∑-∆ modulator
output [8].
VCO
LPF
Reference
signal
PFD
VCO
LPF
N/N+1
N/N+1
N selection
K
K
F
-
Latch
N selection
METHODOLOGY
The methodology of designing ∑-∆ fractional-N PLL for
WiMAX application through behavioral simulation
approach is discussed in this section. In order to perform
frequency synthesizer behavioral simulation for any system
application, specifications definition base on system
requirements is essential. WiMAX system specification
gives an idea of frequency synthesizer topology to be used,
overall expected performance and fabrication technology to
be applied. The detail specification of WiMAX system will
be discussed in Section IV.
In this work, the PLL Design Assistant will be used as a
tool to provide the overall system parameters for the
frequency synthesizer. The PLL Design Assistant is part of
CppSim which allows the design of phase-locked loops at
transfer function level [2]. The overall system parameters
can be inspected by performing noise and dynamic analysis
through the use of PLL Design Assistant. The other
detailed PLL parameters will be further investigated using
the CppSim behavioral simulator. The simulated step
response and phase noise of the synthesizer via CppSim
will be compared to the results obtained from PLL Design
Assistant. Fig. 5 portrays the simplified flowchart of
behavioral simulation steps in this work.
(2)
The alternating N/N+1 division ratios cause the output
frequency to vary between N.fREF and (N+1).fREF. This
alternating cyclical process generates spurious tones at the
fractional offset frequency [6].
D.
H(z)
III.
Assume the accumulator size is F and it overflows K times
every F clock cycles. Then, the divider divides K times by
N+1 and by N for the rest of the time. Therefore,
K .( N  1)  ( F  K ). N
K
N
F
F
+
Figure 4. ∑-∆ Fractional-N PLL Block Diagram
Fig. 3 Fractional-N PLL Block Diagram
N frac 
+
Sigma-Delta Fractional -N PLL
The introduction of fractional spurs into the systems when
manipulating the divider modulus to obtain the fractional
ratio is one of fractional-N PLLs’ drawbacks. One of the
spur suppression approaches is employing dithering
technique with a higher order sigma-delta (∑-∆) modulator.
Since the alternating process is deterministic, it is feasible
to correct the periodic phase error, dithering is a technique
used to randomize the choice of the division ratio.
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Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 8, August 2012)
It frequently establishes the overall performance of a
radio communication system. The complexity and
requirements can be assessed in relation to the WiMAX RF
architecture. A frequency synthesizer has to provide all
necessary frequencies for the down and up conversion with
proper channel spacing that corresponds to the channel
bandwidth or to the frequency raster. Frequency switching
has to be performed switfly to establish the output
frequency in a required finite time. WiMAX system entails
strict requirements on synthesizers in terms of frequency
tuning range, frequency resolution, and frequency purity.
Ideally, the synthesized signal is a pure sinusoidal or square
waveform which is represented by an impulse in the
frequency domain. However, the oscillator random
fluctuations produce tails on both sides of the desired
frequency. They are characterized by its phase noise (or
spur level) at a certain frequency offset from the desired
carrier frequency in unit of dBc/Hz (or dBc) [7]. Table 1
summarizes the requirements given by the Mobile WiMAX
standard [1].
Fig. 5 Behavioral Simulation Flowchart
The PLL Design Assistant program provides a graphical
user interface methodology to the design of PLL. It acts as
a tool allowing fast and straightforward design of PLLs at
the transfer function level. In particular, the program
acquires as input a desired closed loop transfer function
description and then automatically calculates the open loop
parameters that must be chosen to achieve the design [9].
Noise parameters like the magnitude of PFD noise and
VCO noise are input to the PLL Design Assistant program.
Subsequently, the estimation of the PLL noise performance
in terms of phase noise and rms jitter are obtained and
observed at the PLL output [5].
Behavioral simulation is done using CppSim [2]. This
allows a detailed analysis of the implemented system in this
work, for which MATLAB can be used for postprocessing. CppSim is a general behavioral simulator that
leverages the C++ language to achieve fast simulation
times, and a graphical framework to allow ease of design
entry and modification. The advantage of this simulator is
that systems can be expressed in a hierarchical level, object
code can be executed in a multi-rate manner, and signals or
data can be stored in binary format compatible with other
simulators.
IV.
TABLE I
MOBILE WIMAX CHANNEL PROFILES DEFINED BY THE WIMAX FORUM
Frequency
Range (GHz)
Channel
Frequency Step
(kHz)
2.3 - 2.4
250
2.305 - 2.320
2.345 - 2.360
250
2.496 - 2.69
250 (200)
3.3 - 3.4
3.4 - 3.8
3.4 - 3.6
3.6 - 3.8
250
Channel
Bandwidth
(MHz)
FFT Size
5
10
8.75
3.5
5
10
5
10
5
512
1024
1024
512
512
1024
512
1024
512
7
1024
10
1024
Duplexing
Mode
Settling
Time [µs]
Phase
Jitter
[°rms]
< 50
<1
TDD
TDD
TDD
TDD
The integrated phase noise should be less than 1° rootmean-square (rms) with an integration frequency from 1/20
of tone spacing to 1/2 channel bandwidth. Moreover, a
switching time of less than 50µs was aimed for the
frequency synthesizer design. The channel frequency step
given by the WiMAX standard is 250 kHz. For this, the
local oscillator has to deliver the required frequency with a
resolution of 125 kHz as a result of raster overlapping for
different channel bandwidths [1].
This stringent WiMAX requirements of high bandwidth,
fast lock (i.e. small settling time), narrow frequency
spacing and low integrated phase noise may be achieved by
the ∑-∆ fractional-N PLL. This architecture can achieve
very small frequency resolution by dithering the divide
value according to the output of a third-order multistage
noise shaping (MASH) modulator which generates integer
values ranging from -3 to 4.
SPECIFICATIONS DESCRIPTION
The Mobile WiMAX standard offers very flexible
deployment by enabling a variable channel size and
multiple frequency allocation. Practically, myriad types of
communication systems use local oscillators (LO) based on
frequency synthesis that is mixed with the incoming RF
signal to translate a lower frequency signal that can be
converted to digital form and processed in the baseband IC.
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V.
The realization of fractional division ability allows the
synthesizer to achieve very high frequency resolution, but
also introducing inevitable error at high-frequency
(quantization error) by performing coarse quantization. The
∑-∆ modulator implementation has the added benefit of
shaping the quantization noise away from the signals of
interest whereby the signals of interest are low-pass filtered
while quantization noise is high-pass filtered.
Fig. 7 illustrates the noise sources in the PLL that
contribute to the impact on overall PLL performance. The
noise modeling can be grouped into 3 categories, mainly
detector noise, VCO noise and ∑-∆ quantization noise.
Detector noise which consists of reference jitter, reference
feedthrough and charge pump noise dominate at low
frequencies [5]. VCO produces phase noise profile with a
slope of 20 dB per decade. The ∑-∆ quantization noise is
moved to high frequencies due to noise shaping. The
influence of VCO and ∑-∆ quantization noise dominates at
high frequencies [5].
MODELING AND BEHAVIORAL SIMULATION
Simulation of fractional-N synthesizers is particularly
challenging for a variety of reasons. The high output
frequency of the synthesizer (often in the GHz range)
imposes high simulation sample frequency for traditional
simulators, thus taking a long time to compute the dynamic
response of the system since many simulation samples are
required. While for noise simulation, the fractional-N
synthesizer adds the additional constraint that its behavior
is non-periodic in steady-state due to the dithering action of
the divide value. This has prevented the use of methods
developed for periodic steady-state conditions as used with
simulators such as SpectreRF [6].
In this paper, ∑-∆ fractional-N PLL based frequency
synthesizer is designed to meet the specifications of
WiMAX system, and it is the focus in the PLL Design
Assistant program. Fig. 6 shows the ∑-∆ fractional-N
frequency synthesizer block diagram, along with a snapshot
of the probed signals at various nodes of the system. The
synthesizer model comprises of PFD, Charge Pump, Loop
Filter, VCO, Divider and ∑-∆ modulator. Reference signal
from the oscillator and feedback signal from the divider are
being compared at the PFD. The polarity of the phase
difference (phase error) is used to turn on the pump-up or
pump-down current source. The charge that will be
transferred to or taken away from the capacitor in the loop
filter is proportional to the magnitude phase difference
produced by the PFD. This will in turn be used to adjust the
tuning voltage of the VCO in a way to minimize the phase
difference. Ideally, the VCO tuning voltage output from the
loop filter should be a clean and stable DC when the
synthesizer in lock condition. The output of ∑-∆ modulator
is used to control the division ratio of the divider which
dynamically switching between two or more values
depending on its order.
Fig. 7 Noise Sources in a ∑-∆ Fractional-N Frequency
Synthesizer
It is also desirable to investigate the dynamic response of
the synthesizer in order to evaluate stability and
characterize the performance of the system. The PLL
Design Assistant program allows us to achieve both of
these objectives by leveraging the modeling approach
described in [5]. In the next section, dynamic analysis and
noise analysis will be presented via closed loop step
response and output phase noise respectively. The loop
bandwidth contributes the most in shaping the settling time
of the system. As the modeling of noise sources includes
detector noise, VCO noise and quantization noise - these
may be viewed independently such that to observe their
contribution to the total phase noise.
Fig. 6 ∑-∆ Fractional-N Frequency Synthesizers and
Associated Signals
Behavioral simulation employs a high level of
abstraction to model the design using various approaches.
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A behavioral design might, for example, contain high-level
operations, such as an eight-bit addition operator, without
containing details on how the design will be implemented.
This is in contrast with the transistor level simulation
techniques that model the adder in a structural design. It
can be impractical due to prohibitive run times. Hence,
simulation using behavioral blocks offer key architectural
design capabilities. The accuracy and precision of the
behavioral simulator as compared to the measured value
depends on how good the modeling algorithm is being
realized. Behavioral simulation allows the designer to
verify syntax and functionality without timing information.
Errors identified early in the design cycles are inexpensive
to fix as compared to functional errors identified during
silicon debug which can be very costly. After the required
functionality using a particular architecture is achieved,
transistor level and timing simulation methods can be
implemented to acquire more detailed verification data.
The CppSim package [2] makes two contributions to the
behavioral simulation of systems. First, it provides a netlist
to C++ translator that allows the C++ simulation code to be
automatically written based on a SPICE-compatible netlist
produced by a graphical schematic capture program. In
doing so, the designer can quickly piece together a system
in a graphical manner based on a library of system
primitives with corresponding code descriptions, and
benefit from the power and speed of running compiled C++
code. Second, the CppSim package provides a set of C++
classes that allow fast and convenient implementation of
system primitives. Common system blocks such a filters,
VCO’s, nonlinear amplifiers, and signal generators are
easily realized using these classes, so that the creation of
new system primitives is typically fast and straightforward
[2].
VI.
Parameter
Value
Center Frequency,
fc
VCO
Gain
Phase Noise
α
Phase-Frequency Detector
Reset Delay
Reference Frequency
Loop Bandwidth
∑∆ Modulator Topology
Divide Ratio
Charge Pump Current
Shape
Order
Type
fz / fo
Loop Filter
RC filters
Lead/lag filter
2.566
Unit
GHz
1/8
MHz/V
dBc/Hz
Ns
MHz
kHz
µA
-
fo1 = 1.25
MHz
fo2 = 2.5
MHz
fp = 543.2
kHz
fz = 31.25
kHz
K = 2.045 x 1011
-
gain = 1/(3.335 x 10-10)
-
50
-135 @10MHz
1 (Tristate Design)
2.5
35
250
MASH 1-1-1
73.1314
100
Butterworth
2
2
These parameters are then put into the PLL Design
Assistant. The resulting noise plot and step response are
shown in Fig. 8 and Fig. 9 respectively. Fig. 8 depicted the
detector noise dominates at lower frequencies in
comparison with the VCO noise which dominates at higher
frequencies. The sigma-delta (S-D) noise does not give a
great impact at high frequencies as they were attenuated by
the two RC poles, fo1 and fo2 at far offsets.
DESIGN RESULTS
A.
Noise and Dynamic Analysis using PLL Design
Assistant
The proposed frequency synthesizer specifications to
meet the WiMAX system requirements are shown in Table
2 below.
Fig. 8 Output Phase Noise of Synthesizer
TABLE II
DESIGN PARAMETERS OF WIMAX SYNTHESIZER
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The magnitude of the frequency peaking and the amount
of overshoot in the step response are dependent on the
selected fz / fo ratio. A large loop bandwidth helps reduce
the loop filter capacitance and suppress the in-band VCO
noise. However, the suppression of the ∑-∆ noise imposes
an upper constraint on the loop bandwidth. To suppress ∑∆ noise at high frequencies and reduce the reference spur,
two parasitic poles were added on purpose. The
implementation is fairly easy; by cascading two RC filters.
The synthesizer design also incorporates a second order
lead/lag filter with frequency response of:
(
Fig. 9 Closed Loop Step Response
)
(
)
(
)
(3)
where j is √(-1), and ω is frequency in radians. The loopfilter zero frequency, f_z, is 31.25 kHz; its pole frequency,
f_p, is 543.2 kHz; and its integrator capacitance, C_3 is
0.33nF. In this case, there is no loading effect between the
filters since the approach exercised is behavioral
simulation.
In this work, the Tristate design for PFD implementation
is chose in view of the fact that XOR-based approach has
the disadvantage of producing high detector noise from the
charge pump as well as higher reference spurs in the PLL
output phase noise. The Tristate design produces narrow
pulses inducing the charge pump to be on for a small time
interval of the reference cycle, thus reducing charge pump
noise and reference spur feedthrough [5]. However, any
mismatch between the up and down paths of its output
degrades the linearity of its phase error characteristic, and
in this case, a delay of 2.5ns was inserted in the reset path
of its registers to avoid dead zone problems. The XORbased PFD has an identical model to that of the tristate
topology except that its gain is increased by a factor of 2
[5].
Unlike integer-N PLL, the reference frequency of ∑-∆
fractional-N PLL can be much larger than the frequency
resolution (125 kHz). With reference frequency of 35 MHz,
the divide value would be N = 73.3143. The PLL in-band
noise enhancement is 20log(N) = 37.3dB. The rms jitter
obtained through PLL Design Assistant is 1.488ps, which
is equivalent to 0.6875°. The ∑-∆ topology chosen for this
work is the third order MASH 1-1-1 architecture which is
commonly used and charge pump operates at 100µA. A
loop bandwidth of fc = 250 kHz is adopted to take
advantage of the fractional-N architecture. The fz / fo ratio
chosen for the closed loop function is 1 / 8. Practical
designs set the value of fz / fo to be in the range of 1 /10 to
1 / 3 [9].
Fig. 9 estimates the settling time of
approximately 15 µs; faster than the required 50µs by a
good margin.
B.
CppSim Dynamic Simulation and Analysis
Feeding the parameters listed in Table 2 using the stated
PLL configuration into the C++ simulator yields a circuit
whose top level circuit blocks are as shown in Fig. 10. A
constant reference frequency, 35MHz and feedback signal
from the VCO divider are connected to the inputs of PFD.
The up and down output of the PFD are used to turn on the
pump-up and pump down current sources. In this
simulation, the loop filter consists of leadlag filter and two
rc filters. The VCO and divider are combined into one
computation block [3]. A step input is fed into the ∑-∆
modulator to observe the settling dynamics and cycle
slipping which will be shown shortly. The simulation
sampling frequency is 1/Ts = 700 MHz, a factor of 20
higher than the reference frequency.
The dynamic behavior of the PLL was analyzed using
CppSim. Firstly, step response result comparison is made
between PLL Design Assistant and CppSim to prove the
compatibility. Fig. 11 shows the step response simulated
using CppSim. VCO input, vin node was probed to observe
the transient response. It is then compared to the step
response produced by the PLL Design Assistant. Both of
the obtained results using PLL Design Assistant and
CppSim matches relatively well which have a settling time
of within 20µs.
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Fig. 10 Schematic View of Sigma-Delta Fractional-N PLL using CppSim
slip many times before re-acquiring frequency lock.
CppSim is used to estimate the nonlinear behavior of
cycle slipping. When an instantaneous phase error is
presented to the phase detector, then cycle slipping can
occur [10]. The PLL output responds to the variations at the
∑-∆ modulator’s input. The step size of 2 was chosen large
enough to knock the synthesizer out of frequency lock, to
illustrate the nonlinear reaction of the PLL. In this case, the
step was given at 50µs as shown in Fig. 12. It causes the
synthesizer out of lock, causing the effects of cycle
slipping. It eventually returns to a locked state within the
interval time of approximately 30µs. Simulations
furthermore show that synthesizer require more time to
relock when larger step of size 4 was introduced as shown
in Fig. 13.
Fig. 11: Closed Loop Step Response using CppSim
C.
CppSim Cycle Slipping Simulation and Phase
Noise Analysis
Next, the impact of increasing the divider step value is
observed so that the PLL loses frequency lock and creates a
condition of cycle slipping. This non linear condition is not
able be predicted by PLL Design Assistant as it assumes a
linearized PLL model. As discussed in [5], this linearized
model can be used to analyze the “small signal” dynamic
properties of the PLL as well as its noise performance.
Hence, only variations in the PLL frequency caused by
small changes in the divide value are considered. If the
divide value is stepped by a large value, the PLL will cycle
Fig. 12 Cycle Slipping Step Response using CppSim with Step
Size of 2
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Fig. 15 Output Phase Noise using PLL Design
Assistant with Detector Noise turned off
Fig. 13 Cycle Slipping Step Response using CppSim with Step
Size of 4
The results of noise simulation of the ∑-∆ fractional-N
PLL are shown in Fig. 14 with constant input to the ∑-∆
modulator. The plot shows the simulated output noise
spectral density, with simulation frequency 1/Ts set to 20
times the reference frequency. The simulated phase noise
plot has a large amount of variance compared to their high
frequency counterparts due the low frequency portion have
a very few points. Moreover, the employed spectral density
calculation method is quite inaccurate [3]. The simulation
results are in good qualitative agreement with the result
shown in Fig. 15, which uses PLL Design Assistant,
illustrating total phase noise with detector noise (dominates
at low frequencies) turned off. It represents a first attempt
and preliminary information on the sensitivity of the results
to various model parameters has been obtained.
VII.
CONCLUSION
There are several types of PLL-based frequency
synthesizer that can be utilized in the WiMAX system. In
this paper, a ∑-∆ fractional-N PLL is selected to meet the
tight requirement from WiMAX specification. A behavioral
simulation of the ∑-∆ fractional-N PLL is implemented in
this work. The behavioral simulation results using CppSim
program (C++ simulator) shows a settling time about 17µs
and integrated phase noise of less than 1°rms. The design
results outlined in this paper can guide designers in
designing and simulating the behavior of a ∑-∆ fractionalN PLL in order to achieve high noise performance, fast
settling time, and high resolution.
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