Chapter #8: Finite State Machine Design
Contemporary Logic Design
8-1
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Reset
0
Even
[0]
1
0
1
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next State
Even
Odd
Odd
Even
Output
0
0
1
1
Symbolic State Transition Table
Odd
[1]
State
Diagram
Present State
0
0
1
1
Input
0
1
0
1
Next State
0
1
1
0
Output
0
0
1
1
Encoded State Transition Table
8-2
Next State/Output Functions : NS = PS xor PI;
Input
NS
Input
D
Q
R
Q
Q
R
Output
Q
\Reset
\Reset
T FF Implementation
D FF Implementation
Input
T
CLK
PS/Output
CLK
OUT = PS
1
0
0
1
1
0
1
0
1
1
1
0
Clk
Output
1
1
1
0
1
1
0
0
1
0
1
1
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
8-3
Basic Design Approach: Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state mininimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3, 4, 5 covered later;
4, 5 generalized from the counter design procedure
8-4
Example: Vending Machine FSM
General Machine Concept:
- deliver package of gum after 15 cents deposited
- single coin slot for dimes, nickels
- no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
N
Coin
Sensor D
Vending
Machine
FSM
Reset
Open
Gum
Release
Mechanism
Clk
8-5
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
- three nickels
- nickel, dime
- dime, nickel
- two dimes
- two nickels, dime
Reset
S0
N
S1
D
S2
Draw state diagram:
N
D
N
D
Inputs: N, D, reset
S4
S5
S6
[open]
[open]
[open]
S3
Output: open
N
D
S7
S8
[open]
[open]
8-6
Step 3: State Minimization
Reset
Present
State
0¢
N
0¢
5¢
D
N
5¢
10¢
D
N, D
10¢
15¢
[open]
15¢
reuse states
whenever
possible
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
8-7
Step 4: State Encoding
Present State
Q1 Q0
0
0
0
1
1
0
1
1
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
Output
Open
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
8-8
Step 5. Choose FFs for implementation
Q1
Q1 Q0
DN
Q1
Q1 Q0
DN
Q1 Q0
DN
N
D
N
N
D
D
Q0
K-map for D1
Q1
D
D1
Q0
K-map for D0
D
CLK
Q0
N
R
Q
Q1
Q
\ Q1
Q1
Q0
K-map for Open
D1 = Q1 + D + Q0 N
\reset
N
\ Q0
OPEN
Q0
\N
D0
Q1
N
Q
D
CLK
RQ
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
Q0
\ Q0
\reset
Q1
D
8 Gates
8-9
Step 5. Choosing FF for Implementation
J-K FF
Present State
Q1 Q0
0
0
0
1
1
0
1
1
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
J1
0
0
1
X
0
1
1
X
X
X
X
X
X
X
X
X
K1
J0 K 0
X
X
X
X
X
X
X
X
0
0
0
X
0
0
0
X
0
1
0
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
0
0
0
X
Remapped encoded state transition table
8-10
J1 = D + Q0 N
Q1 Q0
DN
Q1
Q1
Q1 Q0
DN
N
D
K1 = 0
N
J0 = Q0 N + Q1 D
D
Q0
K-map for J1
Q1
Q1 Q0
K0 = Q1 N
Q0
K-map for K1
Q1
Q1 Q0
DN
DN
N
N
J
D
\ Q0
D
D
N
Q0
Q0
K-map for K0
Q0
K-map for J0
CLK
Q
KRQ
Q1
\ Q1
N
OPEN
Q1
D
CLK
\ Q1
N
\reset
J
Q
Q0
K
Q
\ Q0
R
7 Gates
8-11
Moore Machine
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
Outputs are function
solely of the current
state
State
Feedback
Outputs change
synchronously with
state changes
State
Register
Xi
Inputs
Comb.
Logic for
Outputs
Combinational
Logic for
Next State
(Flip-flop
Inputs)
Outputs depend on
state AND inputs
Zk
Outputs
Clock
state
feedback
Mealy Machine
Input change causes
an immediate output
change
Asynchronous signals
8-12
State Diagram Equivalents
Mealy
Machine
N D + Reset
(N D + Reset)/0
Reset/0
Reset
Moore
Machine
0¢
0¢
[0]
Reset
Reset/0
N
N/0
5¢
5¢
N D/0
ND
D/0
D
[0]
N
N/0
10¢
10¢
D
D/1
[0]
N D/0
ND
N+D
N+D/1
15¢
15¢
[1]
Reset/1
Outputs are associated
with Transitions
Reset
Outputs are associated
with State
8-13
States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
Same I/O behavior
Different # of states
0/0
0
0
[0]
0
1/0
0/0
1
0
1
1
1/1
[0]
1
2
[1]
1
Equivalent
ASM Charts
8-14
Timing Behavior of Moore Machines
Reverse engineer the following:
X
X
\B
J Q
C
KR Q
FFa
A
Input X
Output Z
State A, B = Z
\A
\Reset
Clk
X
X
\A
J Q
C
KR Q
FFb
Z
\B
\Reset
Two Techniques for Reverse Engineering:
• Ad Hoc: Try input combinations to derive transition table
• Formal: Derive transition by analyzing the circuit
8-15
Behavior in response to input sequence 1 0 1 0 1 0:
100
X
Clk
A
Z
\Reset
Reset
X =1
X =0
X =1
X=0
X =1
X=0
X=0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00
A B
0 0
Partially Derived
State Transition
Table
0 1
1 0
1 1
X
0
1
0
1
0
1
0
1
A+
?
1
0
?
1
0
1
1
B+
?
1
0
?
0
1
1
0
Z
0
0
1
1
0
0
1
1
8-16
Synchronous Mealy Machine
Clock
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
state
feedback
latched state AND outputs
avoids glitchy outputs!
8-17
Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications
Four Case Studies:
• Finite String Pattern Recognizer
• Complex Counter with Decision Making
• Traffic Light Controller
• Digital Combination Lock
We will use state diagrams and ASM Charts
8-18
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one
output (Z). The output is asserted whenever the input
sequence … 010… has been observed, as long as the
sequence 100 has never been seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010…
Z: 00010101000…
X: 11011010010…
Z: 00000001000…
8-19
Step 2. Draw State Diagrams/ASM Charts for
the strings that must be recognized ( 010 , 100).
S0
[0]
Outputs 1
Reset
S1
[0]
S4
[0]
S2
[0]
S5
[0]
S3
[1]
S6
[0]
Moore State Diagram
Reset signal places
FSM in S0
Loops in State
8-20
Exit conditions from state S3: have recognized … 010
if next input is 0 then have … 0100!
if next input is 1 then have … 0101 = … 01 (state S2)
S0
[0]
Reset
S1
[0]
S4
[0]
S2
[0]
S5
[0]
S3
[1]
S6
[0]
8-21
Exit conditions from S1: recognizes strings of form … 0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form … 1 (no 0 seen)
loop back to S4 if input is 1
S0
[0]
Reset
S1
[0]
S4
[0]
S2
[0]
S5
[0]
S3
[1]
S6
[0]
8-22
S2, S5 with incomplete transitions
S2 = … 01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = … 10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
S0
[0]
Reset
S1
[0]
S4
[0]
S2
[0]
S5
[0]
S3
[1]
S6
[0]
Final State Diagram
8-23
Review of Process:
• Write down sample inputs and outputs to
understand specification
• Write down sequences of states and
transitions for the sequences to be
recognized
• Add missing transitions; reuse states as
much as possible
• Verify I/O behavior of your state diagram
to insure it functions like the specification
8-24
Complex Counter
A sync. 3 bit counter has a mode control M.
if M = 0, the counter counts up in the binary sequence.
if M = 1, the counter advances through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)
001
010
110
111
101
110
111
8-25
One state for each output combination
Add appropriate arcs for the mode control
S0
[000]
Reset
S1
[001]
S2
[010]
S3
[011]
S4
[100]
S5
[101]
S6
[110]
S7
[111]
8-26
Digital Combination Lock
"3 bit serial lock controls entry to locked room.
Inputs are RESET, ENTER, 2 position switch for bit
of key data.
Locks generates an UNLOCK signal when key
matches internal combination. ERROR light
illuminated if key does not match combination.
Sequence is:
(1) Press RESET
(2) enter key bit
(3) Press ENTER
(4) repeat (2) & (3) two more times.
8-27
Problem specification is incomplete:
• how do you set the internalcombination?
• exactly when is the ERROR light asserted?
Make reasonable assumptions:
• hardwired into next state logic vs. stored in internal
register
• assert as soon as error is detected vs. wait until full
combination has been entered
Our design: registered combination plus error after full
combination
8-28
Understanding the problem: draw a block diagram …
RESET
Operator Data
ENTER
UNLOCK
KEY-IN
Combination
Lock FSM
Internal
Combination
ERROR
L0
L1
L2
Inputs:
Reset
Enter
Key-In
L0, L1, L2
Outputs:
Unlock
Error
8-29
Reset + Enter
Equivalent State Diagram
Reset
Start
Reset • Enter
Comp0
KI = L0
KI ° L0
Enter
Enter
Idle0
Idle0'
Enter
Enter
Comp1
KI = L1
Error1
KI ° L1
Enter
Enter
Idle1
Idle1'
Enter
Enter
Comp2
KI = L2
Reset
Done
[Unlock]
Reset
Start
Error2
KI ° L2
Error3
[Error]
Reset
Reset
Start
8-30