BULETINUL INSTITUTULUI POLITEHNIC DIN IAŞI
Publicat de
Universitatea Tehnică „Gheorghe Asachi” din Iaşi
Tomul LV (LIX), Fasc. 2, 2009
SecŃia
AUTOMATICĂ şi CALCULATOARE
SOME CONSIDERATIONS ON THE SYNTHESIS OF
SEQUENTIAL LOGIC SYSTEMS USING SET-RESET
FLIP-FLOPS
BY
ALEXANDRU VALACHI, BOGDAN AIGNĂTOAIEI,
MIHAI TIMIŞ and *ADRIAN BABAN
Abstract. The synthesis and implementation of Finite Automata (FA) can be
accomplished using various flip-flops (R-S, J-K, D, T). Usually, for SET-RESET (R-S)
flip-flops, in technical literature, it is considered the case of circuits for which the data
inputs can not be activated simultaneously (Rn*Sn = 0) [2]. In this paper we will take in
consideration all types of R-S circuits (SET-Dominant, RESET-Dominant,
unsimultaneously activation of R-S inputs).
Key words: Finite Automata, Flip-Flop, Moore Machine, Mealy Machine.
2000 Mathematics Subject Classification: 94C10.
1. Introduction
In technical literature ([1], [2]), the synthesis of sequential logic
systems is performed using R-S flip-flops for which the data inputs (R-S) can
not be activated simultaneously.
Fig. 1 presents the architecture of a synchronous sequential system,
implemented with Set-Reset flip-flops (with dotted line – Mealy/Moore
machine).
In technical literature [3], are considered three types of SET-RESET
flip-flops:
a) SET-Dominant flip-flop (DS);
b) RESET-Dominant flip-flop (DR);
c) R-S inputs unsimultaneously activated (Rn*Sn = 0).
The equation for flip-flop circuits is deducted from the excitation table.
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Fig. 1 − Mealy/Moore machine implemented with R-S flip-flops.
1.1. SET-Dominant Flip-Flop (DS)
In Table 1, it is presented the excitation table of the flip-flop circuit and
the corresponding output function.
Table 1
The Excitation Table for the R-S Flip-Flop (SET-Dominant)
Sn
Rn
Qn+1
Q n+1
0
0
Qn
Qn
HOLD
0
1
0
1
RESET
1
Ф
1
0
SET
Operation
Based on elementary logical calculations, it results:
(1)
Qn+1 =  S + R + Q  .

 n
A possible implementation is presented in Fig. 2 (SET-Dominant
LATCH) and in Fig. 3 (the synchronous version).
Fig. 2 – SET-Dominant LATCH.
Bul. Inst. Polit. Iaşi, t. LV (LIX), f. 2, 2009
67
Fig. 3 – Synchronous SET-Dominant LATCH.
In this paper, the following notations are used:
a) tpLH – the propagation time in an elementary logic circuit of the input
variable, if the output variable varies from Low -> High;
b) tpHL – the propagation time in an elementary logic circuit of the input
variable, if the output variable varies from High -> Low.
By propagation time is defined the duration of the interval between
activation of inputs commands and stabilisation of the outputs (Fig. 4), [1], [2].
Fig. 4a – Definition of propagation time
for asynchronous LATCH variant.
Fig. 4b – Definition of propagation time
for synchronous LATCH variant.
In the case of two variants we have (using the definition):
{
}
tb = MAX 2t pHL + t pLH ,2t pLH + t pHL (asynchronous LATCH)
(2)
(
)
tb = 2 t pHL + t pLH (synchronous LATCH).
We noted with x and x , the minimum value and the maximum value
of x. The synthesis of sequential system is difficult using only these types of
flip-flops because the possible occurrence of hazard due to the restrictive
condition on the clock, [1];
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(3)
Alexandru Valachi et al.
tb < tw ≤ tb + tp (Qj → Rk , Ck ) .
In the combinational structure SLC1 (Fig. 1), it have been noted by
tp (Qj → Rk , Ck ) , the minimum propagation time of the Qj variables.
In order to eliminate this inconvenience, Master-Slave (M-S) flip-flops
are used with the architecture illustrated in Fig. 5.
Fig. 5 – Master-Slave (M-S) Flip-Flop Architecture (DS).
The M-S circuit is composed of two flip-flops - LATCH (noted by the
“S” indicates that the flip-flops has SET-Dominant type).
Transition state functionality: If Ck = 0, the R-S inputs of the circuit
(M) are blocked, at the same time the outputs QM, QM are connected to input S,
respectively R (Q=QM, Q = QM ).
After the rising edge of the clock Ck, the inputs (R,S) of the Master
Flip-Flop are connected. In the same time, the propagation time switches and
the inputs (R,S) of the Slave Flip-Flop are disconnected; this state is maintained
as long as Ck is High. At the falling edge of the Ck signal the (R,S) inputs of the
Master Flip-Flop are disconnected, while the (R,S) inputs of the Slave Flip-Flop
are connected, the latest switching to the M latched state (M → S transfer).
The circuit is presented in Fig. 6 (the R-S Flip-Flop with falling edge
switching).
Fig. 6 – R-S Flip-Flop representation of a switch on
the falling edge of the clock Ck signal.
Bul. Inst. Polit. Iaşi, t. LV (LIX), f. 2, 2009
69
1.2. RESET-Dominant Flip-Flop (DR)
The excitation table for this type of flip-flop is presented bellow.
Table 2
The Excitation Table for the R-S Flip-Flop (RESET-Dominant)
Sn
Rn
Qn+1
Q n+1
Operation
0
0
Qn
Qn
HOLD
1
0
1
0
SET
Ф
1
0
1
RESET
It can be observed that if S, R are simultaneously activated (S = R = 1),
the flip-flop reset occurs (Q = 0, Q = 1). The equation deduced from the
excitation table is:
(4)
[
]
Qn +1 = R + S + Q n .
A possible implementation is presented in Fig. 7 a - Asynchronous
RESET-Dominant LATCH - and Synchronous RESET-Dominant LATCH as in
Fig. 7b.
a
b
Fig. 7 − RESET-Dominant LATCH (a); synchronous RESET-Dominant LATCH (b).
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Alexandru Valachi et al.
The propagation time is defined by relation (2). The use of flip-flops in
the synthesis of the sequential systems is difficult because of the restrictive
condition (3). The MASTER-SLAVE (M-S) circuits will be defined like as a
SET-Dominant R-S Flip-Flops, having the architecture presented in Figs. 8 a
and 8 b.
a
b
Fig. 8 – MASTER-SLAVE Flip-Flop RESET-Dominant Architecture (a);
MASTER-SLAVE Flip-Flop RESET-Dominant Scheme (b).
1.3. R-S Inputs Unsimultaneously Activated (Rn*Sn = 0)
In this case, the excitation table from Table 3 is considered.
Table 3
Excitation Table of SET-RESET (R-S) Flip-Flop
with R, S Inputs Unsimultaneously Activated
Rn
Sn
Qn+1
Q n+1
Operation
0
0
Qn
Qn
HOLD
0
1
1
1
0
1
1
0
Ф
0
1
Ф
SET
RESET
FORBIDDEN
Bul. Inst. Polit. Iaşi, t. LV (LIX), f. 2, 2009
71
From Table 3, the following relation results:
(5)


Q n +1 =  S + R + Q 

n
Rn * Sn = 0
It can be observed that is the same relation as in the case of R-S FlipFlop (DS – SET-Dominant). The restrictive condition on the R, S data inputs is
that the two inputs can not be activated in the same time. The MASTERSLAVE and also the asynchronous and synchronous LATCH types are
similarly defined.
2. The Synthesis of a Sequential System Using the SET-RESET Flip-Flop
2.1. SET-RESET Flip-Flop (SET-Dominant)
From Eq. (1), the Eqs. (6) and (7) are derived.
(6)
Qn = 0 ⇒ Qn + 1 = Sn + Rn + 0 = S n,
so Sn = Qn + 1 and Rn = φ
(7)
Qn = 1 ⇒ Qn + 1 = Sn + Rn + 1 = Rn * S n,
or Sn = Qn + 1 , Rn = 1
Based on Dn = Qn + 1 (D Flip-Flop), [1], [2], it results that Sn = Dn ,
Rn = 1 (Fig. 9).
Fig. 9 – D type Flip-Flop.
2.2. SET-RESET Flip-Flop (RESET-Dominant)
From relation (4), the Eqs. (8) and (9) are obtained.
(8)
Qn = 0 ⇒ Qn + 1 = Rn + Sn + 0 = Sn * Rn
or Rn = Qn + 1 , Sn = 1
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(9)
Alexandru Valachi et al.
Qn = 1 ⇒ Qn + 1 = Rn + Sn + 1 = Rn
or Rn = Qn + 1 , Sn = φ
Based on Dn = Qn + 1 (D Flip-Flop with negative input), it results that
Sn = 1 , Rn = Qn + 1 = Dn (Fig. 10).
Fig. 10 – D Flip-Flop with negative input.
It can be observed that the implementation represents the synthesis of a
sequential system using a D Flip-Flop.
2.3. SET-RESET Flip-Flop with Unsimultaneously
Activated Inputs (Rn*Sn = 0)
Based on Eq. (5), the results from Eqs. (10) and (11) are derived.
(10)
(11)
Qn = 0 ⇒ Qn + 1 = S n , so Sn = Qn + 1 and Rn is determined by the
relation (R * S)n = 0, meaning that, if Sn = 0 , we choose Rn = φ
and for Sn = 1 , we choose Rn = 0 (we denote Rn = Ф*).
Qn = 1 ⇒ Qn + 1 = S n * Rn and Rn * Sn = 0 or
Qn + 1 = S n * Rn + Sn * Rn = Rn , so Rn = Qn + 1 and Sn = Ф*
3. Example for Synthesis of a Sequential System
We consider the sequential system Mealy, with the state transition
graph (Fig. 11) [1].
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73
Fig. 11 − State Transition Graph (Museum problem – see [1]).
3.1. Synthesis of the D Flip-Flop System
As we observed earlier, the problem is equivalent to the D Flip-Flop
synthesis. Using the classic methodology [1], [2], we will draw the state
transition table followed by the excitation and output tables; prior to that the
states are encoded and finally the relations for the Dj data inputs and Zk outputs
are obtained (Tables 4 and 5).
Table 4
State Transition Table
Qn+1/Z1Z0
x1x0
Qn
1
2
3
4
(Q1Q0)n
00
01
11
10
00
01
11
10
1/00
1/10
1/00
1/01
1/00
1/00
4/00
4/00
2/00
2/00
3/00
3/00
3/00
2/00
3/00
Ф/ФФ
Table 5
Excitation/Output Table
(Q1Q0)n+1
Q 1Q 0
00
01
11
10
x1x0
(Z1Z0)n
00
01
11
10
00
01
11
10
00
00
00
00
00
00
10
10
01
01
11
11
11
01
11
ФФ
00
10
00
01
00
00
00
00
00
00
00
00
00
00
00
ФФ
Based on the output table, Eq. (12) results:
(12)
Z1 = Q 1Q0 x 1 x 0
Z0 = Q1 Q 0 x 1 x 0
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Alexandru Valachi et al.
The Veitch – Karnaugh (V-K) tables allowing the input data synthesis
are presented in Table 6 (Dj=Qj,n+1).
Table 6
The Veitch – Karnaugh tables for Dj
D1
Q 1Q 0
00
01
11
10
x1x0
D0
00
01
11
10
00
01
11
10
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
Ф
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Ф
Based on all above, the relations (13) and implementation from Fig. 12
are established.
(13)
D1 = x1 x 0 Q 0 + Q1(x1 + x0)
D0 = x 1
Fig. 12 – D Flip-Flop implementation.
3.2. Synthesis of the R-S Flip-Flop Systems with Unsimultaneously
Activated Inputs
As mentioned above, the Eqs. (10) and (11) are used to draw the Veitch
– Karnaugh (V-K) tables of the Rj and Sj inputs (Table 7). This approach allows
Bul. Inst. Polit. Iaşi, t. LV (LIX), f. 2, 2009
75
the synthesis of these signals with a lower cost (Fig. 13).
Table 7
Veitch – Karnaugh (V-K) Tables for Rj and Sj
S1
Q 1Q 0
x1x0
00
01
11
10
(14)
R1
S0
R0
00
01
11
10
00
01
11
10
00
01
11
10
00
01
11
10
0
0
0
0
0
0
Ф
Ф
0
0
Ф
Ф
1
0
Ф
Ф
Ф
Ф
1
1
Ф
Ф
0
0
Ф
Ф
0
0
0
Ф
0
Ф
0
0
0
0
0
0
0
0
1
Ф
Ф
1
1
Ф
Ф
Ф
Ф
1
1
Ф
Ф
1
1
Ф
0
0
0
0
0
0
0
Ф
S1 = x 1 x 0 Q 0
S0 = x 1
R1 = x 1 x 0
R0 = x 1
Fig. 13 – R-S Flip-Flop implementation.
4. Conclusions
1. Architecture and equations of set-dominant and reset-dominant flipflops are presented in the paper.
2. It was demonstrated that the synthesis of the sequential systems using
R-S Flip-Flop (DS) or R-S Flip-Flop (RS) represents in fact the D Flip-Flop
synthesis.
3. There were presented two examples of synthesis: based on D FlipFlop and based on R-S Flip-Flop (R, S unsimultaneously activated) with a lower
cost.
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Alexandru Valachi et al.
4. Synthesis with D and R-S Flip-Flop are recommended, but for lower
cost R-S Flip-Flop must be taken into account.
Received: April 15, 2009
“Gheorghe Asachi” Technical University of Iaşi
Department of Computer Science
and Engineering
e-mail: avalachi@cs.tuiasi.ro
and
* Continental Automotive Romania SRL
e-mail: adrian.baban@continental-corporation.com
REFERENCES
1. Valachi Al., Onofrei V., Hoza Fl., Silion R., Analysis, Synthesis and Testing of
Digital Devices. Nord-Est, 1993.
2. Roth Ch., Fundamentals of Logic Design. 4th Ed., West, St. Paul, MN, 1992.
3. Tinder R.F., Engineering Digital Design. Academic Press, 2000.
CÂTEVA CONSIDERAłII PRIVIND SINTEZA SISTEMELOR LOGICE
SECVENłIALE, UTILIZÂND CBB-URI DE TIP R-S
(Rezumat)
Implementarea sistemelor logice secvenŃiale poate fi realizată prin folosirea
diverselor tipuri de circuite basculante bistabile (CBB) ca R-S, J-K, D, T. În această
lucrare, autorii se limitează la folosirea CBB-urilor de tip R-S, în literatura de
specialitate fiind considerată sinteză cu bistabile cu intrările de date (R,S), neactivate
simultan ( Rn ⋅ S n = 0 ).
Elementul de originalitate îl constituie abordarea sintezei folosind circuite
basculante bistabile (R-S) cu intrările de date activate simultan, după cum urmează:
a) CBB R-S (Set Dominant), la care în cadrul activării simultane
( Rn = S n = 1 ), bistabilul va memora cifra binară “1”;
b) CBB R-S (Reset Dominant), la care în cadrul activării simultane
( Rn = S n = 0 ), bistabilul va memora cifra binară “0”.
În urma studiului realizat, se pot desprinde următoarele concluzii:
1) folosirea CBB R-S (Reset Dominant) sau (Set Dominant) se reduce la
implementarea cu CBB D;
2) se alege soluŃia cu cost minimal din cele două situaŃii; implementarea cu
CBB D sau CBB R-S cu intrări neactivate simultan.