8-bit Microprocessor
Project Report
Hassan Ilyas 2012-10-0041
Arsalan Akram Sandhu 2012-10-0099
Muhammad Usama 2012-10-0081
Project Overview
Microprocessors are among the most complex sequential circuits used today. Designing efficient
architectures is an ever green field of research. Newer architectures have to be tested at every stage of
the design. In modern design engineering VHDL is one of the most popular design applications used by
the designers. Emulating a microprocessor on VHDL is a good way to test the architecture of any
microprocessor.
The scope of this project was to implement an 8-bit microprocessor using VHDL, and then implementing
it on FPGA. We first simulated the design in modelsim. After the success of simulation, the VHDL was
implemented into FPGA. Assembler was designed that goes with our design. The register values are
visible on LEDs of the fpga. The current value of program counter is displayed on seven segment display.
Architecture
Instructions
We plan on including the following 15 Instructions in our Processor.
1. R-Type
a.
b.
c.
d.
e.
f.
2. I-Type
a.
b.
c.
d.
e.
f.
g.
3. J-Type
a.
b.
And
Or
Add
Sub
Slt
Jr
Andi
Ori
Addi
Beq
Bne
Lw
Sw
J
Jal
Instruction Formats

R-Type
4-bit opcode determines which instruction should be implemented. 3-bit values from Rs and Rt are from
input values from the two registers. ALU performs the desire operation and output is placed in register
Rd. Last 3-bits are ignored.
o
o
o
o
o
Op-Code 4-Bits

4-Bit Opcode
3-Bit Rs
3-Bit Rt
3-Bit Rd
Last 3 Bits Ignored
Rs 3-Bits
Rt 3-Bits
Rd 3-Bits
Ignored 3-Bits
I-Type
4-bit opcode determines which instruction should be implemented. 3-bit values from Rs and 6-bit
immediate value are the inputs and the result is stored in Rt.
o
o
o
o
Op-Code 4-Bits
 J-Type
4-Bit Opcode
3-Bit Rs
3-Bit Rt
6-Bit Immediate
Rs 3-Bits
o
o
o
Op-Code 4-Bits

Rt 3-Bits
Imm 6-Bits
4-Bit Opcode
8-Bit Jump Address
Last 4 Bits Ignored
Jump Address 8-Bits
K-Type
o 4-Bit Opcode
o 1-Bit for Read or Write
o Last 11 Bits Ignored
Op-Code 4-Bits
Read or Write 1-Bit Ignored 11-Bits
The truth table below shows the 15 instructions we have implemented in our project.
Ignored 4-Bits
Truth Table
And
Or
Andi
Ori
Add
Sub
Addi
Beq
Bne
Slt
J
Lw
Sw
nothing
Jal
Jr
OpCode
S3
S2
S1
S0
M
Cn
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
0
1
0
0
0
1
1
1
0
1
X
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
X
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
X
1
0
1
0
1
0
1
0
0
0
1
1
1
0
1
X
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
1
0
1
1
1
1
1
1
1
0
1
X
Reg Mem
Write Write
1
1
1
1
1
1
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Rx
0
0
1
1
0
0
1
X
X
0
X
1
1
0
1
X
PC+1
B or
Jal
Branch Immediate
Jump
000
0
0
000
0
0
000
1
0
000
1
0
000
0
0
000
0
0
000
1
0
010
0
0
011
0
0
000
0
0
100
1
0
000
1
0
000
1
0
000
0
0
100
1
1
100
0
0
Alu_Out
or Mem
0
0
0
0
0
0
0
0
0
0
0
1
0
0
X
0
Project Schematic
3
/
Control Unit
BEQ
BNE
Pc+1 ALU_Out Mem
Jal
Imm/Reg
B/Imm.
8
/
Rx
8
/ Pc+1+(Imm. / Reg)
PC
Input
8
/
1
New
PC
ALU_Out / Mem
ALU funct
Mem. Write
Reg Write
6
/
Imm/Reg
PC +1
8
/
PC +1
Adder
PC
8
/
8
/
4
/
8
/
Adder
Reg Write
3
/
Rs
Reg
Read1
3
/
Rt
Instruction 16
/
Memory
8
/
A
Reg
Read2
Memory
1st Input
8 ALU OUT
/
Register File
1
Rx
Rd 3
/
Rx
2
8
/
6
/
Imm/Reg
Zero
Flag
Opcode
Address
8
/
8
/
8
/
8
B/
Reg
Write
8
B/Imm. /
2nd Input
8
/
8
/
Imm.
PC+1
Jal
ALU Out
Memory
8
/
8
/
ALU Out
Memory
Data In
8
/
8
/
Address
ALU
Data
Sign
Ext.
Data Out
Design Details
Simulation Results
I/O of microprocessor:
Inputs:
3-bit Register Select: Switches on the board are used to select any register to be displayed on the LEDs.
1-bit Program Counter Select: Selects MSBs or LSBs of the program counter.
Outputs:
8-bit Register Value: LEDs display any register value.
4-bit counter Value (Seven Segment Display): Program counter value is displayed on seven segment
display.
Features
ALU
The Arithmetic Logic Unit (ALU) provides all the simple operations expected in an 8-bit processing unit.
All operations are performed using an operand provided by any register. The result is returned to the
same register. For R-type instructions there are three registers Rs, Rt and Rd. It takes inputs from Rs and
Rt, perform operations and the result is stored in Rd which is the destination register. For the
implementation of I-type instructions Rs is the input register and there is an immediate value given and
the output is stored in Rt register.
JUMP
Under normal conditions, the programs counter (PC) increments to point to the next instruction. The
address space is fixed to 256 locations (00 to FF hex), making the program counter 8-bits wide. The top
of the memory is FF hex and will increment to 00.The JUMP instruction is used to modify the sequence
by specifying a new address. However, the JUMP instruction can be conditional. A conditional JUMP is
only performed if a test performed on either the ZERO flag or CARRY flag is valid. The JUMP instruction
has no effect on the status of the flags. Each JUMP instruction must specify the 8-bit address as a twodigit hexadecimal value. The assembler supports labels to simplify this process
Flags/Program Flow Control
The ALU operation results affect the ZERO and CARRY flags. Using conditional and non-conditional
program flow control instructions, this information determines the execution sequence of the program.
JUMP commands specify absolute addresses within the program space.
Some complications in the project
Clock synchronization:
Microprocessor includes a universal clock, and this has to be distributed to every component. It is really
important that the clock event is synchronized to give the right output.
DFF:
Xilinx FPGAs allow DFFs with only one synchronized clock and only two latch inputs. So no signal should
be set on two separate clock events. We had to define a lot of new signals to get over this error.