Vol. 15 | SEPTEMBER 2014
ISSN-2095-1563
Journal of The International Association of Advanced Technology and Science
Modeling of 8255 Programmable Peripheral
Interface Using VHDL
KINSHUK DUDEJA
AISHWARYA KHARBANDA
Abstract:
The 8255 Programmable Peripheral interface (PPI) is a general purpose I/O interface to connect
peripheral equipment a microcomputer system bus.it contains 3I/O Ports which can be programmed in
different modes and to program the fuction to all three I/O ports it contains a register called as control
register.it is a general purpose in nature and provides many facilities for connecting different devices . The
core’s functional configuration is designed by VHDL code anddesigned input signal (Test bench) for PPI
8255, which is generated by VHDL code. It has 3,8 bit ports port A, port B and port C .which are
arranged in two groups of 12 pins. three programming modes for Peripheral Ports:Mode 0(simple I/O)
Mode 1 (strobed I/O) and Mode 2(strobed bi-directional I/O).
Keywords
VHDL, PPI, 8255, MOS
INTRODUCTION
The 8255 PPI The 8255 Programmable Peripheral Interfacechip is a peripheral chip originally developed
for the Intel8085 microprocessor, and as such is a member of a largearray of such chips, known as the
MCS-85 Family. Microcomputers have developed into a powerful and versatile tool in today‟s industry
and research labs. In order to control a process by a microcomputer an interface must exist from the
microcomputer to the hardware being controlled. An interface can span from a simple to complex
design. The Intel 82C55A programmable peripheral interface component is used to interface hardware
to the microprocessor of a microcomputer.The Intel 8255A is a general purpose programmable I/O
device which is designed for use with all Intel and most other microprocessors . 24 I/O pins which may
be individually programmed in 2 groups of 12 and used in 3 major modes of operationIn MODE 0, each
group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In MODE 1, each
group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for
handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.The 8255
is a 40 pin integrated circuit (IC), designed to perform a variety of interface functions in a computer
environment. The 8255 wasn't originally designed to be connected to the Z80. It was manufactured by
Intel for the 8080 microprocessor. This chipwas later also used with the Intel 8086 and its descendants. It
was later made (cloned) by many other manufacturers. It ismade in DIP 40 and PLCC 44 pins
encapsulated versions.This chip is used to give the CPU access to programmableparallel I/O, and issimilar
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to other such chips like theMotorola 6520 PIA (Peripheral Interface Adapter) the MOSTechnology 6522
(Versatile Interface Adapter) and the MOSTechnology CIA (Complex InterfaceAdapter) all developedfor
the 6502 family. Other such chips are the 2655Programmable Peripheral Interface from the Signe tics
2650family of microprocessors, the 6820 PIO (Periphera PIO(Peripheral Input/output) from the Motorola
6800 family, theWestern Design Center WDC 65C21, an enhanced 6520,and many others.
ABOUT VHDL
VHDL(VHSIC Hardware Description Language) is hardware description language used in
electronic design automation to describe digital and mixed signal system such as field
programmable gate arrays and integrated circuits . VHDL can also be used as a general purpose
parallel programming language. VHDL was originally developed at the behest of the U.S Department
of Defence in order to document the behavior of the ASICs that supplier companies were including
in equipment.The idea of being able to simulate the ASICs from the information in this
documentation was so obviously attractive that logic simulators were developed that could read the
VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and
output a definition of the physical implementation of the circuit.
II. OVERALL ARCHITECTURE AND DESCRIPTION:
A. PPI - Programmable Peripheral Interface
The 8255A programmable peripheral interface (PPI)implements a general-purpose I/O interface
to connectperipheral equipment to a microcomputer system bus. Thecore's functional
configuration is programmed by the systemsoftware so that external logic is not required to
interfaceperipheral devices.
Features:




3 8-bit IO ports PA, PB, PC
It is a programmable parallel I/O device.
TTL compatible.
PA can be set for Modes 0, 1, 2. PB for 0, 1 and PC formodev0 and for BSR. Modes 1
and 2 are interruptingdriven.
 PC has 2 4-bit parts: PC upper (PCU) and PC lower(PCL),each can be set.
Independently for I or O.
 Improved DC driving capability
• TTL compatible.
• Improved dc driving capability.In the SVI-328/318 the 8255 is used to strobe the keyboard
lines, to interface joystick fire button switch, the paddle and tocontrol the cassette tape system.
The following I/O ports areused to communicate with the PSG
Used to interface between 8255 data bus with system bus.
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Fig. 1 : Architecture of 8255 PPI
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Data Bus buffer:
It is a 8-bit bidirectional Data bus.
Used to interface between 8255 data bus with system bus.
The internal data bus and Outer pins D0-D7 pins are connected in internally.
The direction of data buffer is decided by Read/Control Logic.
Read/Write Control Logic:
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This is getting the input signals from control bus Address bus
Control signal are RD and WR
Address signals are A0.A1 ,and CS.
8255 operation is enabled or disabled by CS
Group A and Group B control:
Group A and B get the Control Signal from CPU and send the command to the individual
control blocks.
Group A send the control signal to port A and Port C (Upper) PC7-PC4.
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•
Group B send the control signal to port B and Port C (Lower) PC3-PC0.
PORT A:
This is a 8-bit buffered I/O latch.
It can be programmed by mode 0 , mode 1, mode 2 .
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•
PORT B:
This is a 8-bit buffer I/O latch.
It can be programmed by mode 0 and mode 1.
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SPORT C:
This is a 8-bit Unlatched buffer Input and an Output latch.
It is splitted into two parts.
It can be programmed by bit set/reset operation.
Operation modes:
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BIT SET/RESET MODE:
The PORT C can be Set or Reset by sending OUT instruction to the CONTROL registers.
I/O MODES:
MODE 0(Simple input / Output):
In this mode , port A, port B and port C is used as individually (Simply).
Features:
Outputs are latched , Inputs are buffered not latched.
Ports do not have Handshake or interrupt capability.
MODE 1 :(Input/output with Hand shake)
In this mode, input or output is transferred by hand shaking Signals.
Handshaking signals is used to transfer data between whose data transfer is not same
MODE 2:bi-directional I/O data transfer:
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•
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This mode allows bidirectional data transfer over a single 8-bit data bus using handshake signals.
This feature is possible only Group A
Port A is working as 8-biy bidirectional.
PC3-PC7 is used for handshaking purpose.
The data is sent by CPU through this port , when the peripheral request it.
CONTROL WORD FORMATS:
In the INPUT mode , When RESET is High all 24 pins (3-ports) be a input mode.
A Use 8255 PPI in VHDL programming
8255 PPI is used in VHDL; we use VHDL code as in input and togive the output in simulated
test bench waveform. As we knowthat, this is also perform in the matlab and P-spice
technologyand in this project we are using new advance technology calledVHDL to give
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simulated test bench waveform of 8255 PPI. Thecodes for the different modules are written in
VHDL and aresimulated using Xilinx ISE 9.1i.
Fig. 2: Pin diagram of 8255 PPI
The IC used for interfacing is the 8255 PPI. This chip is designedand manufactured by Intel.
The 8255 Interface Adapter is aprogrammable peripheral interface device designed for use
in microcomputer interfacing systems. It is a general purposeI/O device that can interface any
TTL compatible peripheraldevice to a microcomputer system. The 8255 has 24 pins of
I/O, programmable and configurable by software, in two groupsof 12 pins that are used in three
separate modes of operation(Brey, 1995). The Interface Adapter is selected by its CS line
for programming and for reading and writing to a port. Portassignment and register selection is
accomplished throughthe A1 and A0 pins. Table 2 shows the I/O port assignmentsused
programming and access the I/O ports (Rafiquzzaman,1995; Uffenbeck, 1998).
Table 2 : Function of Port A, B, C and CWR
B. Programming with 8255 PPI
The 8255 has 3 8-bit ports (A, B and C), each of which canhave a different I/O Status (i.e. input or
output). Port C canalso be programmed to operate in two halves. (As twoseparate 4-bit ports). The
functional configuration of eachport is programmed but the system software. In essence, the
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CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit
set", "bit reset",etc, that initializes the functional configuration of the 8255.There are 3 basic modes of
operation under which the portscan function. Mode 0 - Basic Input/ output Mode 1 - Strobed
input/output (Not used by SVI) Mode 2 - Bi-Directional Bus(Not used by SVI) in some of these modes
port C is used asa control/status port for port A or B. It can be used toconfirm when data transfer may take
place, and reflect anyother flags. The 8255 PPI is therefore supplied with theadded option for the user to
set or reset any individual bits inport C. The I/O status, mode of operation and bit setting isdefined by the
8255 PPI control byte.
Results obtained:
1. RTL View of 8255 PPI Architecture
Fig.
Fig. 3: RTL View of 8255 PPI Architecture
2. RTL View of 8255 PPI Core Internal
Fig. 4: RTL View of 8255 PPI Core Internal Architecture
3. RTL View of 8255 PPI Core Architectur
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Fig. 5: RTL View of 8255 PPI Core Architecture
Simulated Test bench Waveform 8255 PPI Architecture Mode 0
REFERENCES
[1] Harris Semiconductor, “CMOS programmable Peripheral Interface”,Product Specification, June 1998.
[2]. Paul, “8255 PPI IBM PC Interface Card”, Tutorial, Nov 2000.
[3] Intel, “Programmable Peripheral Interface”, Data Sheet, 1999.
[4] T.C. Manjunath, S. Janardhanan, N.S. Kubal, “Simulation, Design,Implementation and Control of a
Welding Process Using Micro –controller”, Paper presentation at Institute of Technology Bombay,Powai,
Mumbai.
[5] Pradeep Kumar Jaisal, Anant G. Kulkarni, “Design of Time TriggeredShared Bus Architecture Using
Very High Speed Integrated CircuitHardware Description Language (VHDL)”,Paper Published at
InternationalJournal of Electronics and Computers, Vol. 2, No. 2, pp. 353-364.
[6] . Pradeep Kumar Jaisal, Anant G. Kulkarni, “Design and Simulation of8255 Programmable Peripheral
Interface Adapter Using VHDL” paperpublished in IJCST Vol. 2, Issue 1, March 2011.
[7] Ramesh S. Gaonkar,”Microprocessor Architecture,Programming andApplication with 8085 ,”Wiley
Eastern Ltd.,5th Edition.
[8] D. E. Thomas and P. Moorby. The Verilog Hardware DescriptionLanguage. Kluwer Academic, 1991.
[9] IEEE. IEEE Standard VHDL Language Reference Manual. IEEE, 1988.
[10] Aldec active-hdl tools. www.aldec.co
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