International Conference on Engineering Trends and Science & Humanities (ICETSH-2015)
AN EFFICIENT PROPAGATION DELAY REDUCTION FOR
NANOMETER CMOS IC
R .UMA,
Mr.S.Rajendraprasad M.E MBA,
M.E VLSI design,
Assistant professor of ece,
Roever engineering college
Roever engineering college,
Elambalur.
Elambalur.
ABSTRACT
The design complexity of systems
created
standards
,and
configurability
on chip drive the need to reuse legacy is
provides flexible hardware on demand of
used
both standards without fabricating a new
for
gate
level
implementation
65 nm
chip.The long- term reliability of nanometer
technology is tested in one of bench mark
integrated circuits can reach the noteworthy
circuit C880 testing circuit. It’s used for
order
analyze single path delay estimation in
hours).Some of the main challenges driving
circuit. Its used for analyze multiple path
the design of reliable system( design for
delay estimation in the circuit. This delay
reliability) encompass soft error ,process
path estimation is analyzed one of the
variation and device aging phenomena, with
bench mark
the
needed.Its used for design of
circuit. Its tested under
of
103
FITs(failures
continuous
scaling
of
in
109
transistor
various multi path technology 65, 90 , 135
dimension ,device aging which cause the
nm technology
significant loss in the circuit and life time
Index terms: C880, reuse legacy,65nm
,delay estimation, path finding algorithm
1. INTRODUCTION
Fast
time-to-
reliability Concerns, therefore an early stage
design optimization in this problem.
Traditional design methods add
market
satisfies
industry designers to keep up with newly
ISSN: 2348 – 8549
becoming increasing dominant for temporal
guard bands or adopt worst case margins to
account for
aging phenomena which in
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International Conference on Engineering Trends and Science & Humanities (ICETSH-2015)
refer to over design and may be expensive
To
Conservative design, the mitigation of aging
for
induced, Aging effects. Recent aging aware
minimization of problem with consideration
techniques basically follow this formulation.
of aging effect.
The proposed a gate sizing algorithm based
on lagrangian relaxation. An Average of
8.7 % area penalty is required to ensure
reliable operation for 10 years.
A
Novel
avoid
conservative
overly
design
.The
area
In some works, complex gates are
converted to primitive gates prior to time
analysis thus applying
the test. Delay
model is designed model to basic gates .This
technology
mapper
methodology may be a source of in
considering signal probabilities NBTI was
accuracies since the
developed. The technique takes signal
simulation has a topology that differs from
probabilities as one of the argument when
the actual circuit structure being finally
searching for best matching in given
manufactured .Other works analyze the
standard cell library. On average 10% area
delay of complex gates through a transistor
recovery and 12 % power saving
are
level approach or using a current source
as compared to the most
model, providing good accuracy at cost of
pessimistic case assuming static NBTI an all
very complex expression that result in a
PMOS transistors design .A Frame work
slow computation time at the circuit level
using
or using current source model providing
accomplished
join logic restricting and pin
reordering can mitigate NBTI induced
performance
circuit
used
for
good accuracy at the cost of very accuracy.
The C88O is the one of the
Traditional design methods add
combinational digital circuitis used for
guard –bands or adopt worst case margins
analyze the number bench mark analysis the
to account for aging phenomena, which in
delay in the circuit. The delay is computed
practice refer to over design and may be
independently of specific input vector is
expensive .To avoid overly conservative
used for path sensization scheme.Most of
design ,the mitigation of aging induced
the paper analyze the delay in the bench
performance degradation problem is used
mark circuit.
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In
this
used
for
analyze
the
C880
.Circuit level analysis is used for fault in the
propagation delay in the bench mark circuit,
circuit, The rest of the paper is used for
We analyze the impact of sensization input
analyze testing of bench mark circuit, path
vector on the propagation delay for complex
delay estimation in the bench mark circuit
gates showing that delay variations may get
Section three explain the
up to 53% depending on the technology
estimation in the circuit the next section
used. We
bench mark circuit
provide an insight root causes
path delay
variation through the careful transistor
2.
COMPLEX
GATES
DELAY
VARIATION
Without loss of
All complex logic cell have more than
one
vector
2.1GATE-LEVEL ANALYSIS
input
that
sensitizes
generality
dependence with sensization input
delay
vector
the
using four logic complex gates. All this
propagation of each input and output. This
process analyzed one of standard logic
paper only analyze the delay variation
library cell the circuit. Four logic gates
between each of one stage. We only
consider the input and its function out the
consider the cases with steady values in all
two output.
inputs except the input being propagated
toward the output state.
Out = A ∗ B + C ∗ D (1)
Out = (A + B) ∗ C
Fig 1:AA022
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Fig 2:OA12
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Table 1: Propagation table
2.2PropagationTable
During the each phase the input is
analyzed on of the commercial tool is 65
analyzed without consider the path delay in
nm. This gates have the number of logical
the circuit. May have significant impact on
bench mark function. This i due to fact that
delay due to errornous in the circuit .Many
technology libraries include many complex
logic gate function analyzed for different
gates .This synthesis is used for reduce the
input and output .Truth table is analyzed for
area delay and power algorithm .
each vector propagation.The other two gates
are the CB416 and the AO1212(also known
2.4 Transistor level analysis
as A02ON and A010,respectively ) their
To analyze the impact of multiple
logic functions are given respectively given.
vector sensization at the circuit level, the
slowest pathes of ISCA85 bench mark
2.3Circuit level relevancy
circuits and compute the how many paths in
Multiple circuit level
analysis is
this circuit using CMOS technology.
Its
used for slowest path analysis; We take the
have multiple input gates and high lighting
C880 bench mark circuit at the circuit level.
the relevancy that this phenomenon might
Its used for multiple sensation in the input
have circuit level. This synthesis algorithm
side and compute the how many vectors at
is used for reduce the area and delay in the
the input side. This bench mark circuit
circuit.
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Fig 3: ISCAS85 bench mark circuit
3. DELAY MODEL, HEURISTIC AND
easily extended to accommodate additional
TOOL
variables. The analytical nature of the model
A
timing
analysis
tool
that
combines a specific delay model and
algorithm to find the true paths in a
combinational circuit. The delay model is
analytical through a polynomial model is
used to estimate both the gate propagation
provides some advantages over the widely
used
LUT
(Look-Up
Table)
based
approaches .The main advantages area faster
computation time due to interpolations
required by LUT methods and less memory
space required to the model data.
delay and the output transition time. Since
The electrical simulations from
latter is required to compute the propagation
which the model parameters are obtained are
delay of the next gate with in path .The
done systematically for a given technology
Second component of the timing analysis
library and consist of a set of iterative of
tool is the algorithm developed to find the
values for each variable considered ,for
true paths inCombinational circuit. Such an
which the propagation delay and output
algorithm is based RESIST algorithm and
transistion time for rising and falling input
was specifically consider the dependent
transition are between the stages of input
delay between input and output complex
and
vector counts.
maximum order each variable adjusted to
output
vector
monitoring.
The
during the extraction process to provide the
3.1 Delay model
desired accuracy in the estimation. An
The delay model includes multiple
application to perform the whole process
variables like input transition time, output
automatically determine the all sensization
load, temperature and supply voltage and
vectors for each gate input generating the
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scripts for the iterative electrical simulation
node of the sensitized gate becomes the new
and finally extracting the model parameters
current node and process is repeated.
from simulations
To perform this logic propagation step
In this work path finding algorithm
efficientlythe algorithm uses a logic system
that sensitizes the path while computing that
with semi –undetermined values that allow
its
The
identifying a logic incompatibility before all
algorithm preserves as different paths those
implied nodes are set to an input .A of an
having the same Course traversing the same
AND2 gate with an undetermined value to
sequence but using preserve sensization
the B inputs leads to a state that starts with
input and output circuit
an unknown logic value represent. This
traverse
through
the
circuit.
This algorithm starts at a circuit and
advances node to node until an output is
reached .If the node being analyzed has a
fan out greater than 1 or the next gate has
multiple sensitization vectors, the process
state is saved .If a logic in compatibility is
found ,all the paths that sharing the current
sub-path are discarded and the algorithm
jumps to the last saved point. If no
incompatibility is found,then the output
method leads to an increase in the algorithm
speed to trace all true paths and avoids
passing twice through the same paths .In this
proposed
system input vector monitoring
using bench mark circuit C880 This
algorithm is used for explore the all possible
input and output in the circuit. The input
vectors
for
each
path
,
unlike
the
commercial tool that only gives one input
vector for each input vector each true path .
Fig 5: Test circuit
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Itsused for estimate the delay due to the
RESULTS
The simulation the delay variation due to the
sensization vector to the delay variation
caused
by other
effects
like
process
parameter fluctuation or the inter connect
system. Such analysis is key is key to
determine the relative significance of this
phenomenon compared to other important
delay variation sources. We carried this
comparison for various combinational to
estimate the circuit,C880 circuit level.
inter connect system .We compared to the
nominal delay of the C880 circuit using
modelsim simulator from the electrical
stimulation. A Specific delay tool based on
analytical
delay
description
has
been
presented. It uses a single pass through the
circuit to get a list of true paths instead of
traditional two pass scheme. This allows the
tool to account for all sensitization vectors
in each complex gate and compute the gate
delay accurately
Fig 6:C880 testing circuit
CONCLUSION
The importance of considering
the input vector used to sensitize a complex
gate in the delay estimation.The delay
variations up to 15 for a 65nm technology
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4. S. Bose, P. Agrawal, and V. D.
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