9-1 Pin-outs and Pin Functions
EEB531 Microprocessor Systems
微處理機系統
8086 and 8088: 16-bit µPs
– Two modes: MN/MX
• 1: min (work with 8-bit peripherals)
• 0: max (if a coprocessor exists)
– require 8288 bus controller
(signals generated externally)
– dropped off after 80286
– Pin-out differences
• data bus width
– 8086: 16 bits (AD0-AD15)
– 8088: 8 bits (AD0-AD7)
• pin 28
– 8086 M/IO pin
– 8088 IO/M pin
• pin 34
– 8086 BHE/S7 pin
– 8088 SSO pin
吳俊興
高雄大學 資訊工程學系
– Power supply requirements
• +5.0V (~10%)
• fan-out: no more than 10 unit loads
– TTL74LS: 5 fan-outs
– CMOS/TTL74A(L)S: 10 fan-outs
May 2005
Outline
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Minimum Mode 8088 System
9-1 Pin-outs and Pin Functions
9-2 Clock Generator (8284A)
9-3 Bus Buffering and Latching
9-4 Bus Timing
9-5 Ready and the Wait State
9-6 Minimum Mode Verse Maximum Mode
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4
8088 Pin Connections
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•
•
•
Figure 9-19 Minimum Mode 8088 System
MN/MX: select either minimum or maximum mode
AD7-AD0: address if ALE=1, data if ALE=0
A15-A8: address bus
A19/S6-A16/S3: address/status bits (Table 9-4)
– S6: always 0
– S5: condition of IF flag bits
– S4 and S3: show which segment is accessed
•
•
•
•
•
•
•
•
CLK (clock): provide basic timing signals
Vcc/GND: power supply input
RESET: cause µP to reset itself if high for min 4T
RD (read signal): 0 if data bus is receptive to data
from memory or I/O devices connected to system
READY: 0 to cause 8088 enter into wait states
TEST: pin=1: cause WAIT instruction wait for 0;
pin=0: equal to NOP (used by 8087)
INTR: cause µP to enter an interrupt ack cycle when
IF=1
NMI (non-maskable interrupt, INT 2): enter interrupt
acknowledge cycle even if IF=0
9-2 Clock Generator (8284A)
9-3 Bus Buffering and Latching: de-multiplexing and buffering
9-4 Bus Timing
9-5 Ready and the Wait State
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9-2 Clock Generator (8284A)
8088 Minimum Mode Pins
• ALE (address latch enable): AD=address if 1
• IO/M: select IO or memory address bus
• DT/R (data transmit/receive): µP is transmitting
data if 1 or receiving data if 0
• WR (write line): 0 to indicate data bus contain valid
data for memory or IO
• DEN (data bus enable): activate external data bus
buffers
• INTA (interrupt ack): response to INTR input
• HOLD: cause µP to hold (wait for DMA)
• HLDA (hold ack): 8088 has entered the hold state
• SS0 (status): status (see Table 9-5)
• Basic functions: clock generation, RESET synchronization, READY
synchronization, and a TTL-level peripheral clock signal
– CLK output 1/3 crystal input frequency and 50% duty cycle
– RESET: goest high in 4 clocks
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8
The Buffered 8088 System
9-3 Bus Buffering and Latching
Fully buffered
• 2*74LS373 latch
•Common buses for computer systems
– address bus: provide the memory address and/or IO port #
– AD7-AD0
– A19/S6-A16/S3
– data bus: transfer data between µP and memory/devices
• 2*74LS244 octal buffer
– A8-A15
– control bus
– control bus: provide control signals
• 1*74LS245 bi-directional buffer
•Two system design issues with 8088/8086
– direction controlled by DT/R signal
– enabled/disabled by DEN
– Shared bus: de-multiplexing required
• address/data (ADx)
• memory address or I/O port number
– Limited fan-out: buffering for large systems
• increasing output currents
• incurring timing delay
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9-4 Bus Timing
Demultiplexing the Buses
Basic bus operations
for 8088 (simplified cycles)
•Writing data to memory
• Demultiplexing 8088
– Two 74LS373 latches
• AD7-AD0
• A19/S6-A16/S3
– µP outputs memory address
on address bus
– µP outputs data to be written
on data bus
– µP issues a write (WR) to
memory and IO/M=0
– Up-to 1MBytes (A0-A19)
– Enabled by ALE=1
• Demultiplexing 8086
– one more latch for AD8-AD15
•Reading data from memory
– µP outputs memory address
on address bus
– µP issues a read (RD) memory
signal
– µP accepts data via data bus
One bus cycle = 4 clocks
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Read
Timing
9-5 Ready and the Wait State
READY input: cause wait states for slower memory and I/O components
Time delay issues
– the amount of time
allowing the memory
or I/O to read the data
•8-bit shift register (74LS164) shifts a logic 0 for
0 or more clock periods
•strapping QB for one wait state
•RD,WR and INTA all 0 force CLR enabled
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READY and RDY Inputs
Write
Timing
• 8088’s READY input
– sampled at the end of T2 and again in the middle of Tw
– logic 0 delays one clocking period Tw(200ns for 5MHz clock)
• 8284A’s RDY input
1.All signals switch between VOH and VOL unless otherwise specified
2.RDY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted
3.Two INTA cycles run back-to-back. The 8088 local addr/data bus is floating during both INTA
cycles. Control signals are shown for the second INTA cycle
4.Signals at 8284 are shown for reference only
5.All timing measurements are made at 1.5V unless otherwise noted
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– RDY1*AEN1 + RDY2*AEN2 (= RDY1 for Figure 9-17)
– ASYNC: 1 for one stage, 0 for two stages
• two stages
– 1st positive edge captures RDY in the first FF
– 2nd negative edge of the clock captures the output of the first FF
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One-Wait State Generator
Enabled from the memory only for memory devices to insert waits
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Summary
Chapter 9 8086/8088 Hardware Specifications
9-1
Pin-outs and Pin Functions
9-2
Clock Generator (8284A)
9-3
Bus Buffering and Latching
9-4
Bus Timing
9-5
Ready and the Wait State
9-6
Minimum Mode Verse Maximum Mode
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