ELE 3230
Microprocessors and Computer
Systems
Chapter 6
8284 Clock Generator
Bus Demux
Bus Cycle
(Brey: ch8; Hall: ch7)
ELE 3230 - Chapter 6
1
8284 Clock Generator
a 8284 is an integrated circuit which generates the CLOCK,
READY and RESET signals needed in the 8088.
a Internally the 8284 consists of an oscillator circuit (which
needs an external crystal oscillator), dividers, flip-flops,
buffers and logic gates. The external crystal frequency is
divided by 3 to produce the basic clock frequency as shown
10 ns Max
10 ns Max
below:
6
+5
3.9
118.33 ns
Min
68.66 ns
Min
1.5
.6
0
-.5
200 ns Min
500 ns Max
ELE 3230 - Chapter 6
2
8284 Clock Generator
RES
D
Q
X1
X2
RESET
CK
CRYSTAL
OSCILLATOR
OSC
F/C
÷3
÷2
SYNC
SYNC
PCLK
EFI
CSYNC
RDY1
CLK
AEN1
CK
CK
RDY2
AEN2
D
Q
D
FF1
Q
READY
FF2
ASYNC
Internal Block Diagram of the 8284 clock generator
ELE 3230 - Chapter 6
3
8284 Clock Generator
CSYNC
1
18
Vcc
PCLK
2
17
X1
AEN1
RDY1
3
16
X2
4
15
ASYNC
READY
5
14
EFI
RDY2
6
13
F/ C
AEN2
7
12
OSC
CLK
8
11
RES
GND
9
10
RESET
8284A
ELE 3230 - Chapter 6
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8284 Output Pins
a PCLK - peripheral clock; outputs clock signal which is at half the
frequency of the main CLK output.
a CLK – clock; outputs a 33% duty cycle periodic clock which runs at
one third the frequency as the EFI or crystal frequency.
a OSC - oscillator output; provides a buffered periodic waveform
running at the crystal frequency. Output is suitable for driving the
EFI input of another 8284.
a RESET - generates an output suitable for the reset input of the
8088.
a READY - generates READY signal suitable for 8088 READY input.
ELE 3230 - Chapter 6
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Relation between CLK and PCLK
OSC
CLK
PCLK
ELE 3230 - Chapter 6
6
8284 Input Pins
a VCC, GND - power supply pins
a RDY1 and RDY2 - bus ready, accepts input of the bus ready signal
a AEN1, AEN2 - address enable (qualifies RDY1 and RDY2)
a ASYNC- ready synchronization select (selects one or two stages of
synchronization for the RDY1 and RDY2 inputs
a X1, X2 - crystal inputs (for connection of external clock signal input)
a EFI - external frequency input (external clock signal input)
a CSYNC - clock synchronization used with the EFI to synchronize
the clock output in multiprocessor systems. MUST BE
GROUNDED if the crystal oscillator is used.
a F/C - frequency/crystal (selects crystal oscillator or EFI as source)
a RES - reset input (accept input from a switch for generating reset)
ELE 3230 - Chapter 6
7
Example - A simple 8284 circuit
• The 8284 can be used simply to generated the CLOCK signal as shown below:
5V
4.7K
8088
RDY1 RDY2
EFI
CLK
F/C
CSYNC
AEN1
READY
AEN2
5V
4.7K
RESET
ASYNC
CLK
READY
RESET
8284
510
X1
510 15MHz
5V
X2
RES
4.7K
Reset Switch
100nF
• If WAIT states for slow memory or IO peripherals are needed, the circuit must be
modified.
ELE 3230 - Chapter 6
8
Vcc
Minimum Mode System Block
Diagram
8284A
RES clock
generator
GND
CLK
MN/ MX
READY IO/ M
RESET
RD
WR
8088
INTA
CPU
DT/ R
DEN
ALE
AD0-AD7
A8-A19
INTR
Vcc
GND
STB
OE
Address /data 8282 Latch
Address
(1, 2 or
3)
T
OE
8286
Transceiver
Data
WEOE
OE
2142 RAM (2)
27162 PROM
EN
CS
RDWR
Peripheral
8259A
Interrupt
controller
IR0-7
INT
9
Demultiplexing the Address and
Data Bus
a Address and data bus are multiplexed in 8086 (AD0AD15) and 8088(AD0-AD7) to reduce the number of pins
required.
a Address and Data need to be demultiplexed from the
bus. (Q: Why not leave it multiplexed?)
a How to maintain a stable address throughout a read or
write cycle?
ELE 3230 - Chapter 6
10
Demultiplexing the Address and
Data Bus on 8088
• Two transparent latches (74LS373) are used for demultiplexed.
• ALE indicates when address information is on AD0-AD7. In maximum mode, ALE is
generated by the bus controller.
A19/S6
A18/S5
A17/S4
A16/S3
A15
A14
A13
A12
A11
A10
A9
A8
8088
ALE
OE
‘373
G
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
G
‘373
Address bus
Minimum mode
address/data
demultiplexing
OE
D7
D6
D5
D4
D3
D2
D1
D0
IO/M
RD
WR
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
IO/M
RD
WR
Data bus
Control bus
MN/MX
+5V
ELE 3230 - Chapter 6
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Latches
a The address and data bus of the 8088 are multiplexed on pins
AD0 to AD7. Address information are contained on AD0-AD7
only when ALE (address latch enable) is asserted.
a External Latches are needed to store (“latch”) the addressing
information before AD0-AD7 change to carrying data.
a A latch simply consists of a D-type flip-flop with additional
logic to select when to read and output data.
ELE 3230 - Chapter 6
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Latches and flip-flops
D latch
D
D
X
0
1
Q
CK
Q
S
Q
D
D flip-flop
CK
Q
R
S
1
1
1
1
0
1
0
R
1
1
1
1
1
0
0
ELE 3230 - Chapter 6
D
1
0
X
X
X
X
X
CK
0
1
1
Q Q
Q Q
0 1
1 0
N
CK
↑
↑
0
1
X
X
X
N
Q
1
0
Q
Q
1
0
•
N
N
Q
0
1
Q
Q
0
1
•
N
N
13
Latches(cont.)
a Integrated circuits containing many latches (one latch is
needed per bit) are available to perform the latching function
of an address line e.g. 8282, 74LS373.
a These packages typically have a single input, called “strobe”
(STB), “latch enable” (LE) or “Gate” (G), which qualifies the
data (i.e. passes the data to the flip-flops only when it the
strobe or gate input is high).
a Some latches also have an “output enable” (OE) input which
qualifies the output data (when OE is low, the outputs are
open circuit).
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8088 Fan-out and Buffers
a In order to drive the system buses, which typically have many
devices attached and with large capacitance, the address
and data output pins must be buffered.
a A buffer merely amplifies the output current.
a Demultiplexed pins are already buffered by latches (e.g.
74LS373).
a Un-multiplexed address pins can be buffered by 74LS245
octal bi-directional buffer and 74LS244 uni-directional buffer.
ELE 3230 - Chapter 6
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Example: 8088 Fully Buffered Buses
• DT/R, DEN and ALE signals are available from the 8088 in minimum mode
mode only. They must be derived from the bus controller when the 8088
operates in maximum mode.
8088
A19/S6
A18/S5
A17/S4
A16/S3
A15
A14
A13
A12
A11
A10
A9
A8
Example of bus
buffering in 8088
(minimum mode
system)
IO/M
RD
WR
OE
IO/M
RD
WR
‘244
OE
A19
A18
A17
A16
A15
A14
‘373
G
A13
‘244
OE
A3
ALE
DT/R DEN
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
G
Buffered
Control bus
‘373
A12
A11
A10
A9
A8
A7
A6
A5
A4
Buffered
Address bus
A2
A1
A0
OE
B7
A7
B6
A6
B5
A5
B4
A4
B3
A3
B2
A2
B1
A1
A0 G DIR B0
D7
D6
D5
D4
D3
D2
D1
D0
Buffered
Data bus
16
Bidirectional Buffers
a Information is transferred in both directions on the data bus - hence the data
bus buffer must be bidirectional.
a A bidirectional buffer has a “direction” (DIR) input which indicates the direction
of data transfer. The direction input to the buffer can be taken from the DT/R
(data transmit/receive) output of the 8088 (minimum mode system) or bus
controller (maximum mode 8088 system).
a Examples of bidirectional buffers include the 74LS245 and 8286.
Inputs/outputs
Outputs/inputs
EN
DIR
17
8088 Fan-out and Buffers
a The output pins of the 8088 have a limited fan out (the output current can
only drive a finite number of devices, and large capacitive loading on the
output will cause problems with dynamic signals
Recommended 8088 Fan-out
Logic family
Sink current Source Current fanout from
(mA)
8088
(µA)
TTL (74XX)
-1.6
40
1
TTL (74LSXX)
-0.4
20
5
TTL (74SXX)
-2
50
1
TTL (74ALSXX)
-0.2
20
10
CMOS (74HCXX)
-0.001
1
10
CMOS (CD4XXX)
-0.001
1
10
NMOS
-0.01
10
10
Q: Pros and cons of buffer?
ELE 3230 - Chapter 6
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Example of Basic 8086 System Timing
(4+NWAIT)=TCY
T1
T2
(4+NWAIT)=TCY
T3
TWAIT
(TWAIT)
(T3)
T4
T1
T2
T3
TWAIT
T4
CLK
ALE
M/IO
ADDR/STATUS
ADDR/DATA
BHE
A19-A16
A15-A0
S7-S3
BUS RESERVERED
FOR DATA IN
D15-D0
VALID
BHE
A19-A16
A15-A0
S7-S3
DATA OUT D15-D0
RD
READY
READY
READY
WAIT
WAIT
DT/R
DEN
MEMORY ACCESS TIME
WR
19
Bus Timing of the 8088
a Access to memory and I/O operates in bus-cycles. Bus cycles are periods
of time equal to four system clocking periods (1 clock period is often
called a T state). For instance, if the 8088 operates at 5MHz, the bus
cycle rate (which is maximum rate of data transfer) is at 5/4 MHz.
Example of BUS READ CYCLE
a The basic steps of the read cycle (simplified) are:
1. Put memory address on the address bus (T1)
2. Issue a read (RD) memory signal (T2-T3)
3. Read the data from the data bus (T3)
ELE 3230 - Chapter 6
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Bus Timing of the 8088 READ Cycle
Example - 8088/8086 Read bus cycle (simplified)
ONE BUS CYCLE
T1
T2
T3
T4
CLK
ADDRESS
ADDRESS/DATA
VALID ADDRESS
ADDRESS
DATA FROM MEMORY
RD
ELE 3230 - Chapter 6
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Bus Timing Diagrams (General)
a To transfer data without error on the system bus, the signals in the bus
must change and hold the values within a certain period of time in a bus
cycle.
a Physically, a system bus consists of conducting wires or tracks on circuit
board. These have distributed inductance and capacitance which tend to
distort the signal waveforms.
a Long system buses can have clock skew (there is a delay in signals
received by distant peripherals - and their clock is slightly out of phase
with the clock received by the microprocessor).
a The rise-time, fall-time, and duration of signals must be within the
specifications of the device or microprocessor - otherwise errors will occur
in transferring data. The manufacturer’s data sheet contain important
information on the timing requirements which can be quite demanding.
ELE 3230 - Chapter 6
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Bus Cycle Operation
a T1 - start of bus cycle. Actions include setting control signals (or S0-S2
status lines) to give the required values for ALE, DT/R and IO/M ,
and putting a valid address onto the address bus.
a T2 - the RD or WR control signals are issued, DEN is asserted and in
the case of a write, data is put onto the data bus. The DEN turns
on the data bus buffers to connect the cpu to the external data
bus. The READY input to the cpu is sampled at the end of T2 and
if READY is low, a wait state TW (one or more) is inserted before T3
begins.
ELE 3230 - Chapter 6
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Bus Cycle Operation
a T3 - this clock period is provided to allow memory to access the data. If
the bus cycle is a read cycle, the data bus is sampled at the end of
T3.
a T4 - all bus signals are deactivated in preparation for the next clock
cycle. The 8088 also finishes sampling the data (in a read cycle) in
this period. For the write cycle, the trailing edge of the WR signal
transfers data to the memory or I/O, which activates and writes when
WR returns to logic 1 level.
ELE 3230 - Chapter 6
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Read Cycle Timing
a The most important information contained in the read timing diagram is the
amount of the time allowed for getting data from memory.
a Memory chips usually have a specified memory access time.
a The memory access time is defined as the interval from when a valid
address is put on the address bus (near the start of T1) to the time when the
data is read (near the end of T3). The permitted memory access time is
therefore less than three T states if no wait states are added.
a To find the exact access time permitted by the read timing diagram:
1. Find the maximum interval necessary for a valid address to appear after the start
of T1. This interval is given the symbol TCLAV (clock-to-address valid) the
microprocessor data sheet (For a 5MHz 8088, TCLAV=110ns)
ELE 3230 - Chapter 6
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Read Cycle Timing (cont.)
2. Valid data must appear on the data bus before the end of T3 in order to allow
the data to be read. The minimum time interval before the end of T3 for valid
data to appear is given the symbol TDVCL (data valid-to clock) and is
specified as 30ns for the 5MHz 8088.
3. The maximum memory access time=3T-TCLAV-TDVCL which, for the 5MHz
8088, is 600-110-30=460 (ns). Actually the memory access time must be less
than this since there will be propagation delays in going through buffers (about
another 40ns).
ELE 3230 - Chapter 6
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Read Cycle Timing Information from
Data Sheet
Bus Timing of 8088 Write Bus Cycle
ONE BUS CYCLE
T1
T2
T3
T4
CLK
ADDRESS
ADDRESS/DATA
VALID ADDRESS
ADDRESS
DATA WRITE TO MEMORY
WR
ELE 3230 - Chapter 6
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Example - 8088/8086 Write Bus
Cycle (simplified)
a Write bus cycle (simplified) consists of :
1. Put memory address on the address bus (T1)
2. Issue a write (WR ) to memory signal (T2-T3)
3. Send data to data bus (T2-T3) and write to memory
a Actual (non-simplified) read and write bus cycle include changes on other
signals such as M/IO, ALE, DEN, DT/R and READY. The actual cycles
will be investigated in detail later.
a T4 in the bus cycle is used to deactivate all the signals in preparation for
the next bus cycle.
ELE 3230 - Chapter 6
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Write Cycle Timing
a Write cycle is very similar to the read cycle. Main differences are
1. RD Strobe is replaced by WR
2. Data bus contains data for memory rather than data from memory
3. DT/R =1instead of DT/R =0
a The most critical of the write timing diagram is the time interval between
the point when WR becomes logic 1 and the time when data are removed
from the data bus, since data are only written after the trailing edge of the
strobe. This critical time interval is given the label TWHDX and is
specified as 88ns for 5MHz 8088.
ELE 3230 - Chapter 6
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Write Cycle Timing
T2
T1
VCH
TCH1CH2
T3
T4
TW
TCL2CL1
CLK(8284 Output)
VCL
TCLDV
TCLAV
AD7-AD0
AD7-AD0
DATA OUT
AD0
TCVCTV
WRITE CYCLE
NOTE 1
TCHDX
TCLAX
TWHDX
TCVCTV
DEN
TCVCTV
TWLWH
WR
TCVCTX
ELE 3230 - Chapter 6
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READY and the WAIT state
a If the access time for a memory device is longer than the memory
access time calculated, need to give extra clock periods, wait state
Tw, for memory.
a The READY input is sampled at the end of T2 and again, if applicable,
in the middle of Tw. If READY is a logic 0 on 1-to-0 clock transition,
then Tw is inserted between T2 and T3. And will check for logic 1 on
0-to-1 clock transition in the middle of Tw to see if it shall go back T3.
a During the wait state, signals on the buses remain the same as they
were at the start of the WAIT state.
a By having the WAIT state, slow memory and devices has at least one
more cycle (200ns for 5 MHz 8088) to get its data output.
a The READY signal is synchronized by the clock generator 8284A.
ELE 3230 - Chapter 6
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READY and RDY input timing
T2
T3
TW
CLK
8ns
30ns
READY
(a) 8088/86 READY Input Timing
T2
TW
T3
CLK
35ns
RDY
0ns
(b) 8284 RDY Input Timing
ELE 3230 - Chapter 6
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Maximum Mode Bus Buffering and
Demultiplexing
Vcc
CLK
GND
8284A
RES
RDY
S0
S1
S2
CLK
READY
RESET
S0
S1
S2
8288
DEN
8088
GND
DT/R
ALE
WAIT STATE
GENERATOR
ADDR
STB
AD0-AD7
LS373
A8-A19
DATA
DIR
E
LS245
a 8288 bus controller generates control signals needed by interrupt
controllers and peripheral devices (memory)
ELE 3230 - Chapter 6
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Maximum Mode System Block
Diagram
Vcc
8284A
RES clock
generator
S0
S1
READY
RESET
GND
MRDC
MWTC
8288 AMWC
S2
Bus Ctrl IORC
DEN
IOWC
DT/ R
A IOWC
ALE
INTA
S1
S2
CLK
CLK
GND
MN/ MX
S0
NC
NC
8088
MPU
STB
GND
OE
AD 0 − AD 7
A 8 − A 19
Address/data
Address
8282 Latch
(1, 2 or 3)
INTR
T
OE
8286
Transceiver
Data
WEOE
EN
2142 RAM (2)
OE
27162 PROM
CS
RDWR
Peripheral
8259A
Interrupt
controller
IR 0-7
INT
ELE 3230 - Chapter 6
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8088/8086 (maximum mode)
Read Bus Cycle
T1
T2
One bus cycle
T4
T3
CLK
S2-* S0
Address/data
and BHE/S7
Address/data
(AD15-AD0)
S2 --S0
S2 - S0 Inactive
BHE, A19-A16
S7 - S3
Float
A15 - A0
Data in D15 - D0
*ALE
*MRDC or IORC
*DT/R
Triebel Fig.7.24(b)
*DEN
Bus master (8088) actions
S0 - S2 changed for ALE
Output A0-A19 (ALE asserted)
DT/R =0, change S0 - S2 to DEN
Wait until READY asserted
Read data from data bus
set S0 - S2 to 111
Slave (memory) Actions
Decode address, negate RDY
Put data on data bus
Assert RDY
ELE 3230 - Chapter 6
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8088/8086 (maximum mode)
Write Bus Cycle
T1
T2
One bus cycle
T3
T4
CLK
S2- S0
Address/data
and BHE/S7
Address/data
(AD15-AD0)
S2-* S0
S2- S0 Inactive
BHE, A19-A16
S7 - S3
A15 - A0
Float
Data in D15 - D0
*ALE
*AMWC or AIOWC
*MWTC or IOWC
Triebel Fig.7.25(b)
*DEN
Bus master (8088) actions
S0 - S2 changed for ALE
Output A0-A19 (ALE asserted)
DT/R =1, change S0 - S2 to DEN
Output data onto data bus
Wait until READY asserted
read data, set S0 - S2 to 111
Slave (memory) Actions
Decode address, negate RDY
Store data
Assert RDY
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