Bachelor Thesis
Estimation of Interface and Oxide Defects in Direct
Contact High-k/Si Structure by Conductance Method
Toru Kubota
Department of Electrical and Electronic Engineering
School of Engineering
Tokyo Institute of Technology
Supervisor: Prof. Hiroshi Iwai
February, 2011
February, 2011
Abstract of Bachelor Thesis
Estimation of Interface and Oxide Defects in Direct Contact
High-k/Si Structure by Conductance Method
Supervisor: Prof. Hiroshi Iwai
Department of Electrical and Electronic Engineering
07_09508 Toru Kubota
Since the scaling of MOSFETs utilizing SiO2 as gate dielectric has reached its limit, high-k
materials have been studied as gate dielectrics. For high-k materials such as Hf-based MOSFETs,
an SiO2 interfacial layer is intentionally formed at the high-k/Si interface to improve electric
characteristics. Besides, La2O3 gate dielectric is a promising high-k material because it shows fairly
nice electrical characteristics by forming La-silicate layers at the interface. Since the dielectric
constants of the silicates are larger than that of SiO2, the equivalent oxide thickness scaling can be
further extended by achieving a direct contact of high-k with the Si substrate. However, the
interface properties of La-silicate and Si substrate are still unknown. Moreover, a method to further
improve the interfacial properties is not clarified yet. In this thesis, the interfacial properties of
La-silicate/Si structures were evaluated by conductance method and modeled to create an
equivalent circuit. The equivalent circuit includes capacitances and conductances representing the
interface states and the parasitic conductance caused by the leakage current through the high-k. By
comparing the spectra obtained from reference SiO2/Si MOS capacitor, additional peaks at
frequency range of 100 Hz was detected with La-silicate/Si structure. The origin of the signals can
be interpreted as the defects in the silicate layers adjacent to the interface as their capture and
emission time constants are different from those for interface states in SiO2/Si structure. Based on
the above findings, an equivalent circuit model of MOS capacitor including the contribution from
oxide defects is newly developed. In consequences, a good agreement between the measured and
calculated data can be obtained. It is shown from this study that the quantitative study on interface
traps and oxide traps is very effective in improving the interfacial properties of MOS devices.
i
Contents
1 Introduction
1.1 Introduction of high-k materials --------------------------------------- 1
1.2 Issue in high-k gate dielectrics ------------------------------------------ 2
1.3 La2O3 as high-k gate dielectrics ---------------------------------------- 3
1.4 Issue in La2O3 gate dielectric -------------------------------------------- 4
1.5 Purpose of this study ------------------------------------------------------ 6
2 Experiments
2.1 Experimental principles
2.1.1 SPM cleaning and HF treatment ----------------------------------- 7
2.1.2 Formations of dielectrics
2.1.2.1 Formation of SiO2 dielectric by thermal oxidation --------- 7
2.1.2.2 Deposition of La2O3 dielectric by MBE ------------------------ 8
2.1.3 RF magnetron sputtering -------------------------------------------- 9
2.1.4 Patterning of resist by photo lithography ----------------------- 10
2.1.5 Dry etching by RIE -------------------------------------------------- 10
2.1.6 PDA and PMA in F.G. ambient ------------------------------------ 12
2.1.7 Deposition of Al by vacuum evaporation ------------------------ 12
2.2 Experimental procedure ------------------------------------------------- 13
2.3 Estimation of interface state density by conductance method
2.3.1 Statistical analysis of GP/ω ------------------------------------------- 16
2.3.2 Analysis of capacitance ----------------------------------------------- 19
3 Results and Discussions in SiO2/Si structure
3.1 Contribution of SiO2/Si structure to small signal voltage --------- 20
3.2 Energy distribution of Dit ------------------------------------------------ 21
ii
4 Results and Discussions in La2O3/Si structure
4.1 Interface state at the high-k/Si interface ------------------------------ 25
4.2 Influence of leakage current on the determination of GP/ω ------- 25
4.3 Proposal of a new model ------------------------------------------------- 29
4.4 Application of a new model to the measurement -------------------- 31
5 Conclusions ----------------------------------------------------------------- 34
Appendices
A. The derivation of calculation changing equivalent circuit model to
simplified circuit ----------------------------------------------------------- 35
B. The derivation of calculation changing measured circuit to
simplified circuit ---------------------------------------------------------- 35
C. The derivation of calculation changing measured circuit to
equivalent circuit model ------------------------------------------------ 37
References --------------------------------------------------------------------- 38
Acknowledgements --------------------------------------------------------- 40
iii
1 Introduction
1.1 Introduction of high-k materials
Metal-oxide-semiconductor field effect transistor (MOSFET) is one of the most
principal elements for very large-scale integration (VLSI) technology. It is used in a lot
of electronic equipment, and we use it every day. It is not too much to say that our
modern life consists of VLSI technology. The high density, performance, and low
consumption electricity of MOSFETs was progressing with the scaling of those device
sizes. Now, most of the gate dielectrics used are silicon dioxide (SiO2) because it
works as layers which have high insulation, passivation, and diffusion barrier [1].
However, as device scaling progresses, physical thickness of SiO2 gate dielectrics
becomes thin, so that leakage current flows because of the quantum mechanical tunnel
effect. Leakage current causes larger electric consumption in the device. Therefore,
scaling of MOSFETs with SiO2 gate dielectrics reach its limit. High-k materials have
been studied to break the limitation instead of SiO2 dielectrics. High-k gate dielectrics
have high dielectric constants, so we can get same capacitance in the larger physical
thickness. Because of this reason, leakage current can decrease compared with SiO2
gate dielectrics. It is shown in Fig. 1.1. It is introduced that the index which expresses
scaling of high-k gate dielectrics is equivalent oxide thickness (EOT). EOT can be
given by
EOT =
ε SiO 2
t OX ,
ε high −k
(1.1)
where εSiO2, εhigh-k are each dielectric constant of SiO2, high-k, and tox is the physical
thickness. Therefore, the study of high-k dielectrics is very important for device
scaling in the future.
1
Gate
Gate
SiO2
S
same EOT and capacitance
D
High-k
S
D
Si-substrate
Si-substrate
Fig. 1.1 High-k gate dielectrics become larger thickness when they have the
capacitance as same as SiO2, and leakage current can decrease.
1.2 Issue in high-k gate dielectrics
It is effective to introduce high-k gate dielectrics in order to realize the low EOT.
However, it is considered that fixed oxide charge generates in high-k gate dielectrics
because the metal diffuses from gate to those [2]. Fixed oxide charge causes bad
influences [3] . Fixed oxide charges work as scattering center, which is called coulomb
scattering. Coulomb scattering makes mobility of carriers in surface inversion channel
decrease. This is one of the most serious problems.
So, the method that is considered in order to solve this problem is forming SiO2
interfacial layer at the interface between high-k gate dielectrics and Si-substrate as
shown in Fig. 1.2. SiO2 interfacial layer is necessary to improve electrical
characteristics. However, we are demanded to achieve EOT = 0.5nm in 2015 as shown
in Fig. 1.3 from ITRS 2009 [4]. So, it is difficult for high-k gate dielectrics formed
SiO2 interfacial layer to achieve EOT = 0.5nm. Thus, we need to select the high-k gate
dielectric that can directly contact Si-substrate.
Gate
High-k
SiO2
Si-substrate
Fig. 1.2 It is difficult to decrease EOT because of SiO2 interfacial layer.
2
1.1
EOT (nm)
1
Planar Bulk
MOSFET
0.9
0.8
0.7
0.6
0.5
0.4
2009
2011
2013
2015
YEAR
Fig. 1.3 EOT versus YEAR plots in planer bulk MOSFETs from ITRS 2009. We are
demanded to achieve EOT = 0.5nm in 2015.
1.3 La2O3 as high-k gate dielectrics
Lanthanum oxide (La2O3) is one of the promising high-k gate dielectrics. The
relations between band gap and dielectric constants, k are shown in Fig. 1.4 [5]. The
dielectrics generally have trade-off relations between band gap and dielectric constants.
Fig. 1.4 shows that La2O3 has a high dielectric constant (εr = 23.4) and broad band gap
(Eg = 5.6 eV) together.
La2O3
Fig. 1.4 Band gap versus dielectric constants, k plots. La2O3 has a high dielectric
constant and broad band gap together.
3
In addition, La2O3 has one more advantage. After the device used La2O3 as gate
dielectric is annealed, it is formed La-silicate layer at the interface between La2O3 and
Si-substrate [6]. It is shown in Fig. 1.5. La-silicate has a higher dielectric constant that
is from 8 to 14 than that of SiO2. So, La2O3 gate dielectric is effective to decrease EOT
in the future. From these discussions, La2O3 is used as high-k gate dielectrics in this
study.
Gate
Gate
Annealing
La2O3
La2O3
La-Silicate
Si-substrate
Si-substrate
Fig. 1.5 After annealing, La-silicate formed at the interface between La2O3 and
Si-substrate, which has a higher dielectric constant that is from 8 to 14.
1.4 Issue in La2O3 gate dielectric
La2O3 can contact Si-substrate directly without SiO2 interfacial layer. However, it is
one of the problems that the interface state at the surface between La2O3 and
Si-substrate is worse than that of SiO2. The reason is the metal diffuses into La2O3
dielectric easily than SiO2.
Interface state causes next two phenomena that have bad influences, so it is
important to decrease interface state density (Dit). First, interface trap generates
additional capacitance because the charge density trapped to interface with the change
of surface potential changes. This capacitance affects capacitance-voltage (C-V)
characteristics, which is one of the indicators expressed the performance of MOSFET.
Therefore, it is important to use device processes which make Dit minimize in order to
do good C-V characteristics that have reproducibility. Second, interface trap generates
leakage current in gate diode structures because it works as generation and
4
recombination centers, or promotes band to band tunneling processes. Therefore, we
must minimize Dit in order to realize high performance and reliability.
However, we need to consider the method estimating Dit in the devices with any
dielectric first. Conductance method is one of the methods estimating Dit. It is a way
which we replace MOS capacitor with equivalent circuit models and calculate Dit. Fig.
1.6 shows equivalent parallel conductance versus frequency plots. This figure means
that the local maximum of each curve indicates the magnitude of Dit (see in paragraph
2.3). We can see the peak of each curve in Fig. 1.6. The curve of SiO2 gate dielectric
has one peak, but that of La2O3 gate dielectric has two peaks in this figure. So, peaks of
the curve used La2O3 gate dielectric mean that interface state and other energy level are
measured. The peak of other energy level is much larger than that of interface state,
and it appears at low frequency region. Therefore, the peak of interface state at low
frequency is concealed by that of other energy level, and the problem interface state
cannot be measured is generated.
(x 10-6)
3
(x 10-9)
5
La2O3
系列2
系列
Gp /ω (F/cm2)
2.5
SiO2
系列1
系列
4
2
3
1.5
2
1
E-Ei = 0.12 eV
Vamp = 100 mV
0.5
1
0
0
101
102
103
104
105
106
107
Frequency (Hz)
Fig. 1.6 Equivalent parallel conductance over angular frequency (GP/ω) versus
frequency plots. Solid dots are La2O3 gate dielectric, open dots are SiO2 gate dielectric.
5
1.5 Purpose of this study
The purpose of this study is to estimate interface and oxide defects by conductance
method, and to compare SiO2 and La2O3 dielectrics.
Chapter 1 shows the background and purpose of this study. In chapter 2,
experimental principles, procedure, and estimate method are described. In chapter 3,
the results in SiO2/Si structure are reported. In chapter 4, the results in La2O3/Si
structure are reported, and compared with SiO2/Si structure. Finally, the conclusions of
this study are summarized in chapter 5.
6
2 Experiments
2.1 Experimental principles
2.1.1 SPM cleaning and HF treatment
In fabrication processes, it is important to clean the surface of Si-substrate because
particles and metal ions affect the performance, reliability, and yield of the devices
greatly. One of the effective methods is sulfuric acid hydrogen peroxide mixture (SPM)
cleaning and hydrofluoric acid (HF) treatment. They remove particles and metal ions,
and make the surface of Si-substrate clean. The liquid used in SPM cleaning is mixed
liquid of H2O2 and H2SO4 (H2O2:H2SO4 = 1:4), which has strong oxidation.
Si-substrate is soaked into the liquid, then particles and metal ions are separated from
Si-substrate because of its oxidation. At that time the surface of Si-substrate is also
oxidized and formed chemical oxide. In order to eliminate chemical oxide, Si-substrate
is soaked into 1% HF. Then the devices with clean surface are completed. Fig. 2.1
shows schematic illustration of SPM cleaning and HF treatment.
Particle Metal ion
SiO2
Chemical oxide
Chemical
oxide
SiO2
SiO2
SiO2
SiO2
Si-substrate
Si-substrate
Si-substrate
SPM cleaning
H2O2+H2SO4
(1:4)
SiO2
HF treatment
1%HF
Si-substrate
Fig. 2.1 Schematic illustration of SPM cleaning and HF treatment.
2.1.2 Formations of dielectrics
2.1.2.1 Formation of SiO2 dielectric by thermal oxidation
The most general method formed SiO2 dielectric is thermal oxidation [7]. It is
oxidized while flown O2 in high temperature, which is typically about 1000oC.
7
Therefore, SiO2 dielectric is formed at the surface. This method takes many times, but
forms high quality and reliability SiO2 dielectric because the position of surface after
thermal oxidation moves inside.
Heat
O2
Si-substrate
Fig. 2.2 Schematic illustration of the oxidation furnace.
Thermal
oxidation
SiO2
SiO2
SiO2
SiO2
Si-substrate
SiO2
Si-substrate
Surface after
thermal oxidation
Fig. 2.3 SiO2 dielectric is formed by thermal oxidation.
2.1.2.2 Deposition of La2O3 dielectric by MBE
The method used in order to deposit La2O3 is Molecular beam epitaxy (MBE) in this
study. Fig. 2.4 shows schematic illustration of MBE [8]. First, the inside of chamber is
done in ultra high vacuum in order to make the orbit of evaporated molecular beam
stable. Then, accelerated electron beam (E-beam) emitted from hot-filament is bended
by the magnetic field, and it hits the source material. The place hit by E-beam is
evaporated because of its heat. The generated molecular beam from there splashes for
Si-substrate, and then La2O3 dielectric is deposited on the wafer.
8
Substrate
Molecular
beam
Evaporated
source
by heat
Accelerated
E-beam
Source
material
Fig. 2.4 Schematic illustration of MBE.
2.1.3 RF magnetron sputtering
Radio frequency (RF) magnetron sputtering is one of the deposition methods.
Schematic illustration is shown in Fig. 2.5. First, the high voltage is applied between
target and substrate, and Ar is flown into the chamber. This voltage difference causes
high electric field. Therefore, that makes Ar become the state of plasma, and Ar is
ionized. Ar ions are attracted to the target because electrons are accumulated in the
target. Ar ions collide with the target, then atoms of the target are emitted and the film
is deposited.
Substrate
Ar+
Atom of
target material
target
material
plasma
Fig. 2.5 Schematic illustration of RF magnetron sputtering.
9
2.1.4 Patterning of resist by photo lithography
Resist patterning is the method to eliminate only parts of required gate metal. It is
used positive resist in this study, which places exposed to light are melted. First, resist
is applied on the gate electrode. In order to make resist uniform, Si-substrates applied
resist are revolved by the spinner. After that, the substrates are heated to fixate the
resist, which is called pre-bake. And, the substrates are adjusted to photo mask to do
resist patterning. After they are exposed to light, they are soaked into the developer. In
consequence, only resist uncovered with the mask is melted by the developer as shown
in Fig. 2.6. Finally, they are heated to fixate the resist, too, and this is called post-bake.
Therefore, only required resist is remained.
Light
Resist
Gate
electrode
Mask
Gate
dielectric
SiO2
SiO2
Si-substrate
SiO2
Exposure
and
Developing
SiO2
Si-substrate
Fig. 2.6 Schematic illustration of photo lithography
2.1.5 Dry etching by RIE
Reactive ion etching is (RIE) is one of the methods to etch the films [9]. It is similar
to RF magnetron sputtering, but it is used by not only physical but also chemical
reaction. The gate electrodes used in this study are tungsten (W) and titanium nitride
(TiN). The gas etching them is sulfur hexafluoride (SF6), and the gas etching resist is
O2. First, the gas used to etch the film becomes the state of plasma as same as RF
magnetron sputtering. SF6 and O2 ionized radicals with high reaction, cations, electrons,
and so on. Chemical reaction occurs when radicals are absorbed on the substrates, and
10
then the compound is separated from the substrates because of its volatility. Cations
collide with the substrates because of electric field, which is physical etching. It is
shown in Fig. 2.7. The advantage of RIE can etch to the same as the shapes of mask
because of anisotropic etching. The reason is that cations are incident vertically. It is
shown in Fig. 2.8.
SF6 or O2
e-
Radical
e-
e-
e-
e-
plasma
Cation
Substrate
Fig. 2.7 Schematic illustration of RIE.
Radical Cation
SF6
O2
Resist
SiO2
SiO2
Si-substrate
Gate
electrode
Gate
dielectric
SiO2
Gate
electrode
patterning
SiO2
Si-substrate
SiO2
Resist
removal
SiO2
Si-substrate
Fig. 2.8 Schematic illustration after etching.
11
2.1.6 PDA and PMA in F.G. ambient
Post deposition annealing (PDA) and post metallization annealing (PMA) are very
important processes to fabricate high performance devices. These two methods are
different from annealing timing, but same as the principle. The structures and
properties of silicon that has periodicity terminate at the surface between Si and gate
dielectrics. So, many dangling bonds that cause interface state are generated there.
PDA and PMA are used in order to terminate them. After it is formed a vacuum,
forming gas (F.G.) (N2:H2 = 97:3) is flown and the substrates are heated at 420oC for
30min or 800oC for 2sec in this study. Thus, forming gas annealing (F.G.A.) is effective
to decrease Dit. It is shown Fig. 2.9.
H2
N2
SiO2 Annealing
SiO2
SiO2
SiO2
H H
H
Si Si Si Si
Si Si Si Si
Si-substrate
Si-substrate
Fig. 2.9 Schematic illustration of forming gas annealing (F.G.A.).
2.1.7 Deposition of Al by vacuum evaporation
Finally, Al electrode is deposited on the back side of substrates. In this study,
vacuum evaporation method is used to deposit Al as shown in Fig. 2.10. Al is placed
on W boat, and current is flown in the circuit connected with W boat. Large current is
flown, and then Al is vaporized by joule heat because the boiling point of Al is lower
than the melting point of W. Therefore, vaporized Al is deposited on the substrates.
12
Back side
of substrate
Heated
Aluminium
W boat
Fig. 2.10 Schematic illustration of vacuum evaporation method.
2.2 Experimental procedure
Fig. 2.11 shows schematic illustration of MOS capacitors fabrication processes. First,
the fabrication of MOS capacitors with SiO2 gate dielectric is explained. SiO2 (10nm)
is deposited on the Si-substrates after SPM cleaning and HF treatment by thermal
oxidation, and W (60nm) is deposited by RF magnetron sputtering. After W is pattered
by photo lithography and RIE, PMA at 420oC for 30min is conducted. Finally, Al
(50nm) is deposited on the back side of substrates, and then they are measured. Next,
the fabrication of MOS capacitors with La2O3 gate dielectric is explained. La2O3 (3nm)
is deposited by MBE, and Si (1.5nm) is deposited by RF magnetron sputtering. In
order to form La-silicate layer, PDA at 800oC for 2sec is conducted here. And then,
TiN (60nm) is deposited as a gate electrode by RF magnetron sputtering. After that
PMA and Al (50nm) deposition are conducted as same as MOS capacitors with SiO2.
13
n&p-Si (100) substrate
Particle
Metal ion
SiO2
SiO2
Si-substrate
SPM cleaning and HF treatment
SiO2
SiO2
Si-substrate
in-situ
SiO2 (10nm) deposition
by thermal oxidation
La2O3 (3nm) deposition by MBE
SiO2
SiO2
La2O3
SiO2
SiO2
Si-substrate
Si-substrate
W (60nm) deposition
by RF magnetron sputtering
Si (1.5nm) deposition
by RF magnetron sputtering
W
SiO2
SiO2
SiO2
Si
SiO2
SiO2
SiO2
Si-substrate
Si-substrate
PDA in F.G. at 800oC for 2sec
SiO2
La-silicate
SiO2
Si-substrate
TiN (60nm) deposition
by RF magnetron sputtering
TiN
SiO2
La-silicate
Si-substrate
14
SiO2
Photo lithography
TiN
W
SiO2
SiO2
SiO2
SiO2
Si-substrate
La-silicate
SiO2
Si-substrate
Gate electrode and resist etching by RIE
PMA in F.G. at 420oC for 30min
TiN
W
SiO2
SiO2
SiO2
SiO2
Si-substrate
La-silicate
SiO2
Si-substrate
Al deposition by vacuum evaporation method
TiN
W
SiO2
SiO2
SiO2
SiO2
Si-substrate
La-silicate
Si-substrate
Al
Al
Measurement
Fig. 2.11 Schematic illustration of experimental procedure.
15
SiO2
2.3 Estimation of interface state density by conductance method
2.3.1 Statistical analysis of GP/ω
In this study, conductance method is used as estimating Dit. Conductance method is
a way which we replace MOS capacitor with equivalent circuit models and calculate
Dit. Fig. 2.12(a) shows an equivalent circuit model of MOS capacitor [10], where COX
is the oxide capacitance per unit area, CS is the silicon capacitance per unit area, Rit and
Cit are the resistance and capacitance components per unit area related to interface trap,
and Gt is tunnel conductance per unit area related to leakage current. On the other hand,
the measurement circuit is shown in Fig. 2.12(b), where Cm and Gm are the measured
capacitance and conductance per unit area. And the equivalent parallel circuit is shown
in Fig. 2.12(c), where CP and GP are the equivalent parallel capacitance and
conductance per unit area. The reason why it is changed like that can be expressed that
GP has only interface trap information not including CS when the circuit is converted.
CP and GP are given by
CP = CS +
GP
ω
=
qDit
1 + (ωτ it )
qωτ it Dit
1 + (ωτ it )
2
2
,
,
(2.1)
(2.2)
where Cit = qDit, and τit = CitRit (see detail calculation in Appendix A). Dit is interface
state density and τit is interface trap time constant here. Eq. (2.2) becomes symmetrical
in ωτit because dividing GP by ω is done. These two equations are for interface traps
with a single energy level in the band gap. However, interface traps actually are
continuously distributed. Therefore, these two equations are rewritten as [11]
CP = CS +
GP
ω
=
qDit
ωτ it
[
tan −1 (ωτ it ) ,
]
qDit
2
ln 1 + (ωτ it ) .
2ωτ it
(2.3)
(2.4)
These two equations are for interface traps with the continuum level. It is more
effective for Eq. (2.4) than (2.3) to calculate Dit because Eq. (2.4) has only parameters
related to interface traps without including CS.
16
On the other hand, the capacitance and conductance are measured from Fig. 2.12(b).
So, we need to change Fig. 2.12(b) for (c), and compare with Eq. (2.4). Then, GP/ω is
calculated as (see detail calculation in Appendix B)
ω (Gm − Gt )C OX 2
=
.
ω (Gm − Gt )2 + ω 2 (C OX − C m )2
GP
COX
COX
Cm
Gt
Gm
Gt
Rit
CS
(2.5)
CP
GP
Cit
(a)
(b)
(c)
Fig. 2.12 Equivalent circuits of MOS capacitor; (a) an equivalent circuit model of the
MOS capacitor, (b) the measured circuit, (c) the simplified circuit of (a).
The values calculated from Eq. (2.2), (2.4) and (2.5) are shown in Fig. 2.13
respectively. We see it is generated serious error between continuum level and
measurement data. It is considered that the reason is surface potential fluctuations. This
is generated by inhomogeneities in oxide charge and interface charge [12]. So, we
consider surface potential fluctuations, but it is difficult to analyze the experimental
data. Therefore, we assume that surface potential fluctuations follow normal
distribution, and then Eq. (2.4) becomes
∞
[
]
q ⌠ Dit
2
= 
ln 1 + (ωτ it ) P(ψ S )dψ S ,
2 ⌡−∞ ωτ it
ω
GP
P(ψ S ) =
(
 ψ −ψ
exp − S 2 S

2σ
2πσ 2

1
17
)
2

,


(2.6)
(2.7)
where ψ S is the surface potential, ψ S and σ are mean and standard variation of the
surface potential respectively. So, the larger σ is, the lower values of the peak and
broader width of the curves are. Values calculated from these equations are shown
solid line in Fig. 2.x. The parameters that is used as the variables are Dit, τit, σ, and Gt
in Eq. (2.6) and (2.7) at this time. These values in Fig. 2.13 are Dit = 8.2 x 1010
eV-1cm-2, τit = 3.1 x 10-5 s, σ = 0.041, and Gt ≈ 0. The integration of Eq. (2.6) is
calculated that Dit and τit are determined by fitting GP/ω curves first. Then, Dit and τit
between determined values are interpolated by spline interpolation method, which is
found the values between determined values by solving polynomicals of three
dimensions. We see measured and statistic data are close values in this figure.
Therefore, it is important for accurate measurements to consider surface potential
fluctuations.
Gp /ω (x10-9 F/cm2)
7
Single level
Continuum level
Measurement
Statistic
6
5
4
3
2
1
0
102
103
104
105
106
107
Frequency (Hz)
Fig. 2.13 Equivalent parallel conductance over angular frequency (GP/ω) versus
frequency plots. Dashed line is values used by single level, alternate long and short
dash line is values used by continuum level, dots are measured values, solid line is
statistic based on normal distribution.
18
2.3.2 Analysis of capacitance
The problems in paragraph 1.4 cause measurement values not to be able to be fitted
by GP/ω. Because we need to discuss other parameters, we notice measured
capacitance and discuss that. Therefore, we change Fig. 2.12(c) to (b), and measured
capacitance is given by (see detail calculation in Appendix C)
 GP  2

COX 
 + C P (COX + C P )
 ω 

Cm =
.
2
 GP 
2

 + (COX + C P )
 ω 
(2.8)
Eq. (2.8) is assumed continuum level. Similarly, surface potential fluctuations follow
normal distribution, so that Eq. (2.8) becomes
∞
 G P  2

⌠
 C OX  ω  + C P (C OX + C P )



Cm = 
P(ψ S )dψ S .
2

 GP 
2

 + (C OX + C P )


ω


⌡−∞
(2.9)
And, substituting Eq. (2.3) and (2.4) into Eq. (2.8) and (2.9), we obtain Fig. 2.14. Thus,
we can fit by using Cm, too.
34
Continuum level
Measurement
Statistic
Cm (nF/cm2)
32
30
28
26
24
22
20
102
103
104
105
106
107
Frequency (Hz)
Fig. 2.14 Measured capacitance (Cm) versus frequency plots. Statistic is similar to
measured capacitance.
19
3. Results and discussions in SiO2/Si structure
3.1 Contribution of SiO2/Si structure to small signal voltage
AC voltage is applied to the device, and it can be measured Dit by conductance
method. The reason is that electrons are not captured to interface state and emitted
from there in the case of DC voltage. It is used sine wave as power sources in this
experiment. So, we need to examine the dependence of small signal voltage and effect
influenced Dit measurement. Fig. 3.1 shows GP/ω in each small signal voltage. We see
that the curve of larger small signal voltage becomes the smaller local maximum and
broader width of that. So, it is considered the change of the small signal voltage works
as same as parameter σ varies. However, even if the small signal voltage is small,
measurement curves do not agree with continuum level curves. And in Fig. 3.1,
frequency of each curve at the local maximum is different. The reason is explained in
Fig. 3.2 and Eq. (2.5). GP/ω in each energy level is shown in Fig. 3.2. In this figure, as
the energy level becomes high, the peak of curve becomes high and the frequency
shifts the right hand. Because GP/ω is followed by Eq. (2.5), when σ is large, it is
deeply related to GP/ω of other energy level. Therefore, the peaks of curves shift the
right hand.
Gp /ω (x10-9 F/cm2)
7
small signal
voltage
6
5
5 mV
50 mV
100 mV
down
4
3
2
up
1
0
102
103
104
105
106
107
Frequency (Hz)
Fig. 3.1 GP/ω versus frequency plots in each small signal voltage.
20
Gp /ω (x10-9 F/cm2)
8
E-Ei
= 0.02 eV
0.16 eV
0.11 eV
0.07 eV
7
6
0.20 eV
5
4
3
2
1
0
102
103
104
105
106
107
Frequency (Hz)
Fig. 3.2 Equivalent parallel conductance over angular frequency (GP/ω) versus
frequency plots when small signal voltage is 50 mV.
3.2 Energy distribution of Dit
Dit is distributed in the band gap of silicon. When Dit is measured by conductance
method, the place of measured interface state is equal to Fermi level. So, we can
determine the place of interface state from Fermi level and surface potential. Because
we cannot determine surface potential directly, it is necessary to determine from the
relation between gate bias surface potential. Although the relation is expressed a
complicated equation, we can make it easy by using depletion approximation. The
reason we use depletion approximation is that most of Dit is measured and it is easy to
analyze in depletion region. Although it is measured in weak inversion region, it is
difficult to analyze [13]. The relation between surface potential and gate bias is given
by
Vg = −
2ε Si qN D ψ S
C OX
− ψ S + V fb (n-type silicon),
21
(3.1a)
2ε Si qN A ψ S
Vg =
C OX
+ ψ S + V fb (p-type silicon),
(3.1b)
where εSi is silicon permittivity, q is electronic charge, ND and NA is donor and acceptor
impurity density in bulk silicon, and Vfb is flat-band voltage. Surface potential is
determined by solving Eq. (3.1a) or (3.1b) as ψ S . The values of ψ S is defined that it
is plus values when the silicon band is bends downward and minus values when the
silicon band is bends upward. And Fermi level is given by
N
E f = kT ⋅ ln D
 ni

 (n-type silicon),

(3.2a)
N 
E f = − kT ⋅ ln A  (p-type silicon),
 ni 
(3.2b)
where k is Boltzmann’s constant, T is absolute temperature, ni is intrinsic carrier
density, and the mid gap energy Ei is replaced as Ei = 0 after this. From these equations,
we get energy distribution of Dit as shown in Fig. 3.3. In this figure, we see Dit is
decreasing as energy approaches the mid gap. And, we also see next two
characteristics.
First, the ranges that can be measured peaks of curves are not equal between p-type
and n-type. Actually, the measured ranges of p-type and n-type are 0.11 eV and 0.19 eV.
The reason is considered τit is different in each type. τit is given by [14]
τn =
 qψ S 
exp −
 (n-type silicon),
vth _ nσ n n0
 kT 
τp =
 qψ S 
exp
 (p-type silicon),
vth _ pσ p p 0
 kT 
1
1
(3.3a)
(3.3b)
where vth_n and vth_p are electron and hole thermal velocity, σn and σp are electron and
hole capture cross section, n0 and p0 are density of free electrons and holes at thermal
equilibrium. In these parameters, n0 and p0 are almost same because they can be
replaced with impurity densities at room temperature. The relation to σn and σp are not
found, but we see vth_n is larger than vth_p [15]. Therefore, the terms except exponential
term in Eq. (3.3b) are larger than that of Eq. (3.3a), so that τp changes more largely
than τn when each ψ S in Eq. (3.3a) and (3.3b) changes for same amount. Because of
22
this reason, GP/ω of p-type silicon shifts more largely than n-type silicon, and it is
considered that the range of measurement is narrow in the p-type silicon.
Second, we see the energy that is minimized Dit is not mid gap in this figure. It is
considered that the bulk impurity densities are not accurate values because the
Si-substrate in this study is used with a given resistivity. Fig. 3.4 shows C-V curves of
the measurement data and ideal data. We see they do not agree in depletion region from
-0.1 V to 0.4 V. In depletion region, the contribution of the depletion layer capacitance
is the largest of all regions. Also, it depends on the impurity density. Therefore, Fig. 3.4
indicates the impurity density is not correct. Thus, if the impurity densities have errors,
Fermi level changes, and it makes energy distribution change, too. The errors of
impurity densities especially influence the fitting by measured capacitance.
Dit (x 1010 eV-1cm-2)
14
12
10
p-type Si
8
6
n-type Si
4
2
0
-0.3
-0.15
0
0.15
0.3
E-Ei
Fig. 3.3 Interface state density versus energy plots. Mid gap in silicon band gap means
E-Ei = 0. Dit is decreasing as energy approached the mid gap.
23
Capacitance (µ
µF/cm2)
0.4
Measurement
Ideal
0.3
0.2
0.1
W/SiO2/n-Si
Not
agree
@100kHz
Nd = 3x1015
0
-0.5
0
0.5
1
1.5
2
Gate Voltage (V)
Fig. 3.4 Capacitance versus gate voltage plots. Measurement data do not agree with
ideal C-V curve in depletion region.
24
4 Results and Discussions in La2O3/Si structure
4.1 Interface state at the high-k/Si interface
It is found that GP/ω curves in La2O3/Si structure are different from those of SiO2/Si
structure as shown in Fig. 4.1, which shows GP/ω versus frequency plots in each scale.
Each small signal voltage and energy is different in order to make the figures easy to
see. Anyway, we can see two peaks from each curve, and each value of two peaks is
different about one digit in these figures. This characteristic is not seen in the case of
SiO2 gate dielectric. Compared with Fig. 3.2, it is considered that peaks on high
frequency region seen in Fig. 4.1(b) are probably caused by interface state.
In this chapter, considerations about these peaks are shown.
30
5
Gp /ω (x10-7 F/cm2)
E-Ei
Vamp = 25 mV
-0.1 eV
25
0.05 eV
0.10 eV
0.15 eV
0.20 eV
4
0 eV
0.1 eV
20
0.2 eV
E-Ei
3
15
2
10
1
5
Vamp = 100 mV
0
0
101
102
103 103
104
105
106
Frequency (Hz)
(a)
(b)
Fig. 4.1 GP/ω curves have two peaks with different values;
(a) low frequency region, (b) high frequency region.
4.2 Influence of leakage current on the determination of GP/ω
In chapter 3, we discuss SiO2 gate dielectric, and then GP/ω are calculated as Gt ≈ 0
in Eq. (2.5). This reason is that SiO2 dielectric has thick membrane (10 nm), so leakage
25
107
current can be almost ignored. However, we must consider the influence of leakage
current in La2O3/Si structure because the thickness of La2O3 is 3nm. By the way, it is
found that EOT of this sample is 0.88nm and flat-band voltage (Vfb) is -0.69V from the
measurement of C-V characteristic. So, we need to consider values of tunnel
conductance (Gt). Fig. 4.2 shows the relation between leakage current per unit and gate
voltage. Seeing overall, the shape of measured plots is similar to exponential function.
However, negative voltage region has particularly errors compared with exponential
approximation. The range from -1.1 to -0.7 is measured by conductance method. Most
of this range is depletion region because Vfb is -0.69V. And Gt is determined by leakage
current differentiated by gate voltage. The relation between Gt and gate voltage is
shown in Fig. 4.3, where the values calculated by measurement are distinguished from
those calculated by approximation (Gt calculated by measurement is called measured
Gt, and calculated by exponential approximation is called approximated Gt in this
paper). Errors of Gt between measured plots and exponential approximation in region
B are largely than those of leakage current in region A. Thus, it is difficult to estimate
Gt.
Leakage Current
(x10-3 A/cm2)
A
60
0
50
aMeasurement
40
bapproximation
-0.5
Exponential
aMeasurement
Exponential
-1
30
bapproximation
-1.5
20
-2
A
10
0
-2.5
-10
-3
-2
-1.5
-1
-0.5
0
0.5
1
-1.1
-1
-0.9
-0.8
-0.7
Gate Voltage (V)
Fig. 4.2 Leakage current per unit area versus gate voltage plots. Measured plots have
errors compared with exponential approximation in region A.
26
Tunnel Conductance
(x10-3 S/cm2)
B
160
4
140
Exponential
120
2
60
1.5
1
B
20
系列2
系列
approximation
2.5
80
40
Exponential
3
bapproximation
100
Measurement
系列1
系列
3.5
aMeasurement
0.5
0
0
-2
-1.5
-1
-0.5
0
0.5
1
-1.1
-1
-0.9
-0.8
Gate Voltage (V)
Fig. 4.3 Tunnel conductance per unit area (Gt) versus gate voltage plots. Errors
between measured plots and exponential approximation are large in region B.
Here, these two types of Gt are compared based on GP/ω in Eq. (2.5). First, GP/ω
calculated by measured Gt is shown in Fig. 4.4. Although we can see a symmetry curve
at E-Ei = 0.05eV, the others are not symmetry. In addition, the values of them become
zero in low frequency region. Generally, values of GP/ω cannot become zero.
Therefore, the probability that measured Gt is not correct is high. Next, GP/ω
calculated by approximated Gt is shown in Fig. 4.5. Compared with Fig. 4.1, it is found
that they are almost same. Therefore, it is considered the effect of leakage current is
small when approximated Gt is used. There is another reason leakage current is small.
C-V characteristic of this sample is shown in Fig. 4.6. If leakage current is large, the
phenomenon capacitance decreases in accumulation region is seen, but the
phenomenon does not occur from this figure. Because of the above reasons, it is
considered approximated Gt is proper.
27
-0.7
Gp /ω (x10-7 F/cm2)
3.5
E-Ei
3
0.05 eV
0.10 eV
0.15 eV
0.20 eV
2.5
2
1.5
1
0.5
Vamp = 25 mV
0
102
103
104
105
106
107
Frequency (Hz)
Fig. 4.4 GP/ω calculated by measured Gt. Most values become zero below 1kHz.
30
5
E-Ei
Gp /ω (x10-7 F/cm2)
0 eV
E-Ei
Vamp = 25 mV
-0.1 eV
25
0.05 eV
0.10 eV
0.15 eV
0.20 eV
4
0.1 eV
20
0.2 eV
3
15
2
10
1
5
Vamp = 100 mV
0
101
102
0
103 103
104
105
Frequency (Hz)
(a)
(b)
Fig. 4.5 GP/ω calculated by approximated Gt;
(a) low frequency region, (b) high frequency region.
28
106
107
Capacitance (µ
µF/cm2)
3
100kHz
1MHz
2.5
not
decrease
2
1.5
1
0.5
0
-2
-1.5
-1
-0.5
0
0.5
1
Gate Voltage (V)
Fig. 4.6 Capacitance does not decrease in accumulation region.
Therefore, leakage current is small.
4.3 Proposal of a new model
In paragraph 4.3, it was found that the peaks appearing in low frequency region were
not related to leakage current. So, we must consider other reasons. According to
Nicollian and Brews [16], there are two types of trap in the silicon. One is interface
traps located at or near the interface. The other is bulk traps, which are distributed
uniformly throughout the Si-substrate. Moreover, they reported bulk traps are mainly
measured in strong inversion region, and not measured in depletion region unless the
value of Dit is less than 1010 eV-1cm-2. However, the peak in low frequency region even
at E-Ei = 0.2eV is seen in Fig. 4.5(a). This means the peak is measured in depletion
region too. So, the probability that GP/ω curves are caused by bulk traps is small.
Therefore, it was considered that the peaks were caused by traps inside the oxide.
Schematic illustration expressed how electrons are captured and emitted is shown in
Fig. 4.7. Electrons transited from conduction band are trapped by traps near the surface.
It is the interface state. And it is considered electrons transited from conduction band
29
are trapped by defects inside the oxide. It is supposed this oxide trap causes GP/ω
curves. There are two reasons about this phenomenon.
First, the peaks appear in not high frequency region but low frequency region. This
means electrons cannot follow in the case of high frequency. Generally, capture and
emission time constant is short when electrons can follow high frequency. Therefore,
the place traps exist is near conduction band. On the contrary, in the case of low
frequency, the place traps exist is far from conduction band.
Second, the values of frequency in appearing the local maximum hardly change at
any energy level. From Fig. 4.5(b), it is found that values of frequency in appearing the
local maximum change about two digits when energy level changes 0.15 eV. On the
other hand, they do not change even one digit in spite of changing 0.30 eV in Fig.
4.5(a). Therefore, because capture and emission time constant does not depend on
surface potential much, it is considered electrons moves for horizon direction for a
long time in Fig. 4.7.
By the way, it is considered the equivalent parallel circuit in Fig. 2.12(a) is changed
to that in Fig. 4.8. Here, Cot is generated capacitance when electrons are captured and
emitted by the states inside the oxide, and Rot is generated losses then. It is supposed
that oxide traps are located near the surface. And it is considered that the systems of
capture and emission are also similar to those of interface traps. Therefore, Cot is the
capacitance generated by changing the surface potential. And then, Eq. (2.6) is
rewritten as
∞
[
]
q ⌠ Dit
2
= 
ln 1 + (ωτ it ) P(ψ S )dψ S
ω 2 ⌡−∞ ωτ it
GP
∞
[
]
q ⌠ Dot
2
+ 
ln 1 + (ωτ ot ) P(ψ S )dψ S ,
2 ⌡−∞ ωτ ot
(4.1)
where Dot is state density inside the oxide and τot is oxide trap time constant. In other
words, if this assumption is correct, GP/ω curves are expressed the sum of interface
traps and oxide traps. Thus, GP/ω curves are separated into interface trap and oxide
trap. Therefore, they may be able to be described accurately, and we can fond interface
state density even if any oxide is used. Also, because these peaks in low frequency
30
region are not always measured, it is considered we can remove them by proper
processes.
La2O3
Si
EC
Ef
Interface trap
EV
Oxide trap
Fig. 4.7 Energy-band diagram of interface trap and oxide trap.
COX
Gt
CS
Rit
Rot
Cit
Cot
Fig. 4.8 A new equivalent parallel circuit model of MOS capacitors.
4.4 Application of a new model to the measurement
In order to confirm whether the model supposed in paragraph 4.3 is correct,
calculation curves compared with measured curves as shown in Fig. 4.9. Calculation
curves in Fig. 4.9(a) are based on the second term in Eq. (4.1), and these curves do not
agree with measured plots even if values of σ are adjusted. It is found difference
31
between two is half breath. So, the assumption like Eq. (4.1) is probably a mistake, and
it is considered the state caused by oxide defects is single energy level. Therefore, Eq.
(4.1) is rewritten correctly as
∞
[
]
qωτ ot Dot
q ⌠ Dit
2
= 
ln 1 + (ωτ it ) P(ψ S )dψ S +
.
2
2 ⌡−∞ ωτ it
ω
1 + (ωτ ot )
GP
(4.2)
Curves calculated from the second term in Eq. (4.2) are shown in Fig. 4.9(b). As a
result, good agreement can be gained. Errors between calculation and measured curves
around 1 kHz are caused by interface traps. Because of this reason, oxide defects are
not influenced well by surface potential fluctuations. Fig. 4.10(b) shows curves
calculated from the first term in Eq. (4.2). These curves are caused by interface state.
And, it is found calculation agree with measurement in the region more than 10 kHz.
On the contrary, errors between calculation and measured curves in the region less than
10 kHz are caused by oxide traps.
Thus, it is found distribution of oxide defects have single energy level. Also,
measured GP/ω curves are expressed by the sum of interface traps and oxide traps.
Gp /ω (x10-7 F/cm2)
30
30
Statistic
fitting
25
25
20
20
15
15
10
10
5
0
101
5
Open dots : Measurement
Solid lines : Calculation
102
Single
level
fitting
Open dots : Measurement
Solid lines : Calculation
0
103 101
102
Frequency (Hz)
(a)
(b)
Fig. 4.9 Calculation curves compared with measured curves caused by oxide traps.
(a) Calculation curves are based on statistic model.
(b) Calculation curves are based on single level model.
32
103
Gp /ω (x10-7 F/cm2)
5
Statistic
fitting
4
Open dots : Measurement
Solid lines : Calculation
3
2
1
0
103
104
105
106
107
Frequency (Hz)
Fig. 4.10 Calculation curves based on statistic model compared with measured curves
caused by interface traps.
33
5 Conclusions
In this study, interface state and oxide defects are estimated by conductance method.
In consequence, peaks of GP/ω curves caused by interface state are measured in
SiO2/Si structure. However, the signal responding low frequency is measured in
high-k/Si structure. It is considered they are caused by defects inside the oxide.
Because the traditional equivalent parallel circuit model is considered only interface
traps, new one is supposed in order to estimate that in detail. As a result, separating
GP/ω curves into interface state and oxide defects is succeeded. It is considered that the
quantification of interface traps and oxide traps is very effective in order to discuss
interfacial properties of MOS devices.
34
Appendices
A. The derivation of calculation changing equivalent circuit model to
simplified circuit
The admittance except COX and Gt in Fig. 2.12(a) is given by
Ya = jωC S +
= jω C S +
= jω C S +
1
Rit +
1
jωC it
jωC it
1 + jωτ it
jωqDit (1 − jωτ it )
1 + (ωτ it )
2
,
(A.1)
where we replace Cit = qDit, and τit = CitRit. And, the admittance except COX and Gt in
Fig. 2.12(c) is given by
Yc = jωC P + G P .
(A.2)
The real part and imaginary part in Eq. (A.1) and (A.2) are compared respectively, so
that we can obtain
CP = CS +
GP
ω
=
qDit
1 + (ωτ it )
qωτ it Dit
1 + (ωτ it )
2
2
,
.
(A.3)
(A.4)
B. The derivation of calculation changing measured circuit to
simplified circuit
First, Equivalent parallel circuit is partially replaced impedance and admittance in
order to explain simply like Fig. B.1. Because the total impedance and admittance of
these two circuits are equal each other, the equations are given by
Yt =
1
+ Gt = Gm + jωC m ,
Z0
Z0 =
1
1
.
+
jωC OX G P + jωC P
35
(B.1)
(B.2)
We obtain next equation from Eq. (B.1) and (B.2).
1
1
1
=
−
G P + jωC P Gm − Gt + jωC m jωC OX
(B.3)
The reciprocal of Eq. (B.3) is
G P + jωC P =
=
1
1
1
−
Gm − Gt + jωC m jωC OX
jωC OX (Gm − Gt + jωC m )
jωC OX − (Gm − Gt + jωC m )
=−
=−
jωC OX (Gm − Gt + jωC m )
(Gm − Gt ) − jω (COX − C m )
jωC OX ⋅ jω [C m (G m − Gt ) + (C OX − C m )(Gm − Gt )]
(Gm − Gt )2 + ω 2 (COX
− Cm )
2
+ jω L
ω 2 (Gm − Gt )COX 2
=
+ jω L .
(Gm − Gt )2 + ω 2 (COX − C m )2
(B.4)
Because the amount of calculation is much, the calculation of imaginary part was
omitted. The real part in Eq. (B.4) is compared, so that we can obtain
GP
ω
=
ω (Gm − Gt )COX 2
.
(Gm − Gt )2 + ω 2 (COX − C m )2
(B.5)
Z0
COX
Gt
CP
Cm
Gm
GP
Yt
Fig. B.1 Equivalent parallel circuit is partially replaced impedance and admittance in
order to explain simply.
36
C. The derivation of calculation changing measured circuit to
equivalent circuit model
First, we change Fig. 2.12(c) to (b) contrary to Appendix B. We want information of
Cm, so the calculation of real part is omitted. In Fig. B.1, we obtain next equation from
Eq. (B.1) and (B.2).
Gm + jωC m =
1
1
1
+
G P + jωC P jωC OX
+ Gt
=
jωC OX (G P + jωC P )
+ Gt
jωC OX + (G P + jωC P )
=
jωC OX (G P + jωC P )
+ Gt
G P + jω (C OX + C P )
=
[
]+ G +L
jωCOX G P + ω 2 C P (COX + C P )
2
G P + ω 2 (C OX + C P )
2
2
t
(C.1)
The imaginary part in Eq. (C.1) is compared, so that we can obtain
 GP  2

COX 
 + C P (COX + C P )
 ω 

Cm =
.
2
 GP 
2

 + (COX + C P )
 ω 
37
(C.2)
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38
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[16] Nicollian & Brews: “MOS Physics and Technology”, p.111, Wiley Interscience,
United States of America (2003).
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Acknowledgements
First of all, the author would like to express gratitude to his supervisor Prof. Hiroshi
Iwai. The author could gain the results of this study because of his continuous
encouragement and advices. He also gave the author the opportunity to attend the
conference. The experience is precious for the author’s life.
The author also deeply thanks Prof. Takeo Hattori, Prof. Kenji Natori, Prof.
Nobuyuki Sugii, Prof. Akira Nishiyama, Prof. Kazuo Tsutsui, Associate Prof. Parhat
Ahmet, and Assistant Prof. Kuniyuki Kakushima for giving him useful advices and
great help whenever he faced difficult problems.
The author also thanks the members of Iwai Lab. for their friendship, active many
discussions and many of encouraging words.
The author also thanks secretaries, Ms. Matsumoto, Ms. Nishizawa, and Ms.
Karakawa for supporting him and the members of Iwai Lab.
Finally, the author would like to thank his parents Akira and Chieko and his brother
Naoki for endless support and encouragement.
40