ECE 546
VLSI Systems Design
Fall 2012
W. Rhett Davis
NC State University
with significant material from Rabaey, Chandrakasan, and Nikolić
© W. Rhett Davis
NC State University
Slide 1
ECE 546
Fall 2012
Announcements

HW#1 Due in 12 Days
© W. Rhett Davis
NC State University
Slide 2
ECE 546
Fall 2012
Today’s Lecture

Course Introduction

Syllabus

Transistor Models (3.3)
© W. Rhett Davis
NC State University
Slide 3
ECE 546
Fall 2012
ECE 546: A Course in Building Stuff
ROM
MCU
DSP
Gates
(RTL)
Cellular Phone
Baseband SOC
RAM
Source: Mike McMahon,
Texas Instruments

What level of abstraction will we use?
© W. Rhett Davis
NC State University
Slide 4
ECE 546
Fall 2012
Our View of the World…



No Register-Transfer
Level (RTL) Verilog
No Synthesis Tools
These are covered in
ECE 520
(ASIC Design)
OK, so, we can build stuff, but how do we build stuff well ?
© W. Rhett Davis
NC State University
Slide 5
ECE 546
Fall 2012
Moore’s Law

In the early 1960’s, Gordon Moore of Intel
recognized that manufacturing capability had
been increasing exponentially, with a doubling
of the maximum number of transistors on a chip
every 18 months.

Economic Law
» Tells us how to make semiconductors profitable
» Gives manufacturers a steadily moving target for
yield and feature sizes
» Gives chip designers a steadily moving target for the
complexity of their integrated systems
© W. Rhett Davis
NC State University
Slide 6
ECE 546
Fall 2012
40 Years of Moore’s Law
Transistors
Per Die
108
(This trend continues today)
256M
Memory
Microprocessor
107
106
105
104
4K 16K
1K
256K
80286
1M
4M
i486™
Pentium®
Pentium® III
Pentium® II
Pentium® Pro
i386™
8086
103
102
64K
16M
64M
8080
4004
101
100
’70
’73
© W. Rhett Davis
’76
’79
’82
NC State University
’85
’88
Slide 7
’91
’94
'97
2000
Source: Intel
ECE 546
Fall 2012
Chips Got Faster!
10,000

Frequency doubles
each generation
1,000
Pentium® III
» When will Moore’s
Law end?
proc
Mhz
Pentium II
Pentium Pro
Pentium proc
100
How fast can they
get?
proc
proc
i486

Problems
» Power Dissipation
» Rising NRE Costs
i386
– Lithography / Masks
– Design Effort









10
Source: Intel
© W. Rhett Davis
NC State University
Slide 8
ECE 546
Fall 2012
Power Dissipation
Lead microprocessors power continued to increase
Power (Watts)
100
P6
Pentium ®
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Source: Borkar, De Intel
© W. Rhett Davis
NC State University
Slide 9
ECE 546
Fall 2012
What Happened? Chip Power Density
Sun’s
Surface
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086 Hot Plate
10 4004
P6
8008 8085
Pentium®
386
286
486
8080
1
1970
1980
1990
Year
2000
2010
Source: Borkar, De Intel
© W. Rhett Davis
NC State University
Slide 10
ECE 546
Fall 2012
Power Consumption a Leading Problem

“Intel Corp. has cancelled its single-core processor
development efforts …. With the 90-nm single-core
Prescott version of the Pentium 4, Intel has run into
power consumption problems that stem from design
issues more than process technology”
» - from “Intel cancels Tejas, moves to dual-core designs”,
EE Times, May 7, 2004

To reduce power,
Intel has moved to multicore processors
Intel 65nm Quad-Core Itanium, ISSCC 2008
© W. Rhett Davis
NC State University
Slide 11
ECE 546
Fall 2012
New Power / Frequecncy Trends

Around 2005, micro-processors hit a
plateau of around 5 GHz clock and 100
W/cm2 power density
Source: Rusu, Intel Corp., 2004
© W. Rhett Davis
NC State University
Slide 12
ECE 546
Fall 2012
To Save Power, Scale Voltage
Source:
Rusu, Intel Corp.,
2004


Reducing the supply voltage reduces the power
Limited by threshold voltages
» must reduce threshold voltage by the same amount
» Leads to exponential increase in leakage/standby power
© W. Rhett Davis
NC State University
Slide 13
ECE 546
Fall 2012
The Problem of Standby Power

Standby/Leakage
power is an everincreasing portion of
total power

Designers must pull
many tricks to limit
this power in mobile
systems
Source: Rusu, Intel Corp., 2004
© W. Rhett Davis
NC State University
Slide 14
» e.g. turn off parts of
the chip that are not
in use.
ECE 546
Fall 2012
Battery Size/Weight
50
Nominal Capacity (W-hr/lb)
Rechargable Lithium
Battery
(40+ lbs)
40
Ni-Metal Hydride
30
20
Nickel-Cadmium
10
0
Source: Rabaey, UC Berkeley



65
70
75
80
85
90
95
Year
Battery lifetime not increasing exponentially
Today’s best batteries have capacity ~75 W-hr/lb
Dynamite has capacity ~1000 W-hr/lb
© W. Rhett Davis
NC State University
Slide 15
ECE 546
Fall 2012
Increasing Fabrication Costs
Process
Min. Charge
$3,000
AMS 0.8 m
$5,000
AMI 0.5 m
TSMC 0.35 m $8,680
TSMC 0.25 m $14,000
TSMC 0.18 m $22,400
$45,000
IBM 0.13 m

Min. Area
6 mm2
5 mm2
7 mm2
10 mm2
7 mm2
10 mm2
Lithography / Mask issues drive up costs
» Optical Proximity Correction (OPC)
» Phase-Shift Masks
» Immersion Lithography

See http://www.mosis.org for a current quote
© W. Rhett Davis
NC State University
Slide 16
ECE 546
Fall 2012
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Design Productivity Gap
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
“Cost of design is the greatest threat to continuation
of the semiconductor roadmap” – ITRS
http://public.itrs.net
© W. Rhett Davis
NC State University
Slide 17
ECE 546
Fall 2012
Sources of Variation
1) Dopant Fluctuation
2) Lithography Effects
source: Bernstein, et al., IBMJR&D’06
3) Wire Capacitance Variation
source: Mentor Graphics
source: K. T. Cheung, UCSB
© W. Rhett Davis
NC State University
Slide 18
ECE 546
Fall 2012
Times may look tough…
…but don’t lose
sight of the
dream!
© W. Rhett Davis
NC State University
Slide 19
ECE 546
Fall 2012
Today’s Lecture

Course Introduction

Syllabus

Transistor Models (3.3)
© W. Rhett Davis
NC State University
Slide 20
ECE 546
Fall 2012
What is a Transistor?
A Switch!
A MOS Transistor
VGS  VT
S
© W. Rhett Davis
|VGS|
Ron
D
NC State University
Slide 21
ECE 546
Fall 2012
The MOS Transistor
Polysilicon
© W. Rhett Davis
NC State University
Slide 22
Aluminum
ECE 546
Fall 2012
MOS Transistors - Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
D
G
S
S
PMOS Enhancement
© W. Rhett Davis
NC State University
B
NMOS with
Bulk Contact
Slide 23
ECE 546
Fall 2012
Threshold Voltage: Concept
+
S
VGS
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
B
© W. Rhett Davis
NC State University
Slide 24
ECE 546
Fall 2012
Standard NMOS I-V Curves
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
© W. Rhett Davis
NC State University
Slide 25
ECE 546
Fall 2012
Transistor in Linear
VGS
S
VDS
G
n+
– V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
© W. Rhett Davis
NC State University
Slide 26
ECE 546
Fall 2012
Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
© W. Rhett Davis
NC State University
Slide 27
ECE 546
Fall 2012
Long-Channel I-V Model
© W. Rhett Davis
NC State University
Slide 28
ECE 546
Fall 2012
A model for manual analysis
© W. Rhett Davis
NC State University
Slide 29
ECE 546
Fall 2012
Deep-Submicron I-V Curves
2.5
x 10
-4
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
ID (A)
1.5
VGS= 1.5 V
1
0.5
0
Linear
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
© W. Rhett Davis
NC State University
Slide 30
ECE 546
Fall 2012
 n (m/s)
Velocity Saturation
sat = 105
Constant velocity
Constant mobility (slope = µ)
c = 1.5
© W. Rhett Davis
NC State University
Slide 31
 (V/µm)
ECE 546
Fall 2012
Short-Channel I-V Model
ID
W
1
ID 
k
 VDS  L

1  
 C L 
2

VDS 
VGS  VT VDS 
1   VDS 
2


Long-channel device
VGS = VDD
Short-channel device
V DSAT
© W. Rhett Davis
(Take ECE 557
for a better
explanation…)
VGS - V T
NC State University
VDS
Slide 32
ECE 546
Fall 2012
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
2
2.5
0
0
0.5
VGS(V)
NC State University
1.5
2
2.5
VGS(V)
Long Channel
© W. Rhett Davis
1
Short Channel
Slide 33
ECE 546
Fall 2012
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
VDS(V)
1.5
2
2.5
0
0
Long Channel
© W. Rhett Davis
NC State University
0.5
1
VDS(V)
1.5
2
2.5
Short Channel
Slide 34
ECE 546
Fall 2012
Simplified Model for Velocity Saturation

Assume abrubt transition from saturation to
velocity saturation.

Assume VDS term ≈ LξC (constant throughout
Velocity Saturation Region)
Call this Value VDSAT

New equation:
W
I D  k
L
© W. Rhett Davis
2

VDSAT 
VGS  VT VDSAT 
 1   VDS 
2 

NC State University
Slide 35
ECE 546
Fall 2012
A unified model for manual analysis
G
S
D
B



© W. Rhett Davis
Triode when Vmin=VDS
Saturation when Vmin=VGS-VT
Velocity Saturated when Vmin=VDSAT
NC State University
Slide 36
ECE 546
Fall 2012
Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
2
2.5
VDS (V)
These plots compares this model to simulations
in a 250nm technology
© W. Rhett Davis
NC State University
Slide 37
ECE 546
Fall 2012
A PMOS Transistor
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
ID (A)
-0.4
-0.6
-0.8
-1
-2.5
VGS = -2.0V
Assume all variables
negative!
VGS = -2.5V
-2
-1.5
-1
-0.5
0
VDS (V)
© W. Rhett Davis
NC State University
Slide 38
ECE 546
Fall 2012
Problem: Low Output Resistance
Vgs = 1.1V
Good Match!
VTL NMOS W=90nm L=50nm
0.00012
HSPICE 0V
0.0001
HSPICE 0.3V
HSPICE 0.5V
0.00008
HSPICE 0.7V
Id
0.00006
HSPICE 0.9V
HSPICE 1.1V
0.00004
HandPrm 0V
HandPrm 0.3V
0.00002
HandPrm 0.5V
0
0
0.2
0.4
0.6
0.8
-0.00002
Vds
1
1.2
HandPrm 0.7V
HandPrm 0.9V
HandPrm 1.1V
Vgs = 0.5V
Model doesn’t capture the
low output resistance
© W. Rhett Davis
NC State University
Slide 39
ECE 546
Fall 2012
Drain-Induced Barrier Lowering (DIBL)

In short-channel
MOSFETs, VDS can pull
down the potential barrier
in the channel

We model this as a VT
dependence on VDS
VT  VT 0  BVDS
 VT 0  VT
source: Van der Tol, Trans. El. Dev.’93
© W. Rhett Davis
NC State University
Slide 40
(Thanks to Harun Demircioglu
for coming up with this model)
ECE 546
Fall 2012
Model Improvement with DIBL
VTL NMOS W=90nm L=50nm
0.00012
HSPICE 0V
0.0001
HSPICE 0.3V
HSPICE 0.5V
0.00008
HSPICE 0.7V
Id
0.00006
HSPICE 0.9V
without ∆VT
HSPICE 1.1V
0.00004
HandPrm 0V
HandPrm 0.3V
0.00002
HandPrm 0.5V
0
0
0.2
0.4
0.6
0.8
1
1.2
-0.00002
HandPrm 0.7V
HandPrm 0.9V
HandPrm 1.1V
Vds
VTL NMOS W=90nm L=50nm
0.00012
HSPICE 0V
0.0001
HSPICE 0.3V
HSPICE 0.5V
0.00008
HSPICE 0.7V
Id
0.00006
HSPICE 0.9V
HSPICE 1.1V
0.00004
HandPrm 0V
HandPrm 0.3V
0.00002
HandPrm 0.5V
0
0
0.2
0.4
0.6
0.8
1
1.2
-0.00002
Vds
© W. Rhett Davis
NC State University
HandPrm 0.7V
HandPrm 0.9V
with ∆VT
(Matches better for
low values of Vgs)
HandPrm 1.1V
Slide 41
ECE 546
Fall 2012
Hand Analysis Parameters
VT0 (V)  (V0.5) VDSAT (V)
NMOS VTL
0.32
0.4
PMOS VTL
-0.32
-0.4
NMOS VTG
0.4
0.4
PMOS VTG
-0.4
-0.4
NMOS VTH
0.6
0.4
PMOS VTH
-0.6
-0.4

k’ (A/V2) (V-1) B (V/V)
240x10-6
0.1
0.10
-0.35 -130x10-6
-0.2
0.10
210x10-6
0.1
0.08
-0.35 -120x10-6
-0.2
0.10
200x10-6
0.1
0.03
-0.30 -120x10-6
-0.1
0.10
0.31
0.33
0.34
Use on all problems unless otherwise noted
© W. Rhett Davis
NC State University
Slide 42
ECE 546
Fall 2012
Summary: Standard Equations

Linear / Tridode Region:
W
ID  k
L

Saturation Region:
ID 

2

VDS 
VGS  VT VDS 

2


k W
VGS  VT 2 1   VDS 
2 L
Velocity Saturated Region:
W
1
ID 
k
 VDS  L

1  
 C L 

Subthreshold Region:
ID  ISe

2

VDS 
 1   VDS 
VGS  VT VDS 
2


VGS
nkT / q
V
 DS 

1  e kT / q 




Threshold Voltage:
© W. Rhett Davis
NC State University
VT  VT 0  
Slide 43

 2F  VSB   2 F
ECE 546

Fall 2012
Summary: Unified Model
for VGS  VT   0
ID  0
W
I D  k
L
2

Vmin 
VGS  VT Vmin 
 1   VDS 
2 

for VGS  VT   0
Vmin  min VGS  VT ,VDS ,VDSAT 
VT  VT 0  BVDS  



 2F  VSB   2F

Use Vmax for PMOS
Use ∆VT = BVDS to model DIBL
© W. Rhett Davis
NC State University
Slide 44
ECE 546
Fall 2012