mm
40
60
80
100
120
5.
40 CMOS Gates: DC and Transient Behavior
J. A. Abraham
60
Department
of Electrical and Computer Engineering
The University of Texas at Austin
80
ECE Department, University of Texas at Austin
VLSI Design
Fall 2015
September 14, 2015
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
1 / 35
Topics
mm
40
60
80
100
120
DC Response
40
Logic Levels and Noise Margins
Transient Response
Delay Estimation
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
1 / 35
Transistor Behavior
mm
40
60
80
100
Behavior in different situations (increase, decrease, or not
change).
120
1
If the width of a transistor increases, the current will
2
If40the length of a transistor increases, the current will
3
If the supply voltage of a chip increases, the maximum
transistor current will
4
If the width of a transistor increases, its gate capacitance will
5
If the length of a transistor increases, its gate capacitance will
6
If the supply voltage of a chip increases, the gate capacitance
of each transistor will
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
2 / 35
Transistor Behavior
Behavior in different situations (increase, decrease, or not
mm
40
60
80
100
change).
120
1
If the width of a transistor increases, the current will increase
2
If the length of a transistor increases, the current will
decrease
40
3
If the supply voltage of a chip increases, the maximum
transistor current will increase
4
If the width of a transistor increases, its gate capacitance will
60
increase
5
If the length of a transistor increases, its gate capacitance will
increase
6
If the supply voltage of a chip increases, the gate capacitance
80 each transistor will not change
of
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
3 / 35
DC Response: Vout vs. Vin for a Gate
mm
40
60
Study the response of Inverters
80
100
120
When Vin = 0 =⇒ Vout = VDD
When Vin = VDD =⇒ Vout = 0
40
In between, Vout depends on
transistor size and current
By KCL, current must be such that
Idsn
60 = |Idsp |
We could solve equations, but
graphical solution gives more
insight
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
4 / 35
Transistor Operation
Current through transistor depends on the region of operation
mm
40 for what60
Need to identify
Vin and Vout80are nMOS100
and pMOS 120
in Cutoff, Linear or Saturation
nMOS Operation
40
Cutoff
Vgsn < Vtn
Vin < Vtn
60
Linear
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn − Vtn
Vout < Vin − Vtn
Saturated
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn − Vtn
Vout > Vin − Vtn
Vgsn = Vin
Vdsn = Vout
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
5 / 35
pMOS Operation
mm
40
Cutoff
Vgsp > Vtp
Vin > VDD + Vtp
40
60
Linear
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp − Vtp
Vout > Vin − Vtp
80
100
120
Saturated
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp − Vtp
Vout < Vin − Vtp
Vgsp = Vin − VDD
60
Vdsp = Vout − VDD
Vtp < 0
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
6 / 35
I-V Characteristics
Make pMOS wider than nMOS such that βn = βp
β = mm
µCox W
L
40
60
80
100
120
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
7 / 35
Current vs. Vout , Vin
mm
40
60
80
100
120
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
8 / 35
Load Line Analysis
mm
40 a given V 60
80
To find the Vout for
in
For a given Vin , plot Idsn , Idsp vs. Vout
100
120
Vout must be where |currents| are equal in the graph below
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
9 / 35
DC Transfer Curve
mm
40
60
Transcribe points on to Vin vs. Vout plot
80
100
120
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
10 / 35
Operating Regions
mm
40
60
Revisit transistor operating regions
Region
A
B
C
D
E
nMOS
40
Cutoff
Saturation
Saturation
Linear
60
Linear
80
100
120
pMOS
Linear
Linear
Saturation
Saturation
Cutoff
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
11 / 35
Beta Ratio
mm
40
60
80
100
120
If βp /βn 6= 1,
40
switching
point will
move from VDD /2
Called skewed gate
60
Analysis of more complex gates
80
Collapse into equivalent inverter
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
12 / 35
Noise Margins
How much noise can a gate input see before it does not recognize
mm
40
60
80
100
120
the input?
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
13 / 35
Logic Levels
To maximize noise margins
Select logic levels
at unity60gain point 80
of DC transfer
mm
40
100
characteristic
120
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
14 / 35
Transient Response
mm
60 if V is constant
80
DC analysis40
gives the Vout
in
100
120
Transient analysis tells us Vout as Vin changes
Input is usually considered to be a step or ramp (from 0 to
VDD or vice-versa)
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
15 / 35
Inverter Step Response
Find the step response of an inverter driving a load capacitance
mm
40
60
Vin (t) = u(t − t0 )VDD
80
100
120
Vout (t < t0 ) = VDD
dVout (t)
dt
(t)
= − ICdsn
load
40
60
Idsn80
(t) =




 β VDD − Vt −
ECE Department, University of Texas at Austin
t ≤ t0
Vout > VDD − Vt
0
β
2 (VDD
− V )2
Vout (t)
2
Vout (t) Vout < VDD − Vt
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
16 / 35
Delay Definitions
tpdr : rising propagation delay
From input to rising output crossing VDD /2
mm
40
60
80
tpdf : falling propagation delay
100
120
From input to falling output crossing VDD /2
tpd : average propagation delay
tpd = (tpdr + tpdf )/2
40
tr : rise time
From output crossing 0.2 VDD to 0.8 VDD
tf : fall time
From output crossing 0.8 VDD to 0.2 VDD
60
tcdr : rising contamination delay
Minimum time from input to rising output crossing VDD /2
tcdf : falling contamination delay
80
Minimum time from input to falling output crossing VDD /2
tcd : average contamination delay
tcd = (tcdr + tcdf )/2
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
17 / 35
Simulated Inverter Delay
Solving differential equations by hand too hard
mm
SPICE simulator
numerically
40 solves equations
60
80
Uses more accurate I-V models too!
100
120
But simulations take time to write
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
18 / 35
Delay Estimation
mm
40
60
80
100
120
We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask “what if ...”?
The
40 step response usually looks like a first order RC response
with a decaying exponential
Use RC delay models to estimate delay
60
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
19 / 35
Example: Sizing 3-Input NAND Gate for Equal Rise and
Fall Times
mm
40
60
80
100
120
40
60
Determine the transistor widths to achieve effective rise and fall
resistances
(times) equal to that of a unit inverter R
80
Annotate the 3-input NAND gate with gate and diffusion
capacitances
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
20 / 35
Example 3-Input NAND Gate
mm
40
60
80
100
120
40
60
Determine the transistor widths to achieve effective rise and fall
resistances (times) equal to that of a unit inverter R
80
Annotate the 3-input NAND gate with gate and diffusion
capacitances
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
21 / 35
Example: Sizing Complex Gate
Size the transistors in the circuit mm
below so that
it has the60
40
same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi40
ble to achieve this ratio.
80
100
120
Note: if there are multiple
paths 60
through a transistor, use
the size for the “worst-case” input combination.
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
22 / 35
Example: Sizing Complex Gate
Size the transistors in the
circuit below so that it has
mm drive strength,
40
the same
in the60
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possible to40
achieve this ratio.
80
100
120
This solution does NOT use the
smallest widths
Note:60 if there are multiple
paths through a transistor, use
the size for the “worst-case” input combination.
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
23 / 35
Example: Sizing of Complex Gate – Better Solution
Size the transistors in the
circuit
that it has60
mmbelow so 40
the same drive strength, in the
worst case, as an inverter that
has PW = 5 and NW = 3.
Use the smallest widths possi40
ble to achieve this ratio.
80
100
120
Note: if there are multiple
paths 60
through a transistor, use
the size for the “worst-case” input combination.
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
24 / 35
Elmore Delay
Finding the delay of ladder networks
ON transistors look like resistors
mm
40
60
80
100
Pullup or pulldown network modeled as RC ladder
120
Elmore delay of RC ladder
tpd 40
=
X
Ri−to−source Ci
nodes i
= R1 C1 + (R1 + R2 )C2 + . . . + (R1 + R2 + . . . + RN )CN
60
80
NOTE: Ci includes all the “off-path” capacitance on nodes that
are connected to node i
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
25 / 35
Example: Delay of 2-Input NAND Using Elmore
Formulation
mm rising and
40 falling propagation
60
80 of a 2-input
100 NAND 120
Estimate
delays
driving h identical gates
40
60
80
ECE Department, University of Texas at Austin
tpdr = (6 + 4h)RC
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
26 / 35
Example: Delay of 2-Input NAND Using Elmore
Formulation
mm
40
60
80
100
Estimate rising and falling propagation delays of a 2-input NAND
driving h identical gates
120
40
60
tpdf
80
ECE Department, University of Texas at Austin
R
R R
= (2C) + (6 + 4h)C
+
2
2
2
= (7 + 4h)RC
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
27 / 35
Example of Elmore Delay Calculation
Calculate the Elmore delay from C to F in the circuit. The widths
mm
40 are shown,
60 and the 80
100
120
of the
pass transistors
inverters have
minimum-sized transistors
40
60
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
28 / 35
Example of Elmore Delay Calculation
Calculate the Elmore delay from C to F in the circuit. The widths
of the pass transistors are shown, and the inverters have
mm
40
60
80
100
120
minimum-sized transistors
40
60
80
R
R
R R
Delay = 9C + 5C +
+
7C + 3RC = 12.33RC
3
3
3
3
off-path
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
29 / 35
Another Example: Elmore Delay Calculation
Use the Elmore delay approximation to find the worst-case rise and fall
delays at output F for the following circuit. The gate sizes of the
mm are shown
40 in the figure.
60 Assume NO80sharing of diffusion
100
120
transistors
regions, and the worst-case conditions for the initial charge on a node.
Input for worst-case rise delay =
40
Worst-case rise delay =
Input for worst-case fall delay =
60
Worst-case fall delay =
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
30 / 35
Delay with Different Input Sequences
Find the delays for the given input
transitions (gate sizes shown in figure)
mm
40
60
80
100
120
Assumptions: diffusion capacitance is
equal to the gate capacitance, the
resistance of an nMOS transistor with
unit width is R and the resistance of a
40
pMOS transistor with width 2 is also R,
and NO sharing of diffusion regions
Off-path capacitances can contribute to
delay, and 60
if a node does not need to be
charged (or discharged), its capacitance
can be ignored
ABCD = 0101 → ABCD = 1101
80
ABCD = 1111 → ABCD = 0111
ABCD = 1010 → ABCD = 1101
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
31 / 35
Delay with Different Input Sequence, Cont’d
Look at the charges on the nodes
at the end of the first input of the
sequence;
mm only the40capacitances
60
of the nodes which would change
with the second vector need to be
considered
80
100
120
40 = 0101 →
ABCD
ABCD = 1101;
Delay = 36RC
ABCD
60 = 1111 →
ABCD = 0111;
Delay = 16RC
ABCD = 1010 →
80
ABCD = 1101;
Delay = 43RC
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
32 / 35
Delay Components
mm
40
60
80
100
120
Delay has two parts
Parasitic Delay
640or 7 RC
Independent of Load
Effort Delay
60 RC
4h
Proportional to load capacitance
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
33 / 35
Contamination Delay
Minimum (Contamination) Delay
mm
40
60
80
100
120
Best-case (contamination) delay can be substantially less than
propagation delay
Example, If both inputs fall simultaneously
Important
for “hold time” (will see later in the course)
40
60
80
ECE Department, University of Texas at Austin
tcdr =
(3 + 2h)RC
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
34 / 35
Diffusion Capacitance
We assumed contacted diffusion on every source/drain
Good layout minimizes diffusion area
mm
40
60
80
100
Example, NAND3 layout shares one diffusion contact
120
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
40
60
These80general observations can be used for initial estimates of area
and performance – using tools to extract parasitics will provide
more accurate results for a particular technology
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 14, 2015
35 / 35