Invited Paper
Silicon On Insulator Inertial MEMS Device Processing
William D. Sawyer and Mert S. Prince
The Charles Stark Draper Laboratory, 555 Technology Square, Cambridge, MA 02139.
Abstract
During the 1980’s and 1990’s the methods used to manufacture inertial MEMS devices could be divided into two
groups; bulk and surface micromachining. Institutions which developed high precision inertial MEMS devices usually
employed bulk micromachining processes. This was done to fabricate devices with large proof masses and stiff beams
which result in a high scale factor, as well as high drive, and sense frequencies. New processes have been developed
which are based on silicon on insulator (SOI) wafers. These processes combine the advantages of bulk and surface
micromachining while enabling the etching of thick proof masses. This paper illustrates the manufacturing and
performance advantages of an SOI inertial MEMS process.
Keywords: Inertial Navigation, Microelectromechanical devices, Silicon on insulator technology, Semiconductor
device fabrication
Introduction
Inertial microelectromechanical (MEMS) devices consist of accelerometers and angular rate sensors, otherwise known
as gyroscopes. The largest volume application for these sensors is in automotive markets. Commercial applications such
as accelerometers used in lap top computers for emergency hard disk parking are also growing in volume. There is
significant price pressure on such high-volume sensors. Manufacturers achieve low costs by compromising on the
inertial performance of the devices through the use of surface micromachining techniques. Automotive gyroscopes, for
example, typically have a bias over temperature and turn off of several hundred to a few thousand deg/h. There is a
growing market for more accurate accelerometers and gyroscopes. Their first use will be in military applications, such
as artillery shell and mortar guidance. Tactical gyroscopes of this type usually require a bias over temperature and turn
off on the order of 1 to 10 deg/h. There are currently very few companies that can supply tactical grade gyroscopes in
volume.
Manufacturers of tactical grade MEMS accelerometers and gyroscopes achieve high accuracy by reducing inertial
errors. They do this largely by manufacturing devices with a large signal to noise ratio. This is achieved by designing
devices with a large scale factor, which in turn requires thicker proof masses than would be used in a commercial grade
MEMS device. For this reason, tactical grade MEMS devices are commonly made using a bulk micromachining
process. The most common bulk micromachining process used is the dissolved wafer process [1, 2]. The dissolved
wafer process has been used to make gyroscopes with noise levels as low as 5 to 10 deg/h/√Hz [2, 3]. It is schematically
shown in fig. 1.
The dissolved wafer process begins with a glass wafer. Typically Pyrex™ or Hoya SD-2™ glass is chosen because their
thermal expansion coefficient closely matches the thermal expansion coefficient of Si (fig. 1A). Recesses are etched
into the glass where metalization will be deposited, which is shown in fig. 1B. Metal is deposited onto the glass
substrate wafer by sputtering or evaporation. Fig. 1C shows that the metalization should protrude several 100 Å from
the surface of the glass.
The next step in the dissolved wafer process is to diffuse a high concentration of B (1019 - 1020 atoms/cm3) into a
moderately B doped Si wafer (typically < 0.1 Ωcm). This step is shown in fig. 1E. The depth to which the high B
concentration extends into the Si substrate will determine the thickness of the proof mass. As shown in fig. 1F, mesas
are etched into the B diffused layer. Fig. 1G shows the definition of the proof mass shape as the result of a deep
anisotropic etch into the Si wafer using an inductively coupled plasma (ICP) [4]. The ICP etch begins on the highly B
doped Si surface, and extends into the moderately doped region of the Si wafer.
MEMS/MOEMS Components and Their Applications III,
edited by Scot S. Olivier, Srinivas A. Tadigadapa, Albert K. Henning,
Proc. of SPIE Vol. 6113, 611302, (2006) · 0277-786X/06/$15 · doi: 10.1117/12.657138
Proc. of SPIE Vol. 6113 611302-1
F
G
H
E
Glass Substrate Wafer
Metallization
B diffused layer
UlIffi Si Substrate Wafer
Fig. 1. Schematic diagram of the dissolved wafer process.
The Si wafer is then anodically bonded to the glass substrate wafer such that the high B concentration is bonded to the
glass, as shown in fig. 1H. The anodic bond process step is performed at 335° C. This temperature is chosen to reduce
the resistivity of the glass. A higher temperature risks damage to the metalization. Finally, the Si and glass wafer stack
are etched in Ethylenediamine Pyrocatechol (EDP), which is shown in fig, 1I. This step removes the substrate Si, but
does not etch the glass wafer or the metalization. Often, the substrate Si is thinned to within several 10’s of µm of the
highly doped B layer using Potassium Hydroxide (KOH) before performing the EDP etch. The advantage of using KOH
is that it etches Si at a much higher rate than EDP. However, KOH is not a good substitute for EDP because it does not
stop etching on highly doped Si as well as EDP.
The dissolved wafer process as presented in fig. 1 has well known disadvantages. The high B concentration results in a
high dislocation concentration in the Si part of the device. The Si surfaces are not flat, and the dimensions of the smaller
device parts, such as oscillator beams and motor fingers are difficult to control during the ICP etch. In addition, a
Proc. of SPIE Vol. 6113 611302-2
significant stress is built into the Si. This results, for example, in a vertical offset between the gyroscope proof mass,
and the motors which drive its motion, causing an error in the gyro bias. There is also a practical limit to the depth that a
high B concentration can be diffused into a Si wafer. The deeper the heavily doped B layer must be diffused into the Si,
the longer the diffusion time, and the greater the initial cost of the device.
The stress built into the Si lattice due to the high B concentration can be reduced by using what the authors call the
modified dissolved wafer process [6]. This process is described in detail in reference 6. The modified dissolved wafer
process uses an epitaxially grown layer of SiGeB to define the thickness of the proof mass. There is less stress built into
the Si lattice, because the strain induced by the high concentration of small atomic sized B is compensated by the larger
sized Ge atoms. The modified dissolved wafer process results in a flat Si surface, and the dimensions of the smaller
device parts can be accurately controlled. In addition, the thickness of the proof mass can be better controlled in an
epitaxial deposition than in a diffusion tube. As more device manufacturers use the modified dissolved wafer process to
manufacture various MEMS devices, the availability of epitaxial SiGeB has increased. Wafers with custom grown
epitaxial SiGeB can be ordered from Okmetic, for example [7].
The modified dissolved wafer process reduces the stress built into the Si lattice, but it does not eliminate it. The vertical
offset between gyroscope proof mass and motors is still present. The process uses EDP, which is a known carcinogen.
There is significant anecdotal evidence that operators who have inhaled EDP fumes become sensitized and develop
asthma. For these reasons, manufacturers of tactical grade inertial devices are switching from epitaxial SiGeB based
manufacturing to using a process based on silicon on insulator (SOI) wafers.
Thick SOI Wafer Process
There is wide use of SOI wafers in the microelectronics industry. The buried oxide in SOI wafers results in increased
CMOS transistor switching speed and reduced power consumption, as well as reduced device latch-up. The buried
oxide in SOI wafers enables new and somewhat simpler manufacturing methods to be used for MEMS devices. Analog
Devices, a manufacturer of inertial devices for automotive and commercial uses has developed the SOIMEMS process,
which is based on SOI wafers [8]. The SOIMEMS process integrates microelectronics and MEMS devices on the same
wafer.
A dual SOI wafer process has been developed at Draper Laboratories to manufacture an accelerometer for high
accuracy applications. It is shown schematically in fig. 3. The nomenclature shown in fig. 2 is used in the following
description. The SOI wafer is ordered with a device Si layer several 10’s of µm thick. The SiO2 layer is 1-3 µm thick,
while the handle Si thickness must be large enough to prevent any bending of the wafer due to the compressive stress in
the SiO2 layer as well as provide a stable substrate for processing. Typically handle wafer thickness is greater than or
equal to 400 µm.
Device Si
• Si02
Ellhlil Handle Si
Fig. 2. Schematic diagram of an SOI wafer.
The dual SOI wafer process begins with the lower SOI wafer which will become the substrate in fig. 3A. Trenches are
etched through the device layer, stopping on the SiO2 layer in order to electrically isolate regions of the device layer.
This is depicted in fig. 3B. Some of the isolated regions of the device layer will carry current when the MEMS device is
functioning, similar to the metalization that is used in the dissolved wafer process. The current carrying regions in the
Proc. of SPIE Vol. 6113 611302-3
lower SOI wafer are referred to as Si runners. After the Si runners are defined, alignment marks are etched into the back
of the lower SOI wafer. They will be needed for the front to back wafer alignment which precedes wafer bond.
F
NNNN
G
\
H
Handle Si
Metallization
us———
nnt
N Device Si
• Oxide
Fig. 3. Schematic diagram of the dual SOI wafer process. Fig 3A and 3B show the lower SOI wafer. Fig. 3C shows the upper SOI
wafer. In Fig 3D, the lower and upper SOI wafer are bonded together. Figs. 3E-I show processing of the bonded SOI wafer stack.
The process continues with a mesa etch of the upper SOI wafer, which is depicted in fig. 3C. The mesa etch defines the
gap between the proof mass and the lower SOI or substrate wafer. Fig. 3D shows the upper and lower SOI wafers
bonded together. Both the upper and lower SOI wafers receive hydrophilic surface preparation before the wafer bond
step [9]. The Si-Si direct bond is initiated in a wafer bond tool at room temperature. The initial bond is strong enough to
transfer the wafers to a furnace for annealing. In the process step depicted in fig. 3D, a high temperature anneal is
Proc. of SPIE Vol. 6113 611302-4
performed while a wet oxide layer is grown on the outer surfaces of the bonded SOI wafers. The anneal results in a very
strong bond between the SOI wafers. After bonding the SOI wafers are inspected using an infrared camera viewing light
which passes through the wafers. This is a common method of assuring that there are no macroscopic areas that are not
bonded due to particle contamination [9].
The handle Si of the upper SOI wafer is removed in fig. 3E. This can be done by first removing the SiO2 layer on the
outside of the upper SOI wafer in a dry CF4/O2 etch, followed by etching with KOH, which is followed by a
Tetramethyl Ammonium Hydroxide (TMAH) etch. It is easier to grind away ½ to 2/3 of the upper SOI wafer handle Si
in a polishing tool, and then complete the Si removal in TMAH, which stops well on the SiO2 layer. Once the upper SOI
wafer SiO2 layer is exposed, it is removed in a short buffered HF wet etch, which also removes the SiO2 layer on the
back of the lower SOI wafer. This process step is depicted in fig. 3F.
Figure 3G shows the formation of ohmic contacts on the upper SOI wafer device Si, and the lower SOI wafer handle Si.
The ohmic contacts are the only metalization deposited onto the device, and the size of the metalization is determined
by die mounting, probing and wire bonding requirements. The device metalization is not needed to conduct current into
the device proof mass. This is accomplished by the Si runners. The ohmic contacts on the upper SOI wafer exist only to
provide a method of wire bonding to the Si runners. The ohmic contact deposition must be performed late in the process
flow because of the high temperature anneal used in the wafer bond step shown in fig. 3D, which would destroy
metalization if it was present on the device.
When the ohmic contact formation is complete, a deep anisotropic ICP etch is performed to define the proof mass,
motors, oscillators and bond pad regions [4]. This process step is shown in fig. 3H. At this point the devices are
complete, and the wafer must be cleaned. The final step in the process depicted in fig. 3I is to saw the wafer into
individual die. They are cleaned and checked for basic electrical and mechanical operation before packaging.
Discussion
A micromachining process for inertial devices which is based on SOI wafers has several advantages over one based on
the modified or classic dissolved wafer process. The undesirable effects of using EDP have been discussed. It is
extremely difficult, if not impossible to grow thick epitaxial SiGeB layers with no built in stress. In addition, when the
SiGeB epitaxial layer is greater than about 30 µm, the cost of a single SOI wafer with equal device layer thickness is
less than the cost of a wafer with SiGeB. The process illustrated in fig. 3 uses two SOI wafers, but it is also possible to
form a thick proof mass inertial device using a glass substrate and one SOI wafer [6].
There are other more subtle advantages to the SOI based process. The high concentration of Ge included in the SiGeB
material significantly increases the thermo-elastic damping of the device flexures [10]. Mechanical energy which should
be used to drive the motion of the device is diverted into heating and cooling the flexing device beams. This reduces the
mechanical Q of the inertial device. If this effect is severe, the inertial MEMS device will not operate (oscillate). Even if
the device functions, its performance is degraded. A high mechanical Q is desirable because many of the error term
formulas for inertial devices contain the mechanical Q term in the denominator [11, 12]. In ref. 6, a silicon oscillating
accelerometer [SOA] was manufactured with the modified dissolved wafer process and with the double SOI wafer
process shown in fig. 3. Although the accelerometer dimensions and design were identical, a 6-fold improvement in the
mechanical Q of the SOI based device was measured. Improved performance of inertial MEMS devices relies on
minimization of the error terms.
The double SOI wafer process shown in fig. 3 results in a MEMS inertial device which other than a thin layer of SiO2,
contains only Si. There is no difference between the thermal expansion coefficient of the proof mass, and the device
substrate. The performance of an all-Si inertial device over temperature will be better than a device made using the
dissolved wafer process in which the thermal expansion coefficient of the proof mass (Si) is different than that of the
substrate (glass). The double Si process contains metal only on bond pad and die mounting areas. This was intentionally
done to make an accelerometer for applications involving radiation exposure. A MEMS device made with a glass
Proc. of SPIE Vol. 6113 611302-5
substrate will have questionable performance under radiation because of radiation-induced expansion or compaction of
the glass [13].
Surface micromachining processes often use polysilicon layers to conduct current into the proof mass [14, 15]. The dual
SOI process in fig. 3 uses the device layer of the lower SOI wafer to accomplish the same thing. The double SOI
process combines the advantages of bulk and surface micromachining. Although the wafer cost of the process is more
expensive than most bulk wafer processes, the ultimate cost of processing the wafer is reduced by avoiding polysilicon
deposition. This allows a MEMS fab which is set up for bulk micromachining to reap some of the benefits of traditional
surface micromachining.
Conclusion
In the double SOI wafer process described in this paper, the thickness and resistivity of the SOI device silicon is chosen
for proper electrical function of the device, and ordered from the manufacturer. There are no inherent process
restrictions on the thickness or doping of the proof mass. The process does not require a high B concentration for use as
an EDP etch stop. Ge is not needed to compensate the strain in the Si lattice due to the high B concentration. The result
is that the inertial MEMS device made with the double SOI wafer process has a demonstrably higher mechanical Q than
an identical device made using the modified dissolved wafer process. This, in turn, reduces the devices errors, and
provides a clear path for even thicker inertial MEMS devices with large scale factors and a high signal to noise ratio.
The process described in this paper is neither inexpensive, nor is it simple to execute, but it offers a suitable means of
achieving tactical grade, radiation hard inertial MEMS device performance.
Acknowledgement
The authors gratefully acknowledge Draper Laboratory’s financial support and the dedicated work of the Draper MEMS
group. Thank you to Julie Merrell for her work on the figures.
Reference
1.
Y. Gianchandani and K. Najafi, "A Bulk Silicon Dissolved Wafer Process for Microelectromechanical
Devices," IEEE/ASME Journal of Microelectromechanical Systems, Vol. 1, No. 2, pp. 77 - 85, June 1992.
2. M. Weinberg, J. Bernstein, J. Borenstein, J. Campbell, J. Cousens, B. Cunningham, R. Fields, P. Greiff, B.
Hugh, L. Niles, and J. Sohn, “Micromachining Inertial Instruments,” in Micromachining and Microfabrication
Process Technology II, Austin, Tex., 1996, pp. 26-36.
3. M. Weinberg and A. Kourepenis, “Error Sources in In-Plane Silicon Tuning Fork MEMS Gyroscopes”,
submitted to J. MEMS.
4. S A McAuley, H Ashraf, L Atabo, A Chambers, S Hall, J Hopkins, G Nicholls, J. Phys, D: Appl. Phys., 34
(2001) 2769-2774.
5. J.T. Borenstein, N.D. Gerrish, R. White, M.T. Currie and E.A. Fitzgerald, “Silicon Germanium Epitaxy: A
New Material For MEMS”, Mat. Res. Soc. Symp., vol. 657, pp. 7.4.1, 2000.
6. W. D. Sawyer, M. S. Prince and G. J. Brown, “SOI Bonded Wafer Process For High Precision MEMS Inertial
Sensors”, J. Micromech. Microeng. 15 2005, 1588-1593.
7. Okmetic Newsletter 3 / 2005, Okmetic Inc., 301 Ridgemont Drive, Allen, TX 75002
8. M. W. Judy, “Evolution of Integrated Inertial MEMS Technology”, 2004 Solid -State Sensor, Actuator and
Microsystems Workshop, Hilton Head SC, June 2004, pp.27-32.
9. O.-Y. Tong and U. Goesele, “Semiconductor Wafer Bonding: Science and Technology”, J. Wiley & Sons,
New York, 1999.
10. A. Duwel, M. Weinstein, J. Gorman, J. Borenstein, P. Ward, “Quality Factors of MEMS Gyros and The Role
of Thermoelastic Damping”, Sens and Actuators A, vol 103, p. 70-75 (2003).
Proc. of SPIE Vol. 6113 611302-6
11. K. A. Gibbons, J. T. Borenstein, D. S. Nokes, M. S. Weinberg, and D. L. Trumper, “The Design, Fabrication,
and testing of a Micromechanical Silicon Oscillating Accelerometer”, AIAA Guidance, Navigation, and
Control Conference and Exhibit, 1998, p. 1296-1306.
12. R. Hopkins, J. Borenstein, B. Antowiak, P. Ward, R. Elliott, M. Weinberg, M. DePiero, and J. Miola “The
Silicon Oscillating Accelerometer: A MEMS Inertial Instrument for Strategic Missile Guidance”, AIAA
Missile Sciences Conference, 2000.
13. C. L. Allred, J. T. Borenstein, L. W. Hobbs, “Nuclear Radiation-Induced Dimensional Changes in MEMS
Glass Substrates”, Mat. Res. Soc. Symp., vol. 687, pp. 137-142, 2002.
14. T. J. Brosnihan, J. M. Bustillo, A. P. Pisano, and R. T. Howe, “Embedded Interconnect and Electrical Isolation
for High-Aspect-Ratio, SOI Inertial Instruments”, Proceedings of Transducers 97, 1997 International
Conference on Solid State Sensors and Actuators, Chicago, 1997, p. 637-640.
15. M. Keim, M. Illing, M. Schofthaller, R. Schellin, and D. Ullmann, “Advanced Microsystems For Automotive
Applications 2000”, Conference on Advanced Microsystems For Automotive Applications (4th), Springer,
Berlin, 2000, p. 219 – 232.
Proc. of SPIE Vol. 6113 611302-7