EE 4363
Week 10: March 23rd to April 3rd, 2009
Homework Assignment #5 and Related Reading
Reading: Chapter 4, Computer Organization and Design: sections 4.8, Appendix C
(found on the CD in your book); Chapter 5: section 5.1, 5.2, 5.3, 5.4, 5.5, 5.9, 5.10 from
the Patterson and Hennessey book.
Due Date: April 15th, 2009
[1] Figure 5.14 in your book shows 4 different 8-block cache configurations. Assume that
the cache block address access sequence is as follows:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
Show whether a particular cache access is a hit or a miss, and show the aggregate miss
rate for each of the four cache configurations: 4 cache configurations (direct-mapped, 1way set associative, 2-way set associative, 4-way set associative, 8-way set- associative).
Assume LRU replacement.
Answer:
Direct-mapped:
Block Address: 0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
Set #:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
H or M:
M,H,M,H,M,H, M, M, M, M, M,M, M,M,M,M,M,M,H,H,H,H
Hit rate: 7/22=0.32; Miss rate is 1.0-(Hit rate)=0.68
2-way Set Associative:
Block Address: 0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
Set #:
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 0, 1, 2, 3, 0
H or M:
M,H,M,H,M, H, M, M, M, M, M, M, M,M,M ,M,M,M,H,H,H,H
Hit rate: 7/22=0.32; Miss rate is 1.0-(Hit rate)=0.68
4-way Set Associative:
Block Address: 0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
Set #:
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0
H or M:
M,H,M,H,M, H, M, M, M, M, M, M, M,M,M,M,M,M,H,H,H,H
Hit rate: 7/22=0.32; Miss rate is 1.0-(Hit rate)=0.68
8-way (Fully) Associative:
Block Address: 0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
Set #:
0, 0, 8, 8, 16, 16, 24, 32, 40, 44, 0, 8, 16, 24, 1, 2, 3, 4, 1, 2, 3, 4
H or M:
M,H,M,H,M, H, M, M, M, M, H,H, H, H, M,M,M,M,H,H,H,H
Hit rate: 11/22=0.50; Miss rate is 1.0-(Hit rate)=0.50
[2] Describe the two types of locality in program instruction and data accesses that drives
the development of a memory hierarchy. Describe what a memory hierarchy is and what
primary electronic and related storage design principle drives its existence.
Answer: See solution to problem 1 in Exam 2.
[3] What are the typical access time ranges for SRAM, DRAM, and magnetic disk.
Answer: See solution to problem 1 in Exam 2.
[4] What are the two strategies for handling cache writes, and what are the tradeoffs
between them?
Answer: Write-back (in which data is written only to the higher level in the memory
hierarchy, not through to a lower level; data is written to lower levels only when a cache
block is being replaced) or write-through (in which data is written both to the higher and
to the lower level in the memory hierarchy). Write-back achieves better performance
because writes do not have to wait for the latency of completing the write to the second
level in the memory hierarchy and, in general, there will be less traffic to the lower level
of the memory hierarchy. On the other hand, write-back is more complex to implement.
[5] What are the four questions that can be applied between any two levels in a memory
hierarchy?
Answer: See section 5.5 and the summary at the bottom of page 522.
[6] What are the three different kinds of cache misses that can occur in a cache-based
memory system (hint: compulsory misses are one type). Describe each type of miss.
Answer: Compulsory (misses caused by first access to a block that has never been in
cache), capacity(misses caused when the cache cannot contain all the blocks needed
during execution of a program), and conflict(misses that occur in set-associative or
direct-mapped caches when multiple blocks compete for the same set).
[7] Exercises 5.3.1; 5.3.2; 5.3.3.
[8] Exercises 5.4.1, 5.4.2, 5.4.3.
[9] Describe a multi-level cache hierarchy and the potential for improvement it has
relative to a single level of cache.
Answer: See pg. 487-489. With a multi-level cache structure, the higher level focuses on
reducing hit times so that the cache can be accessed at high clock speeds used by the
pipelined processor; the second level cache focuses on low miss rates and less on access
time, so it has much higher capacity and typically higher associativity levels.