Q UA R T U S P R I M E D E S I G N S O F T WA R E Q UA R T U S P R I M E D E S I G N S O F T WA R E Fastest Path to Your Design Quartus® Prime software is number one in performance and productivity for FPGA, CPLD, and SoC designs, providing the fastest path to convert your concept into reality. Quartus Prime software can easily adapt to your specific needs in all phases of FPGA, CPLD, and SoC design in different platforms. Quartus Prime software provides everything you need to design with Altera devices: • Qsys system integration tool • TimeQuest timing analyzer • Transceiver Toolkit • External Memory Interface Toolkit • PowerPlay power analysis tools • DSP Builder Advanced Blockset • Altera SDK for OpenCLTM • ModelSim®-Altera Edition simulation software Altera Edition Quartus Prime Software Key Features Faster Compile Time PowerPlay Power Analyzer TimeQuest Timing Analyzer Qsys System-Level Integration Tool Industry-Leading Compile Time Quartus Prime software delivers superior synthesis and placement and routing, resulting in compilation time advantages for both Lite Edition and Standard Edition software. Additional compilation time reduction features include the following: – Multiprocessor support – Incremental compile – Advanced place-and-route algorithms 2 Q UA R T U S P R I M E D E S I G N S O F T WA R E Compile Time Comparison Quartus Prime Software Relative Compilation Time (Relative time based on fixed designs and fixed CPU) Relative Compile Time (Log Scale) 100% 50% 25% 13% 6% 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 Year Compare Full and Incremental Compile Incremental Compilation Top-Down Approach Full Compilation Create Design Partitions (A, B, C) Step 1 Quartus Prime Project (No Partitions) Quartus Prime Project Step 1 Modify Design (in Red) Re-compile Whole Project Step 2 Quartus Prime Project (No Partitions) AA B B C C Modify Design in Partition A Re-compile Only Partition A Quartus Prime Project Step 2 AA B B C C Incremental Compile • Compiles only the changes in a partition to reduce compile time by up to 70 percent • Preserves timing in unchanged partitions for performance preservation • Enables team-based designs 3 Q UA R T U S P R I M E D E S I G N S O F T WA R E TimeQuest Timing Analyzer TimeQuest Timing Analyzer GUI • Comprehensive Synopsys® Design Constraints (SDC) support • Second-generation, easy-to-use timing analyzer • Complete GUI environment and scripting support to create timing constraints and reports • Easy-to-use wizard to create SDC constraints PowerPlay Power Analyzer Flow Design Entry Constraints Speed Area Power Placement and Routing PowerPlay Power Analyzer Power-Optimized Design 4 • Push-button power optimization technology • Automated power optimization for an average 10 percent reduction in power consumption Synthesis Optimize Power PowerPlay Power Analyzer Q UA R T U S P R I M E D E S I G N S O F T WA R E Qsys System Integration Tool The Qsys system integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys is powered by a new FPGA-optimized network-on-a-chip (NoC) technology, delivering higher performance, improved design reuse, and faster verification. • High-performance Qsys interconnect based on the NoC architecture and automatic pipelining delivers up to 2X higher performance • Hierarchical design flow enables scalable designs, supports team-based design, and maximizes design reuse • Higher flexibility with support for mixing different industry-standard interfaces, such as the AMBA® AXI™, AMBA APBTM, AMBA AHBTM, and Avalon® interfaces • IP management capabilities enable designs and systems to appear as an IP for easier reuse • Faster board bring-up with a system-level debug approach using address-based transactions and System Console Qsys – Altera’s System Integration Tool HighPerformance Interconnect Hierarchy Industry-Standard Interface IP Management Real-Time System Debug 5 Q UA R T U S P R I M E D E S I G N S O F T WA R E The Quartus Prime software is number one in performance and productivity for FPGA, CPLD, and SoC designs, providing the fastest path to convert your concept into reality. The Quartus Prime software also supports many third-party tools for synthesis, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. Quartus Prime Software Design Flow Availability Quartus Prime Software Key Features Cyclone®, MAX®, and Arria® II device support Device Support Standard Edition Pro Edition (Free) ($) ($) 3 1 3 Arria and Stratix® device support 3 Arria 10 device support 3 3 3 3 3 Available for purchase 3 3 3 3 3 2 3 Multiprocessor support (faster compile time) IP Base Suite Design Entry Lite Edition Qsys Rapid Recompile 3 BluePrint Platform Designer Functional Simulation Synthesis ModelSim-Altera Starter Edition software 3 3 3 ModelSim-Altera Edition software 33 33 33 Spectra-Q™ Synthesis Fitter (Place and Route) Placement and Routing 3 3 3 Spectra-Q Hybrid Placer Spectra-Q Router Timing and Power Verification System Design Software 3 3 3 3 PowerPlay Power Analyzer 3 3 3 5 3 3 Transceiver toolkit 3 3 JNEye link analysis tool 3 3 3 Windows/Linux 64 bit support 3 3 3 Nios® II Embedded Design Suite 3 3 3 Available for purchase Available for purchase Available for purchase Available for purchase Available for purchase DSP Builder Altera SDK for OpenCL Notes: 1. The only Arria II FPGA supported is the EP2AGX45 device. 2. Available for Stratix V, Arria V, Cyclone V. 3. Requires an additional license. 4. Available for Arria 10, Stratix V, Arria V, Cyclone V 5. Available with TalkBack feature enabled. 6 3 4 3 SignalTap II Logic Analyzer Operating System (OS) Support 34 TimeQuest Static Timing Analyzer TM In-System Debug 3 Q UA R T U S P R I M E D E S I G N S O F T WA R E Third-Party Support Verification Performance and Timing Closure Methodology Design Flow Methodology Quartus Prime Design Software Features Summary BluePrint Platform Designer Platform designer tool that enables you to quickly create your I/O design using real time legality checks. Pin planner Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs. Qsys Automates system development by integrating IP functions and subsystems (collection of IP functions) using a hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture. Off-the-shelf IP cores Lets you construct your system-level design using IP cores from Altera and from Altera’s third-party IP partners. Synthesis Now with expanded language support for System Verilog and VHDL 2008. Scripting support Supports command-line operation and Tcl scripting, as well as graphical user interface (GUI) design. Rapid Recompile1 Maximizes your productivity by reducing your compilation time up to 4X (for a small design change after a full compile). Improves design timing preservation. Physical synthesis Uses post placement and routing delay knowledge of a design to improve performance. Design space explorer (DSE) Increases performance by automatically iterating through combinations of Quartus Prime software settings to find optimal results. Extensive cross-probing Provides support for cross-probing between verification tools and design source files. Optimization advisors Provides design-specific advice to improve performance, resource usage, and power consumption. Chip planner Reduces verification time while maintaining timing closure by enabling small, post placement and routing design changes to be implemented in minutes. TimeQuest timing analyzer Provides native Synopsys® Design Constraint (SDC) support and allows you to create, manage, and analyze complex timing constraints and quickly perform advanced timing verification. SignalTap II logic analyzer1 Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering capabilities available in an embedded logic analyzer. System Console Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to quickly create a GUI to help monitor and send data into your FPGA. PowerPlay technology Enables you to analyze and optimize both dynamic and static power consumption accurately. EDA partners Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit www.altera.com/eda-partners. Notes: 1. Available with Talkback feature enabled in Quartus Prime Lite Edition software. Getting Started Steps Step 1: Download the free Quartus Prime Lite Edition software www.altera.com/download Step 2: Get oriented with the Quartus Prime software interactive tutorial After installation, open the interactive tutorial on the welcome screen. Step 3: Sign up for training www.altera.com/training 7 M A I N C O R P O R AT E O F F I C E S Altera Corporation 101 Innovation Drive San Jose, CA 95134 USA Telephone: (408) 544 7000 www.altera.com Altera European Headquarters Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom Telephone: (44) 1 494 602 000 Altera Japan Ltd. Shinjuku i-Land Tower 32F 6-5-1, Nishi Shinjuku Shinjuku-ku, Tokyo 163-1332 Japan Telephone: (81) 3 3340 9480 www.altera.co.jp Altera International Ltd. Unit 11- 18, 9/F Millennium City 1, Tower 1 388 Kwun Tong Road Kwun Tong Kowloon, Hong Kong Telephone: (852) 2945 7000 www.altera.com.cn Altera Corporation Technology Center Plot 6, Bayan Lepas Technoplex Medan Bayan Lepas 11900 Bayan Lepas Penang, Malaysia Telephone: 604 636 6100 Altera European Trading Company Ltd. Building 2100 Cork Airport Business Park, Cork, Republic of Ireland Telephone: +353 21 454 7500 ©2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal. November 2015 GB-1001-3.3