CoDeveloper for LabVIEW FPGA Platform Support Package

Help Contents 1

1 Help Contents

CoDeveloper

ä

from

Impulse Accelerated Technologies

ä

LabVIEW FPGA

ä

Platform Support Package

CONTENTS

Before You Begin (Read This First)

LabVIEW FPGA Platform Support Package Overview

Quick Start Tutorial

1.1

LabVIEW FPGA Platform Support Package Overview

© 2003-2015 Impulse Accelerated Technologies

2 CoDeveloper for LabVIEW FPGA Platform Support Package

Welcome to CoDeveloper

ä

for LabVIEW FPGA

ä

Welcome to CoDeveloper: advanced software technologies enabling high-performance applications on programmable hardware platforms. CoDeveloper will change the way you create FPGA-accelerated applications for LabVIEW FPGA platform targets.

The complete CoDeveloper environment consists of a set of libraries allowing Impulse C applications to be executed in a standard C/C++ desktop compiler (for simulation and debugging purposes) as well as cross-compiler and translation tools allowing mixed hardware/software applications to be implemented on selected programmable hardware platforms including National Instruments

CompactRIO ä , R Series ä and Compact Vision System ä .

CoDeveloper is designed for use with leading tools for embedded software and programmable hardware development, including FPGA synthesis tools, desktop (Windows and Linux) C/C++ development tools and embedded compiler and debugger tools. The LabVIEW FPGA Platform

Support Package (described in this document) extends the power of CoDeveloper by providing automated software/hardware generation for National Instruments FPGA-based programmable platforms.

Getting Started

To get started using CoDeveloper for LabVIEW FPGA platforms, you should load one of the

tutorial sample projects

included in the Examples\LabVIEW subdirectory of your CoDeveloper installation. These examples will help you understand how to create and manage an Impulse C project in conjunction with the software tools provided by Xilinx and National Instruments.

To load a sample project, select Open Project from the Application Manager File menu, and navigate to the Examples\LabVIEW subdirectory of the Impulse C installation directory. Select one of the sample projects and open the project file (identified by a .icProj file name extension) associated with that project. Be sure to review any Readme files included with the sample project.

Before starting with a CoDeveloper example project, be sure you have reviewed the information in the

Read This First

section of this document. Also, please take time to familiarize yourself with the Xilinx and National Instruments tools.

See Also

Help Contents

Read This First



Help Contents 3

1.1.1

Read This First

Release Notes

This is release 2.20 of CoDeveloper for LabVIEW FPGA Platform Support Package , from Impulse

Accelerated Technologies.

SYSTEM REQUIREMENTS

The following is required to make full use of the LabVIEW FPGA Platform Support Package:

· PC with 1GHz or better clock speed

· 512MB RAM

· Windows 2000 or Windows XP

The following additional hardware and software is required:

· National Instruments R Series, CompactRIO, Compact Vision System or equivalent hardware platform

· National Instruments LabVIEW FPGA, Version 8.0 or later

· Xilinx ISE development tools, version 8.1 or newer (included with LabVIEW FPGA)

PREREQUISITES

The information and tutorials included in this Platform Support Package assume that you have previously installed the National Instruments LabVIEW FPGA software, and have familiarized yourself with its operation. If you have not done so, we strongly suggest that you begin by going through one or more of the simple design tutorials included with the LabVIEW tools. In particular, you should be familiar with concept of host to FPGA communication using your selected FPGA hardware platform.

The tutorials in this Platform Support Package also assume that you have read and understand the introductory sections of the CoDeveloper User's Guide, which is installed with your CoDeveloper product and can be accessed from the CoDeveloper Help menu. In particular, you should take the time to go through the tutorials provided with CoDeveloper so you have a good understanding of the frontend design flow including both desktop simulation and hardware compilation.

Note: the tutorials provided in this document are intended for illustrative purposes only. The steps required to use CoDeveloper with a specific FPGA and LabVIEW FPGA platform combination may differ somewhat from the steps described in these tutorials. Please take the time to familiarize yourself with your selected platform and with the National Instruments and Xilinx tools prior to beginning.

GETTING STARTED

A sample project targeting the R Series platform is included in this document. To work with this example:

1.

Start the Impulse Application Manager by selecting Start -> Impulse Accelerated Technologies ->

CoDeveloper -> Application Manager.

2.

Select the Sample Projects tab in the CoDeveloper Start Page.

3.

Navigate to the Simple Filter sample project in the LabVIEW FPGA section of the Sample Projects list.

Once you have opened the sample project, you can review the Impulse C source code, launch a desktop simulation or invoke the Impulse C hardware generator to process the sample application and generate output files compatible with LabVIEW FPGA. These steps are fully described in the Quick



Start Tutorial included in this document.

See Also


1.1.2

Contents

CoDeveloper

ä

from

Impulse Accelerated Technologies

ä

LabVIEW FPGA

ä

Platform Support Package

CONTENTS

Before You Begin (Read This First)

LabVIEW FPGA Platform Support Package Overview



Help Contents 5

1.2

Quick Start Tutorials

Overview

Impulse C is a compiler and a set of library functions that enable and simplify the creation of FPGAaccelerated software applications. As such, Impulse C can be used to generate hardware modules that are directly connected to an HDL Interface Node in the LabVIEW FPGA graphical programming environment. By combining C programming and the C-to-FPGA capabilities of Impulse C with the powerful block diagram-oriented features of LabVIEW FPGA, you have the power to create highly accelerated, custom hardware solutions for data acquisition, control and analysis.

The Impulse C streaming programming model is an excellent fit in the LabVIEW FPGA environment.

Like LabVIEW itself, the Impulse C programming model emphasizes the use of dataflow objects

(called processes ) along with well-defined data communication channels (called streams ) for moduleto-module communication. These stream interfaces map well to the dataflow communication methods provided in LabVIEW FPGA, and can support both hardware-to-hardware and hardware-to-software communications.

There are many possible ways to use Impulse C in the LabVIEW FPGA environment. For the most efficient host/FPGA communications, however, the use of DMA for data communications is highly recommended. The following tutorial therefore focuses on the use of DMA FIFO interfaces to create a complete application that communicates data from the host to the FPGA platform, processes that data using Impulse C generated hardware, and communicates results from the FPGA back to the host. The techniques described in this example can be applied to a wide variety of C-language algorithms. The tutorial will lead you step-by-step through the compilation, execution and RTL generation of this application using the Impulse, Xilinx and National Instruments tools.



See Also

Tutorial 1: A Simple FPGA-based Filter

1.2.1

Tutorial 1: A Simple FPGA-based Filter

Overview

This tutorial will demonstrate how to generate low-level hardware and related interfaces in the form of

VHDL descriptions and corresponding netlists compatible with the Xilinx and National Instruments software tools.

The steps described assume that you are using Xilinx ISE version 8.1, and LabVIEW FPGA Version

8.0. Other versions may require changes to some of the steps presented.

The purpose of this tutorial is to take you through the entire process of generating hardware and related interfaces, and importing the relevant files to the LabVIEW FPGA environment. As part of this description, the tutorial will also demonstrate how to use the Xilinx ISE tools.

This tutorial will require approximately 45 minutes to complete, including software run times.


Help Contents 7

Steps

Loading the Sample LabVIEW Project

Loading the Impulse C Project

Building the Application for the Target Platform

Using the Xilinx ISE Tools

Importing the Generated Hardware into LabVIEW

Running the Application

Understanding the Stream Interface

1.2.1.1

Loading the Sample LabVIEW Project

Simple Filter Tutorial for LabVIEW FPGA, Step 1

To begin, start LabVIEW and select Open Project from the File menu. Navigate to the

Impulse/CoDeveloper2/Examples/LabVIEW/SimpleFilter directory and open the Impulse C Simple

Filter sample project.

Opening the project will result in the display of a window similar to the following:

The provided sample project includes two VIs, one titled DMA Buffered Impulse C Filter (on FPGA

Target 2), and one titled DMA Buffered Host Application. The project also includes two DMA FIFOs that are used for host-to-FPGA and FPGA-to-host communications.

Double-click on the DMA Buffered Host Application VI to see the host application. The front panel appears as shown below:



The sample application includes two waveform displays, the first of which represents an original, unfiltered waveform. A control knob is provided that allows the frequency of the sample waveform (a sine wave) to be adjusted while the VI is running. Two data entry fields in the upper left allow the amplitude and offset of the waveform to be adjusted.

The second waveform display represents the filtered waveform that will be returned from the executing

FPGA VI.

Now open the block diagram associated with this front panel (either by using the Window menu or by pressing CTRL-E). The block diagram will appear as follows:

This block diagram represents the functions to be executed on the host side of the application. In particular, notice that there are two DMA FIFO blocks, each of which represents one dataflow channel for host/FPGA communication. Notice also that a sine wave generator is used to provide the sample


Help Contents 9 waveform. This sine wave generator can be replaced with actual data acquisition as required.

To view the FPGA VI, double-click on the left-most block titled FPGA Target 2. The DMA Buffered

Impulse C Filter VI will open, as shown below:

Use the CTRL-E key to open the block diagram for this VI, as shown below:



The block diagram for the FPGA VI includes a while loop, within which the DMA FIFO operations for reading from and writing data to the host are provided. Notice that there is an HDL Interface Node in the center of the diagram that accepts data from the first DMA FIFO, and sends results to the second

DMA FIFO, using 32-bit unsigned integer wires labeled S1 and S2. This HDL Interface Node is a filter that has been written and processed using Impulse C. The steps that follow will show you how the hardware for this HDL Interface Node was created and imported into LabVIEW FPGA.

See Also

Loading the Impulse C Project

1.2.1.2

Loading the Impulse C Project


The filter that we have created for demonstration purposes accepts the incoming data as buffered stream, performs a simple amplitude clipping function, and passed the resulting modified waveform values to its outputs on a second buffered stream. The input and output streams are connected via appropriate handshake logic to the HDL Interface Node, which is in turn connected to the FPGA VI diagram.

To view the C source code for this example, open the sample project in the Impulse CoDeveloper environment. Start the Impulse CoDeveloper application, select Open Project from the File menu, then navigate to the Impulse/CoDeveloper2/Examples/LabVIEW/SimpleFilter directory. Open the

FilterTest project file:


Help Contents 11

Files included in the FilterTest project include:

Source files FilterTest_hw.c, FilterTest_sw.c, and FilterTest.h

- These source files represent the complete application, including the main() function, consumer and producer software processes (for desktop simulation) and a single hardware process representing the filter.

Note: for information about desktop simulation and other features of the CoDeveloper tools, refer to the

CoDeveloper User Guide.

Double-click on the FilterTest_hw.c

source file to view the source code for the filter:

Scroll down in the source file to find the C subroutine titled "MyFilter" with the following declaration:


12 CoDeveloper for LabVIEW FPGA Platform Support Package void MyFilter (co_stream S1, co_stream S2)

This subroutine (or process , using the Impulse C terminology) represents the filter. The streams named S1 and S2 map directly to S1 and S2 seen previously on the FPGA VI block diagram, as input and output parameters of the HDL Node. Scroll down a bit more in the source code (as shown above) and examine the inner code loop of the filter. As mentioned previously, this filter is quite simple. You can, however, modify this inner loop to perform a wide variety of filter operations. Impulse C examples provided with your CoDeveloper installation demonstrate many different types of stream processing.

In the next step, you will learn how to process this C code to create a VHDL netlist representation compatible with the Xilinx FPGA synthesis tools, and compatible with LabVIEW FPGA.

See Also

Building the Application for the Target Platform

1.2.1.3

Building the Application for the Target Platform


Specifying the Platform Support Package

The next step, prior to compiling and generating the HDL and related output files, is to select a platform target. Which target you select has a number of implications, including:

· The output file format (e.g. VHDL, Verilog or other intermediate language)

· The primitive components that will be referenced in the output (e.g. memory components or buffer types)

· The types of optimizations performed during compilation

· The software library components that will be generated

· The type of I/O to be generated for the input and output streams

To specify a platform target, open the Generate Options dialog as shown below:



Specify NI LabVIEW (VHDL) as shown. Also specify "hw" and "sw" for the hardware and software directories as shown, and specify "Use std_logic_types for VHDL interfaces". Do not select any other options. In particular, do not select the "Generate dual clocks", "Active-low reset" or "Do not include co_ports in bus interface" options. Click OK to save the options and exit the dialog.

Note: you must specify the "Use std_logic_types" option for LabVIEW FPGA compatibility.

Generate HDL for the Hardware Process

To generate hardware in the form of HDL files, and to generate the associated software interfaces and library files, select Generate HDL from the Project menu, or click on the Generate HDL button. A series of processing steps will run in a command window as shown below:



When processing is complete you will have a number of resulting files created in the hw subdirectory of your project directory. Take a moment to review these generated files. They include:

· Generated VHDL source files ( FilterTest_comp.vhd

and FilterTest_top.vhd

) representing the hardware process and the generated hardware stream interface.

· An additional VHDL source file ( hdlnode_FilterTest_arch.vhd

) representing the Impulse stream to LabVIEW interface.

· A text file ( hdlnode_FilterTest_arch.txt

) describing the required HDL Node component instantiation statements.

· A lib subdirectory containing required VHDL library elements.

In the next step, we will describe how to import these generated files into the Xilinx ISE tools to create an .NGC format file for use within LabVIEW FPGA.

See Also

Using the Xilinx ISE Tools

1.2.1.4

Using the Xilinx ISE Tools


As you saw in the previous step, CoDeveloper creates a number of hardware output files that must be combined, in a process called synthesis , to create FPGA-compatible hardware files.

Note: you must have Xilinx ISE version 8.1 installed in order to proceed with this and subsequent steps. This software is installed with your LabVIEW FPGA software, in the Xilinx subdirectory of your

LabVIEW software installation.

First, create a subdirectory within your project directory that will contain the new Xilinx project files. For this tutorial we have chosen the directory name "ISE_Project".

Creating a New Xilinx ISE Project

Now we'll move into the Xilinx tool environment. Begin by launching Xilinx ISE software and creating a new project. Create the new project as shown below:



Click Next, then specify the FPGA device and family appropriate for your selected National Instruments platform.



For the R Series PCI-7811R board used for this example, the correct device is a Virtex2 xc2v1000, package fg456. Other products may require other FPGA family and package selections. Refer to your hardware documentation for details.

Click Next. The wizard will ask you if you want to add new source files to your project. This is a convenient place to add a required library (the "impulse" library) to the project. To do this, select the

Add New Source button. In the dialog that appears, select VHDL Library from the list of source files types, then enter "impulse" into the File Name field as shown below:



Click Next. You will now have one source in your new project, as shown below:



Click Next to view a summary of your new project:

Click Finish to exit the wizard and create the new project.

The Library View of your newly-created project should look similar to the following:



Notice that there is a "work" library, as well as an "impulse" library. Now you will import the actual

VHDL source files for the project, starting with the files representing the Impulse library. Right-click on the impulse library entry and select the "Add Files..." menu item. Select the following files from the hw/lib subdirectory of your Impulse C project directory (you will have to navigate to these directories, which are found under the directory containing your Impulse C project):



Highlight all the files shown, then click Open. Your ISE project should now appear as follows:



Note: it is critical that the library files shown above are located within the impulse library.

Now select the work directory and right-click to again select the "Add Files..." menu item. Select the following three files:



Click Open to add these files to the work library. The ISE program will ask you what kind of source file type each of these files is (a design file or a test bench). For all files, specify "VHDL Design File" as shown:

The Impulse-generated project files have now been imported into ISE.



Now, select the Module View tab to display the project hierarchy. Find the "hdlnode_filtertest_archimplementation" entry in the list and select it with your mouse as shown below:



This entry represents the top-most module in the project. In the Process View window, find the

Synthesize-XST entry and highlight it as shown above.

Before running synthesis, there is one important property that must be set for the selected module. To set this property, right-click on the Synthesize-XST line and select Properties... from the menu that appears.



In the Process Properties dialog, choose the Xilinx Specific Options tab, and un-check the Add I/O

Buffers option. This default option assumes that the I/O lines of the top-level module are to be attached to pins on the FPGA. Because we will be combining our generated hardware with higher-level hardware generated by LabVIEW FPGA, we must turn off this option.

Note: if the Add I/O Buffers option is selected, there will be errors generated during LabVIEW FPGA synthesis.

Click OK to exit the Properties dialog.

Now you are ready to synthesize the logic of the filter. To do this, simply double-click on the

Synthesize-XST process. The synthesis process will begin, and will require a few minutes to complete.

When finished, a transcript similar to the following will be displayed:

Verify that the Maximim Frequency shown meets the requirements for your target FPGA platform (for the R Series boards, the frequency must be 40MHz or higher), and check to make sure there are no synthesis errors. (Synthesis warnings are normal.)

You have now generated the required hardware, in the form of a Xilinx .NGC file.

The next step will demonstrate how to import the generated .NGC file into LabVIEW FPGA.



See Also

Importing the Generated Hardware into LabVIEW

1.2.1.5

Importing the Generated Hardware into LabVIEW


You will now return to the LabVIEW FPGA application. Open the FPGA VI block diagram as shown:

Double-click on the HDL Node to invoke the Configure HDL Node dialog:



Notice that the 32-bit S1 and S2 parameters have already been created. S1 is specified with direction

"in", and S2 is given a direction of "out".

Now select the Code tab:



This tab contains the HDL statements specifying the behavior of the HDL Interface Node. Notice that the source code is entered in four different fields. For Impulse C integration, you should leave the

Libraries and entity name fields with their default values as shown. The contents of the two larger fields representing the VHDL architecture can be copied directly from the text file that was generated by

Impulse C during hardware generation. In this case the text file is named hdlnode_FilterTest_arch.txt

, and includes the following statements:

-- Insert the following code into the Code dialog of your

-- LabVIEW FPGA HDL Interface Node: architecture implementation of hdlnode is component hdlnode_FilterTest_arch is

generic (

ClockFrequency : Integer := 40000000

);

port (

clk : in std_logic;

reset : in std_logic;

enable_in : in std_logic;



enable_out : out std_logic;

enable_clr : in std_logic;

S1 : in std_logic_vector(31 downto 0);

S2 : out std_logic_vector(31 downto 0)

); end component hdlnode_FilterTest_arch; begin

FilterTest_arch_sl_0: hdlnode_FilterTest_arch_sl

port map (

clk,

reset,

enable_in,

enable_out,

enable_clr,

S1,

S2); end implementation;

These statements are provided for your convencience, and as a guideline for creating the required

Impulse to LabVIEW FPGA integration. Notice that there is no actual logic specified in this file; all required handshake signals and other logic are generate by the Impulse compiler and are located lower in the hardware design hierarchy.

Now select the External Files tab:



This tab is where you specify the location and name of the .NGC format file generated by the ISE tools in the previous tutorial step. If you have generated your .NGC file in a different directory than the one shown, you should first Remove the existing file, then choose "Add File..." to re-import the .NGC netlist file.

Click OK to exit the Configure HDL Interface Node dialog.

You have now imported all necessary hardware files and and HDL source code. In the

next step

you will see how to run the application on the R Series hardware.

See Also

Running the Application



1.2.1.6

Running the Application


At this point, if you have followed the tutorial steps carefully you have:

· Generated VHDL hardware files from the CoDeveloper environment.

· Created a new Xilinx ISE project and created a LabVIEW-compatible FPGA netlist (.NGC file).

· Imported your generated files to LabVIEW FPGA via the HDL Interface Node.

You are now ready to generate the bitmap and download the complete application to the target

LabVIEW FPGA platform. This process is not complicated (at least in terms of your actions at the keyboard) but can be quite time consuming due to the large amount of processing that is required for

FPGA synthesis and place-and-route.

First, from within the FPGA VI block diagram, save the diagram and click the Run button to verify the diagram and invoke the FPGA synthesis process. The Compile Server will display a series of messages as the application is compiled:

Note: this process may require 15 minutes or more to complete, depending on the speed and memory of your development system.

When the bitstream has been generated, a dialog similar to the following will appear:



Click OK to exit the dialog. The FPGA VI will now be running, but without the host. Stop the FPGA VI execution, then open the Host VI front panel:

Click the Run button, and observe the application running. Notice that the modified waveform exhibits clipping behavior, as expected:



Congratulations! You have successfully compiled a complete, customized host/FPGA application on the target FPGA platform, without the need to write any low-level VHDL code.

Although this sample clipping filter was somewhat trivial, the process for substantially larger, more complex applications is essentially the same. You can follow these steps and use this sample project as a starting point when creating and compiling your own Impulse C applications.

What's Next?

In the next tutorial section, you'll learn more about the LabVIEW FPGA interface by examining the automatically generated wrapper code used in this example.

See Also

Understanding the Stream Interface

1.2.1.7

Understanding the Stream Interface


Overview

This optional tutorial section describes in detail the hardware interface generated by the Impulse C compiler. This hardware interface provides translation and synchronization of signals produced in the

LabVIEW FPGA environment (in particular, the enable chain) with corresponding signals created by the Impulse C compiler for streaming applications.

The Impulse / LabVIEW Wrapper Code



Integration between a LabVIEW FPGA Virtual Instrument (VI) and an Impulse C generated hardware module is provided through the creation of a "wrapper", which is an automatically-generated VHDL file.

The wrapper architecture is summarized below:

In this diagram, the top-level block represents the HDL code that is entered in the HDL Interface Node

Code, in the Code section of the configuration dialog. The hdlnode_filter block represents the automatically generated wrapper code that is created by the Impulse C compiler. The filter_top and filter_comp blocks represent the VHDL code that is normally generated by the Impulse C compiler, including the standard Impulse C stream interfaces. (These stream interfaces are described in detail in the Impulse C User's Guide.)

While it is generally not necessary to examine or modify the generated code, it is useful to have a basic understanding of how the wrapper is architected, and how the wrapper facilitates communication between LabVIEW FPGA and the Impulse C generated hardware module. The wrapper code provides the handshake mechanism between a LabVIEW FPGA VI and the automatically generated VHDL code found in filter_top and filter_comp . This code is generated in VHDL and is instantiated from within the

Code tab of the HDL Interface Node.

Why is this wrapper needed? The LabVIEW environment and all componts found within a LabVIEW diagram are synchronized using what is called the "enable chain". This enable chain is a set of signals used to control the dataflow between the blocks and nodes of a LabVIEW virtual instrument (VI). The

HDL Interface Node uses an enable chain to make sure that it receives all of its inputs (that all input data is valid) before executing the HDL code found within or referenced by its Code Tab. Any hardware executing within the HDL Interface Node must wait for this enable chain, and must generated appropriate top-level enable chain signals to indicate that the hardware outputs are valid.

Impulse C processes such as the filter being described here also include a synchronization mechanism. Unlike the LabVIEW enable chain, however, the Impulse C method makes use of distinct synchronization signals for each input and output stream. Each Impulse C generated stream interface has its own set of signals that form the complete interface for a single stream of an Impulse C process.



Without the wrapper code, neither the HDL Interface Node nor the Impulse C generated hardware would know when to send data, or when data to be received is valid.

Wrapper Code Structure

If you wish, you can create your own wrapper code and enter this code into the Code tab of the HDL

Interface Node, then use the "Xilinx Generic" output option in CoDeveloper when generating hardware.

More typically, however, you will use the wrapper code that is generated for you using the "NI LabVIEW

FPGA" output option. Whichever method you use, the following commented code (automatically generated for the filter example) forms a good foundation for understanding the basic structure of any

LabVIEW FPGA to Impulse C wrapper.

-- LabVIEW FPGA HDL Interface Node Generated by CoDeveloper

-- Copyright (c) 2006 Impulse Accelerated Technologies, Inc.

--

-- This file represents the top of the NGC file hierarchy, and

-- must be synthesized without I/O buffer insertion before

-- being added to the LabVIEW FPGA HDL Interface Node.

--

-- See the file hw/hdlnode_FilterTest_arch_readme.txt for sample

-- HDL Interface Node HDL code.

-library ieee; use ieee.std_logic_1164.all; entity hdlnode_FilterTest_arch is

generic (


);

port (

clk : in std_logic;







); end hdlnode_FilterTest_arch; architecture implementation of hdlnode_FilterTest_arch is

-- Declare ImpulseC component. Note that FilterTest_arch_sl

-- is the top-level entity generated by the Impulse C

-- compiler. This component is found in the xxxx_top.vhd

-- file.

component FilterTest_arch_sl is

port (


sclk : in std_logic;

clk : in std_logic;

S1_en : in std_logic;

S1_eos : in std_logic;

S1_data : in std_logic_vector (31 downto 0);

S1_rdy : out std_logic;

S2_en : in std_logic;

S2_data : out std_logic_vector (31 downto 0);

S2_eos : out std_logic;

S2_rdy : out std_logic

);

end component;

signal S1_rdy : std_logic;



signal S1_en : std_logic;

signal S1_eos : std_logic;

signal S1_idata : std_logic_vector (31 downto 0);

signal S2_rdy : std_logic;

signal S2_en : std_logic;

signal S2_eos : std_logic;

signal S2_idata : std_logic_vector (31 downto 0);

-- The following signals used to create a rising edge pulse

-- based on enable_in

signal nd, prev_enable_in: std_logic; begin

FilterTest_arch_sl_0: FilterTest_arch_sl

port map (

reset,

clk, -- Note that both clock inputs are

clk, -- tied to the same LabVIEW FPGA clock

S1_en,

S1_eos,

S1_idata,

S1_rdy,

S2_en,

S2_idata,

S2_eos,

S2_rdy);

-- Create a rising edge pulse based on enable_in, indicating new data

delay_enable_in:

process(clk)

begin

if rising_edge(clk) then

prev_enable_in <= enable_in;

end if;

end process delay_enable_in;

nd <= enable_in and not(prev_enable_in);

-- This is the enable chain controller. Output data must be valid

-- when enable_out asserts, and must remain valid until enable_in

-- deasserts or enable_clr asserts. Enable_out must only assert

-- in response to enable_in asserting.

enable_chain_controller:

process(clk, reset)

begin

if reset = '1' then

enable_out <= '0';

elsif rising_edge(clk) then

if enable_in = '1' then

enable_out <= '1';

else

enable_out <= '0';

end if;

end if;

end process enable_chain_controller;

-- The following is the controller for the S1 input stream

S1_enable_controller:

process (clk, reset)

begin

if reset = '1' then



S1_idata <= (others => '0');

S1_en <= '0';


if enable_clr = '1' then


S1_en <= '0';

else

if (nd = '1' and S1_rdy = '1') then

S1_idata <= S1;

S1_en <= '1';

else


S1_en <= '0';

end if;

end if;

end if;

end process S1_enable_controller;

-- The following is the controller for the S2 output stream

S2_enable_controller:

process (clk, reset)

begin

if reset = '1' then

S2 <= (others => '0');

S2_en <= '0';


if enable_clr = '1' then

S2_en <= '0';

else

S2 <= S2_idata;

if S2_rdy = '1' then

S2_en <= '1';

else

S2_en <= '0';

end if;

end if;

end if;

end process S2_enable_controller; end;

The above wrapper code can be instantiated using VHDL statements entered within the Code tab of the HDL Interface Node. For your convenience, the Impulse C automatically generates the required

HDL Interface Node code in a text file, as described in previous tutorial steps. The following is all the code required by the HDL Interface Node for this example:

-- Insert the following code into the Code dialog of your

-- LabVIEW FPGA HDL Interface Node: architecture implementation of hdlnode is component hdlnode_FilterTest_arch is

generic (


);

port (

clk : in std_logic;









); end component hdlnode_FilterTest_arch; begin

FilterTest_arch_0: hdlnode_FilterTest_arch

port map (

clk,

reset,

enable_in,

enable_out,

enable_clr,

S1,

S2); end implementation;

Other Information

For more information on the FPGA VI and its enable chain, see the National Instruments article titled

Importing HDL Code into FPGA VIs Using the HDL Interface Node .

For more information on the stream I/O signals of an Impulse C process, see the CoDeveloper User

Guide Tutorial 4 entitled DES Encryption Part 2 .


CoDeveloper for LabVIEW FPGA Platform Support Package

1 Help Contents

CoDeveloper

from

Impulse Accelerated Technologies

LabVIEW FPGA

Platform Support Package

1.1

LabVIEW FPGA Platform Support Package Overview

Welcome to CoDeveloper

for LabVIEW FPGA

Getting Started

See Also

1.1.1

Read This First

Release Notes

SYSTEM REQUIREMENTS

PREREQUISITES

GETTING STARTED

See Also

1.1.2

Contents

CoDeveloper

from

Impulse Accelerated Technologies

LabVIEW FPGA

Platform Support Package

1.2

Quick Start Tutorials

Overview

See Also

1.2.1

Tutorial 1: A Simple FPGA-based Filter

Overview

Steps

Simple Filter Tutorial for LabVIEW FPGA, Step 1

See Also

Simple Filter Tutorial for LabVIEW FPGA, Step 2

See Also

Simple Filter Tutorial for LabVIEW FPGA, Step 3

Specifying the Platform Support Package

Generate HDL for the Hardware Process

See Also

Simple Filter Tutorial for LabVIEW FPGA, Step 4

Creating a New Xilinx ISE Project

See Also

Simple Filter Tutorial for LabVIEW FPGA, Step 5

See Also

Simple Filter Tutorial for LabVIEW FPGA, Step 6

What's Next?

See Also

Simple Filter Tutorial for LabVIEW FPGA, Step 6

Overview

The Impulse / LabVIEW Wrapper Code

Wrapper Code Structure

Other Information

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