The World of Time-Interleaved ADCs
- from theory to design -
Manar El-Chammas
Texas Instruments, Inc.
June 17, 2012
Who am I?
Received B.E. from A.U.B. in 2004
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Who am I?
Received B.E. from A.U.B. in 2004
Received Ph.D. from Stanford University in 2010
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Thesis: “Background calibration of timing-skew in time-interleaved ADCs”
Ph.D. Advisor: Prof. Boris Murmann
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Who am I?
Received B.E. from A.U.B. in 2004
Received Ph.D. from Stanford University in 2010
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Thesis: “Background calibration of timing-skew in time-interleaved ADCs”
Ph.D. Advisor: Prof. Boris Murmann
Research interests: Integrated circuits, background calibration, low
power design
Joined Texas Instruments, Inc. (Dallas, TX) in 2010
I
Design high-speed data converters
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The purpose of this tutorial is ...
... to help you understand the theory and operation of
time-interleaved ADCs and how to design them
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The purpose of this tutorial is ...
... to help you understand the theory and operation of
time-interleaved ADCs and how to design them
At the end of this tutorial, you (hopefully!) will have a toolbox to
analyze time-interleaved ADCs with
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The purpose of this tutorial is ...
... to help you understand the theory and operation of
time-interleaved ADCs and how to design them
At the end of this tutorial, you (hopefully!) will have a toolbox to
analyze time-interleaved ADCs with and a starting point from which
to design one
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The purpose of this tutorial is ...
... to help you understand the theory and operation of
time-interleaved ADCs and how to design them
At the end of this tutorial, you (hopefully!) will have a toolbox to
analyze time-interleaved ADCs with and a starting point from which
to design one
Stop me whenever you have questions
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A broad-stroke outline
Data converters 101
The time-interleaved ADC
Analyzing time-varying errors
Design of time-interleaved ADCs
Calibration
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Part I
Data Converters 101
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I think there is a world market for maybe five computers
- Attributed (probably falsely) to T.J. Watson, 1943
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Introduction
Data converters form important part of signal chain
[Image from B. Murmann notes]
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Data converter applications
Consumer electronics
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Video and audio
Digital cameras
Automotive systems
Communication systems
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Wireless infrastructure
Ethernet
Computing and control
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Storage media
Feedback systems
Instrumentation
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Medical equipment
Oscilloscopes
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Data converter applications
There are more data converters than people in this room
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Data converter applications
There are more data converters than people in this room
No. data converters
% with time
No. people
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Examples
Agilent oscilloscope (ISSCC 2003)
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Examples
1 kS/s ADC for medical implants (ESSCIRC 2010)
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Examples
TI ADC used in wireless infrastructure (ISSCC 2010)
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Reference books
Principles of Data Conversion System Design, Behzad Razavi
Data Converters, F. Maloberti
CMOS Data Converters for Communications, Mikael Gustavsson et al.
Understanding Delta-Sigma Data Converters, Richard Schreier et al.
Data Conversion Handbook, Analog Devices Inc.
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What exactly is an ADC?
IN
ADC
OUT
Definition
An ADC (analog-to-digital converter) converts a continuous-time signal
to a discrete-time representation
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What exactly is an ADC? (1955)
[Blecher 1955]
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Analog-to-digital conversion consists of ...
Sampling: Discretizing in time
Quantization: Discretizing in amplitude
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Sampling and quantization
(Example of sampled and quantized signal)
[Murmann notes]
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Sampling and quantization
Most common approach is to discretize uniformly in both time and
amplitude
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Sampling and quantization
Most common approach is to discretize uniformly in both time and
amplitude
These two concepts alone can fill an entire semester ...
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Sampling and quantization
Most common approach is to discretize uniformly in both time and
amplitude
These two concepts alone can fill an entire semester ...
For more on these, see reference books
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Types of ADCs: the flash ADC
Flash ADC has 2B − 1 comparators
Extremely fast with limited resolution
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Types of ADCs: the pipeline ADC
Pipeline ADCs have moderate speed and high resolution
[Image from B. Murmann notes]
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Types of ADCs: the sar adc
SAR ADCs can have moderate speeds and resolution (some reach 18
bits) and very low power
[Image from B. Murmann notes]
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Types of ADCs
Sigma-delta
Algorithmic
Single-slope
Time-to-digital
Logarithmic
Compressive sensing
... references previously mentioned discuss most of these
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Moore’s law reapplied: research trend in ADCs
[Jonsson 2012]
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Questions?
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Part II
The Time-Interleaved ADC
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Introduction to time-interleaved ADCs
Definition
An ADC that cycles through a set of N sub-ADCs
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Introduction to time-interleaved ADCs
Definition
An ADC that cycles through a set of N sub-ADCs, such that the aggregate
sample-rate is N times the sample-rate of the individual sub-ADCs
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Introduction to time-interleaved ADCs
0(t)
ADC0
1(t)
x(t)
....
ADC1
y[n]
N-1(t)
ADCN-1
Sub-ADCs tend to be identical
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Back in 1980 ...
William Black, Ph.D. thesis
“High Speed CMOS A/D
conversion techniques”
Published “Time-Interleaved
Converter Arrays”
[Black 1980]
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Back in 1980 ...
William Black, Ph.D. thesis
“High Speed CMOS A/D
conversion techniques”
Published “Time-Interleaved
Converter Arrays”
This “high speed” technique was for a 7-bit 2.5 MHz ADC
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... 30 years later
Time-interleaved ADCs are still a serious research area
Multi-GHZ ADCs are the norm
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Agilent, 2003: 80-way interleaved 20 GS/s
Fujitsu, 2009: 4-way interleaved 56 GS/s
Nortel, 2010: 16-way interleaved 40 GS/s
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How exactly does it work?
Intuitive in the time-domain
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FirstExample
ADC samples
signal
...
of the
Two
Interleaved
Sub-ADCs
ADC0
y[n]
x(t)
x(t)
ADC1
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Second
ADC samples
the signal
...
Example
of Two
Interleaved
Sub-ADCs
ADC0
x(t)
x(t)
y[n]
ADC1
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AndExample
again, first ADC
samples
the signal ...Sub-ADCs
(ad infinitum)
of Two
Interleaved
ADC0
y[n]
x(t)
x(t)
ADC1
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Time-domain analysis
Each sub-ADC output is (ignoring quantization)
yi [n] = x ((nN + i)Ts )
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Time-domain analysis
Each sub-ADC output is (ignoring quantization)
yi [n] = x ((nN + i)Ts )
(2)
where:
I
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Ts = sampling period of time-interleaved ADC*
N = interleaving factor
i = 0, ..., N − 1
(*NTs is the sampling period of the sub-ADC)
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Time-domain analysis
0(t)
ADC0
1(t)
x(t)
....
ADC1
y[n]
N-1(t)
ADCN-1
Output multiplexer combines these streams such that
y [n] = [y0 [0], y1 [0], ..., yN−1 [0], y0 [1], ...]
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Time-domain analysis
0(t)
ADC0
1(t)
x(t)
y[n]
....
ADC1
N-1(t)
ADCN-1
Output multiplexer combines these streams such that
y [n] = [y0 [0], y1 [0], ..., yN−1 [0], y0 [1], ...] = yi
n−i
N
where i = n mod N
(3)
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Time-domain analysis
Ideally:
y [n] = x(nTs )
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Time-domain analysis
Ideally:
y [n] = x(nTs )
(4)
i.e. same output as single ADC with sample rate = Ts
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Time-domain analysis
Ideally:
y [n] = x(nTs )
(4)
i.e. same output as single ADC with sample rate = Ts
It also means that this tutorial would be over ^
¨
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Frequency-domain analysis
This is less intuitive ...
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Frequency-domain analysis
This is less intuitive ...
Can take the discrete-time Fourier transform (DTFT) of
1
2
(Upsampled) sub-ADC outputs
Time-interleaved ADC output
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Frequency-domain analysis
This is less intuitive ...
Can take the discrete-time Fourier transform (DTFT) of
1
2
(Upsampled) sub-ADC outputs
Time-interleaved ADC output
Definition
Given a discrete set of real (or complex) numbers x[n], the DTFT of x[n] is
X (ω) =
∞
X
x[n]e −iωn
(5)
n=−∞
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Frequency-domain analysis
In theory, ...
Y (f ) =
N−1
X
Yi (f )
(6)
i=0
where:
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Yi (f ) = DTFT of the upsampled sub-ADC output
N = interleaving factor
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Frequency-domain analysis
Assume you have an input signal with the following DTFT
1
|X(f)|
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
f
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Frequency-domain analysis
With N = 4, the resulting (upsampled) sub-ADC output DTFT will be
0.25
|Y0(f)|
0.2
0.15
0.1
0.05
0
0
0.2
0.4
0.6
0.8
1
f
(Note the replicas due to upsampling)
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Frequency-domain analysis
Replicas have different phases for each of the sub-ADCs
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Frequency-domain analysis
Replicas have different phases for each of the sub-ADCs
These phases sum to zero
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Frequency-domain analysis
Replicas have different phases for each of the sub-ADCs
These phases sum to zero
Therefore, output has the same spectrum as input
1
|Y(f)|
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
f
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Time-varying errors
In theory, theory and practice are the same.
In practice, they are not.
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Time-varying errors
(a.k.a the reason this tutorial isn’t over yet)
Ideally, a time-interleaved ADC can be blackboxed into a single
monolithic ADC
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Time-varying errors
(a.k.a the reason this tutorial isn’t over yet)
Ideally, a time-interleaved ADC can be blackboxed into a single
monolithic ADC
As mentioned earlier, we want: y [n] = x(nTs )
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Time-varying errors
0(t- 0)
o0
Offset
G0
ADC0
Gain
1(t- 1)
Timing skew
o1
(Bandwidth)
(Nonlinearity)
G1
....
x(t)
GN-1
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y[n]
ADC1
N-1(t- N-1)
oN-1
ADCN-1
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Time-varying errors
Ideal
2
1.5
1
x(t)
0.5
0
-0.5
-1
-1.5
-2
-1
0
1
2
3
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Time-varying errors
Ideal
2
1.5
1
x(t)
0.5
0
-0.5
-1
-1.5
-2
-1
0
1
2
3
4
5
6
7
8
9
10
6
7
8
9
10
Offset
2
1.5
1
x(t)
0.5
0
-0.5
-1
-1.5
-2
-1
0
1
2
3
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Time-varying errors
Gain
Ideal
2
2
1.5
1.5
1
1
x(t)
0.5
x(t)
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
-1.5
-2
-2
-1
-1
0
1
2
3
4
5
6
7
8
9
10
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Offset
2
1.5
1
x(t)
0.5
0
-0.5
-1
-1.5
-2
-1
0
1
2
3
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Time-varying errors
Gain
Ideal
2
2
1.5
1.5
1
1
x(t)
0.5
x(t)
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
-1.5
-2
-2
-1
-1
0
1
2
3
4
5
6
7
8
9
0
1
3
4
5
6
7
8
9
10
8
9
10
Timing Skew
Offset
2
2
1.5
1.5
1
1
x(t)
0.5
x(t)
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
-1.5
-2
-2
-1
2
10
0
1
2
3
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5
6
7
8
9
-1
10
Time-Interleaved ADCs
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1
2
3
4
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Sources of errors
PVT (Process, voltage, temperature) variations
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Sources of errors
PVT (Process, voltage, temperature) variations
Current flow, layout nonidealities, mismatch in stray capacitance, etc.
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Sources of errors
PVT (Process, voltage, temperature) variations
Current flow, layout nonidealities, mismatch in stray capacitance, etc.
All of these will limit your ADC performance
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Offset mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
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Offset mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(7)
Each sub-ADC actually digitizes x(t) + oi
yi [n] = x ((nN + i)Ts ) + oi
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(8)
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Offset mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(7)
Each sub-ADC actually digitizes x(t) + oi
yi [n] = x ((nN + i)Ts ) + oi
(8)
oi is different for each sub-ADC
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Offset mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(7)
Each sub-ADC actually digitizes x(t) + oi
yi [n] = x ((nN + i)Ts ) + oi
(8)
oi is different for each sub-ADC
y [n] = [y0 [0], y1 [0],..., yN−1 [0], y0 [1], ...]
⇓
(9)
y [n] = [y0 [0] + o0 , y1 [0] + o1 , ..., yN−1 [0] + oN−1 , y0 [1] + o0 , ...]
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Frequency-domain effects
0.25
|Y0(f)|
0.2
0.15
0.1
0.05
0
0
0.2
0.4
0.6
0.8
1
f
The DTFT of the sub-ADC changes because of these offsets
I
Look at the spurs in the replicas
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Frequency-domain effects
|Y(f)|
1
0.5
0
0
0.2
0.4
0.6
0.8
1
f
The DTFT of the ADC has spurs at frequencies i · fs /N
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Gain mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
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Gain mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(10)
Each sub-ADC actually digitizes Gi x(t)
yi [n] = Gi x ((nN + i)Ts )
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(11)
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Gain mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(10)
Each sub-ADC actually digitizes Gi x(t)
yi [n] = Gi x ((nN + i)Ts )
(11)
Gi is different for each sub-ADC
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Gain mismatch
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(10)
Each sub-ADC actually digitizes Gi x(t)
yi [n] = Gi x ((nN + i)Ts )
(11)
Gi is different for each sub-ADC
y [n] = [y0 [0], y1 [0],..., yN−1 [0], y0 [1], ...]
⇓
(12)
y [n] = [G0 y0 [0], G1 y1 [0], ..., GN−1 yN−1 [0], G0 y0 [1], ...]
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Frequency-domain effects
0.2
|Y0(f)|
0.15
0.1
0.05
0
0
0.2
0.4
0.6
0.8
1
f
The DTFT of the sub-ADC changes because of these gain differences
I
Look at the amplitude (this is a function of Gi )
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Frequency-domain effects
0.8
|Y(f)|
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
f
The DTFT of the ADC has replicas at frequencies fin − i · fs /N
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Timing skew
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
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(13)
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Timing skew
Each sub-ADC ideally digitizes x(t)
yi [n] = x ((nN + i)Ts )
(13)
Each sub-ADC actually digitizes x(t − τi )
yi [n] = x ((nN + i)Ts − τi )
(14)
τi is different for each sub-ADC
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Frequency-domain effects
0.25
|Y0(f)|
0.2
0.15
0.1
0.05
0
0
0.2
0.4
0.6
0.8
1
f
The DTFT of the sub-ADC changes because of timing skew
I
Not obvious from amplitude plot, since timing skew affects phase
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
54 / 180
Frequency-domain effects
1
|Y(f)|
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
f
The DTFT of the ADC has replicas at frequencies fin − i · fs /N
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
55 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
Let’s take a closer look at offset
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
What did you notice?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
56 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And at gain
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
What did you notice?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
57 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
And finally, at timing skew
0
Y [dBc]
−20
−40
−60
−80
−100
0
0.1
0.2
0.3
Freq [Fin/Fs]
0.4
0.5
Look at the fundamental (with the dot) and the spurs
What did you notice?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
58 / 180
Some notes
Gain and offset mismatch are “static” errors
I
Impact independent of input frequency
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
59 / 180
Some notes
Gain and offset mismatch are “static” errors
I
I
Impact independent of input frequency
But ... what if gain is a function of frequency? (which it is)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
59 / 180
Some notes
Gain and offset mismatch are “static” errors
I
I
I
Impact independent of input frequency
But ... what if gain is a function of frequency? (which it is)
And ... what if the gain transfer function varies? (which it will)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
59 / 180
Some notes
Gain and offset mismatch are “static” errors
I
I
I
I
Impact independent of input frequency
But ... what if gain is a function of frequency? (which it is)
And ... what if the gain transfer function varies? (which it will)
You have bandwidth mismatch ... (see references for more information
on this)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
59 / 180
Some notes ... continued
Sampling Error Due to Timing Skew
Timing skew is not a “static” error
x(t)
x(t)
Error
Error
t
t
Skew
Ideal
Sampling
Point
Skew
Actual
Sampling
Point
Ideal
Sampling
Point
Actual
Sampling
Point
“Fast” signals suffer more sampling error
due to timing skew than “slow” signals
18
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
60 / 180
Some notes ... continued
Sampling Error Due to Timing Skew
Timing skew is not a “static” error
x(t)
x(t)
Error
Error
t
t
Skew
Ideal
Sampling
Point
Skew
Actual
Sampling
Point
Ideal
Sampling
Point
Actual
Sampling
Point
“Fast” signals suffer more sampling error
due to
timingsampling
skew thanerror
“slow”due
signals
“Fast” signals suffer
more
to timing skew than
“slow” signals
M. El-Chammas (TI)
Time-Interleaved ADCs
18
NEWCAS 2012
60 / 180
Some questions
1
Why is timing skew a problem?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Some questions
1
Why is timing skew a problem?
2
How much of a problem is it?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
61 / 180
Some questions
1
Why is timing skew a problem?
2
How much of a problem is it?
3
Where does it come from?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
61 / 180
Why is timing skew such a problem?
ADCs are generally uniform sampling systems
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
62 / 180
Why is timing skew such a problem?
ADCs are generally uniform sampling systems
What if two consecutive samples aren’t at times nTs and (n + 1)Ts ?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
62 / 180
Why is timing skew such a problem?
ADCs are generally uniform sampling systems
What if two consecutive samples aren’t at times nTs and (n + 1)Ts ?
I
If the deviation is random, you have jitter
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
62 / 180
Why is timing skew such a problem?
ADCs are generally uniform sampling systems
What if two consecutive samples aren’t at times nTs and (n + 1)Ts ?
I
I
If the deviation is random, you have jitter
If the deviation is deterministically time-varying because you are
interleaving, you have timing skew
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
62 / 180
Why is timing skew such a problem?
ADCs are generally uniform sampling systems
What if two consecutive samples aren’t at times nTs and (n + 1)Ts ?
I
If the deviation is random, you have jitter
If the deviation is deterministically time-varying because you are
interleaving, you have timing skew
I
Sidenote: Timing skew becomes jitter as N → ∞
I
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Why is timing skew such a problem?
Timing skew is not fundamentally a problem
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
63 / 180
Why is timing skew such a problem?
Timing skew is not fundamentally a problem
Reconstruction of nonuniformly sampled signals still possible! (see
sampling theory for more details)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
63 / 180
How much of a problem is timing skew?
Interleave N B-bit sub-ADCs
Input signal is sinusoid with frequency fin
s
στ =
N
N −1
1
2
·
·
3(2πfin )2
22B
(15)
[Jenq 1988]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
64 / 180
How much of a problem is timing skew?
8
fin = 2 GHz
fin = 4 GHz
ADC Resolution [Bits]
7
fin = 8 GHz
fin = 16 GHz
6
5
4
3
2
0.1
1
10
Standard Deviation of Skew [ps]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
65 / 180
Where does timing skew come from?
Clocking circuitry
Sampling circuitry
Clock and signal routing
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
66 / 180
Where does timing skew come from?
Clocking circuitry
Sampling circuitry
Clock and signal routing
... to name the more obvious sources ...
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
66 / 180
Sources of timing skew: random mismatch
Vout1
Vin
Vout2
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Sources of timing skew: random mismatch
3
Vout1
Vin
Vout2
3σ Timing Skew [ps]
2.5
2
1.5
1
0.5
0
0
0.2
0.4
0.6
Normalized Power
0.8
1
Threshold mismatch causes delay change
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
67 / 180
Sources of timing skew: random mismatch
3
Vout1
Vin
Vout2
3σ Timing Skew [ps]
2.5
2
1.5
1
0.5
0
0
0.2
0.4
0.6
Normalized Power
0.8
1
Threshold mismatch causes delay change
Rule: Halve deviation with four-fold increase in power (Pelgrom’s
equation)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
67 / 180
Sources of timing skew: routing mismatch
C+ C
Vout1
Vin
Vout2
C
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
68 / 180
Sources of timing skew: routing mismatch
8
Vout1
Vin
Vout2
C
3σ Timing Skew [ps]
C+ C
6
4
2
0
0
2
4
6
8
10
∆ C / C [%]
12
14
16
Trace RC differences cause delay change
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
68 / 180
Phase Generator
Sources of timing skew
Vin
To
Sub-ADC
Vin
To
Sub-ADC
Can easily have over 10 ps skew [Agrawal 2008]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
69 / 180
To summarize
Time-interleaving introduces mismatch
I
offset, gain, timing skew, ...
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
70 / 180
To summarize
Time-interleaving introduces mismatch
I
offset, gain, timing skew, ...
How do we design time-interleaved ADCs?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
70 / 180
Questions?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
71 / 180
Part III
Quantitative Analysis of Time-Varying Errors
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Errors exist. What can we do?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
73 / 180
Errors exist. What can we do?
Step 1: Quantify error you can tolerate
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
73 / 180
Errors exist. What can we do?
Step 1: Quantify error you can tolerate
Step 2: Define your design space
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
73 / 180
The sinusoidal approach
Most ADC simulated and tested with a sine wave input
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
74 / 180
The sinusoidal approach
Most ADC simulated and tested with a sine wave input
Allows you to define dynamic performance metrics
I
I
I
I
Fundamental tone and harmonics
SFDR: Spurious free dynamic range
SNR: Signal to noise ratio
SNDR: Signal to noise and distortion ratio
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
74 / 180
The sinusoidal approach
Most ADC simulated and tested with a sine wave input
Allows you to define dynamic performance metrics
I
I
I
I
Fundamental tone and harmonics
SFDR: Spurious free dynamic range
SNR: Signal to noise ratio
SNDR: Signal to noise and distortion ratio
Can do the same for time-varying errors
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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The sinusoidal approach
Given a mismatch (e.g. offset), calculate the following:
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
75 / 180
The sinusoidal approach
Given a mismatch (e.g. offset), calculate the following:
I
The power PS of the fundamental
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
75 / 180
The sinusoidal approach
Given a mismatch (e.g. offset), calculate the following:
I
I
The power PS of the fundamental
The power PN of the resulting spurs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
75 / 180
The sinusoidal approach
Given a mismatch (e.g. offset), calculate the following:
I
I
I
The power PS of the fundamental
The power PN of the resulting spurs
SNRM = PPNS
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
75 / 180
The sinusoidal approach
We also know that:
I
SNRQ =
M. El-Chammas (TI)
3
2
· 22B (SNR due to quantization)
Time-Interleaved ADCs
NEWCAS 2012
76 / 180
The sinusoidal approach
We also know that:
I
SNRQ =
3
2
· 22B (SNR due to quantization)
What mismatch causes SNRQ = SNRM ?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
76 / 180
Bounds on time-varying errors (part 1)
Bound on offset
s
σo =
M. El-Chammas (TI)
N
N −1
A2
·
3 · 22B
Time-Interleaved ADCs
(16)
NEWCAS 2012
77 / 180
Bounds on time-varying errors (part 1)
Bound on offset
s
σo =
N
N −1
A2
·
3 · 22B
(16)
N
N −1
·
(17)
Bound on gain
s
σg =
M. El-Chammas (TI)
Time-Interleaved ADCs
2
3 · 22B
NEWCAS 2012
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Bounds on time-varying errors (part 1)
Bound on offset
s
σo =
N
N −1
A2
·
3 · 22B
(16)
N
N −1
·
(17)
Bound on gain
s
σg =
Bound on timing skew
s
στ =
N
N −1
·
2
3 · 22B
3 · 22B
2
· (2πfin )2
(18)
[Jamal 2001]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
77 / 180
Examples
5-bit ADC with input amplitude A = 1 and N = 2
I
I
I
σo = 25 mV
σg = 3.6 %
1
(e.g. fin = 100 MHz, στ ≈ 57 ps)
στ = 175·f
in
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
78 / 180
Examples
5-bit ADC with input amplitude A = 1 and N = 2
I
I
I
σo = 25 mV
σg = 3.6 %
1
(e.g. fin = 100 MHz, στ ≈ 57 ps)
στ = 175·f
in
12-bit ADC with input amplitude A = 1 and N = 2
I
I
I
σo = 0.2 mV
σg = 0.028 %
1
στ = 22,000·f
(e.g. fin = 100 MHz, στ ≈ 0.5 ps)
in
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Examples
Offset should be less than 0.2 mV?
I
σVt ≈
√3
WL
M. El-Chammas (TI)
mV/µm
Time-Interleaved ADCs
NEWCAS 2012
79 / 180
Examples
Offset should be less than 0.2 mV?
√3
WL
I
σVt ≈
I
WL > 225µm2
M. El-Chammas (TI)
mV/µm
Time-Interleaved ADCs
NEWCAS 2012
79 / 180
Examples
Offset should be less than 0.2 mV?
√3
WL
I
σVt ≈
I
WL > 225µm2
I
W > 1.25mm in 180 nm technology
M. El-Chammas (TI)
mV/µm
Time-Interleaved ADCs
NEWCAS 2012
79 / 180
Examples
Offset should be less than 0.2 mV?
√3
WL
I
σVt ≈
I
WL > 225µm2
I
W > 1.25mm in 180 nm technology
I
W > 2.5mm in 90 nm technology
M. El-Chammas (TI)
mV/µm
Time-Interleaved ADCs
NEWCAS 2012
79 / 180
Examples
Offset should be less than 0.2 mV?
√3
WL
I
σVt ≈
I
WL > 225µm2
I
W > 1.25mm in 180 nm technology
I
W > 2.5mm in 90 nm technology
I
W > 5.6mm in 45 nm technology
F
mV/µm
If Wfinger < 10µm ⇒> 560 fingers ⇒ Good luck!
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
79 / 180
Bounds on time-varying errors (part 2)
In real-world applications, ADCs don’t sample sine waves
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
80 / 180
Bounds on time-varying errors (part 2)
In real-world applications, ADCs don’t sample sine waves
I
Many systems are Serial
broadband
High-Speed
Link
Channel
Data In
Tx
Rx
Data Out
5
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
80 / 180
Bounds on time-varying errors (part 2)
Using a sine wave at Nyquist will overdesign your system
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
81 / 180
Cost of overdesign
More chip area
More power
Longer design cycle
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
82 / 180
Cost of overdesign
More chip area
More power
Longer design cycle
More $$$
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
82 / 180
Cost of overdesign
More chip area
More power
Longer design cycle
More $$$
Use minimum-mean square error to derive more realistic bounds
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
82 / 180
“Best-fit” approach
y [n] = xo [n] + e[n]
M. El-Chammas (TI)
Time-Interleaved ADCs
(19)
NEWCAS 2012
83 / 180
“Best-fit” approach
y [n] = xo [n] + e[n]
(19)
xo [n] = Ĝ x (nTs − τ̂ )
(20)
xo [n] is the “best-fit”
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
83 / 180
“Best-fit” approach
y [n] = xo [n] + e[n]
(19)
xo [n] = Ĝ x (nTs − τ̂ )
(20)
xo [n] is the “best-fit”
Nontrivial to solve in the general sense
Solvable for WSS and WSCS signals [El-Chammas 2009]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
83 / 180
Gain (G)
Gain (G)
Intuition
Skew (t)
Skew (t)
Find vector that minimizes distance to sub-ADC vectors
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
84 / 180
Wide-sense stationary
Definition
A signal is wide-sense stationary (WSS) if its mean and autocorrelation are
not a function of time
M. El-Chammas (TI)
m(t1 ) = m(t2 ) = m
(21)
R(t1 , t1 + τ ) = R(t2 , t2 + τ ) = R(τ )
(22)
Time-Interleaved ADCs
NEWCAS 2012
85 / 180
Calculate the MSE
f (Ĝ , τ̂ ) = E e[n]2 − E [e[n]]2
(23)
where
e[n] = y [n] − xo [n]
M. El-Chammas (TI)
Time-Interleaved ADCs
(24)
NEWCAS 2012
86 / 180
Calculate the MSE
f (Ĝ , τ̂ ) =
N−1
N−1
N−1
P X 2
Ĝ X
1 X 2
Ĝ P +
Gi − 2
Gi R(τi − τ̂ ) +
o
N i=0
N i=0
N i=0 i
2
!
1
− 2
N
N−1
X
!2
oi
(25)
i=0
(work your “write” arm muscles and derive this)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
87 / 180
Calculate the “best-fit” parameters
Minimize f (Ĝ , τ̂ )
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
88 / 180
Calculate the “best-fit” parameters
Minimize f (Ĝ , τ̂ )
Differentiate with respect to Ĝ and τ̂ and set to zero
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
88 / 180
Calculate the “best-fit” parameters
Minimize f (Ĝ , τ̂ )
Differentiate with respect to Ĝ and τ̂ and set to zero
N−1
1 X
Ĝ =
Gi R(τ̂ − τi )
NP
(26)
i=0
τ̂ = arg max
τ
M. El-Chammas (TI)
N−1
X
Gi R(τ − τi )
(27)
i=0
Time-Interleaved ADCs
NEWCAS 2012
88 / 180
Mismatch or quantization limited?
SNRf =
M. El-Chammas (TI)
P
f (Ĝ , τ̂ )
Time-Interleaved ADCs
NEWCAS 2012
89 / 180
Mismatch or quantization limited?
SNRf =
M. El-Chammas (TI)
P
f (Ĝ , τ̂ )
≷
3 2B
· 2 = SNRQ
2
Time-Interleaved ADCs
(28)
NEWCAS 2012
89 / 180
Mismatch or quantization limited?
SNRf =
P
f (Ĝ , τ̂ )
≷
f (Ĝ , τ̂ ) ≶
M. El-Chammas (TI)
3 2B
· 2 = SNRQ
2
(28)
2·P
3 · 22B
(29)
Time-Interleaved ADCs
NEWCAS 2012
89 / 180
Effect of timing skew
Impact on timing skew is different than previously shown
Assume oi = 0 and Gi = 1
N−1
1 X
R(τ̂ − τi ) ≥ N
P
s
i=0
M. El-Chammas (TI)
Time-Interleaved ADCs
SNRQ − 1
SNRQ
(30)
NEWCAS 2012
90 / 180
Effect of timing skew
Impact on timing skew is different than previously shown
Assume oi = 0 and Gi = 1
N−1
1 X
R(τ̂ − τi ) ≥ N
P
s
i=0
SNRQ − 1
SNRQ
(30)
Let’s make one more assumption: the autocorrelation is second order
differentiable
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
90 / 180
Effect of timing skew
Impact on timing skew is different than previously shown
Assume oi = 0 and Gi = 1
N−1
1 X
R(τ̂ − τi ) ≥ N
P
s
i=0
SNRQ − 1
SNRQ
(30)
Let’s make one more assumption: the autocorrelation is second order
differentiable
X
+
R(τ ) ≈ R(0) + R 0X
(0)τ
X
X
M. El-Chammas (TI)
Time-Interleaved ADCs
R 00 (0) 2
τ
2
(31)
NEWCAS 2012
90 / 180
Effect of timing skew
s
στ ≤
N
N −1
·
2
3 · 22B
·
1
00
|R (0)|
(32)
Function of three parameters (N, B, and R 00 (0))
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
91 / 180
Ignoring the math
Key points:
I
WSS signals described by autocorrelation
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
92 / 180
Ignoring the math
Key points:
I
WSS signals described by autocorrelation
I
Autocorrelation related to signal “speed” (i.e. frequency components)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
92 / 180
Ignoring the math
Key points:
I
WSS signals described by autocorrelation
I
Autocorrelation related to signal “speed” (i.e. frequency components)
F
F
Narrower autocorrelation ⇔ faster signal
(This is the autocorrelation curvature)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
92 / 180
Ignoring the math
Key points:
I
WSS signals described by autocorrelation
I
Autocorrelation related to signal “speed” (i.e. frequency components)
F
F
I
Narrower autocorrelation ⇔ faster signal
(This is the autocorrelation curvature)
We know from before: higher frequencies suffer more from timing skew
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
92 / 180
Ignoring the math
Key points:
I
WSS signals described by autocorrelation
I
Autocorrelation related to signal “speed” (i.e. frequency components)
F
F
Narrower autocorrelation ⇔ faster signal
(This is the autocorrelation curvature)
I
We know from before: higher frequencies suffer more from timing skew
I
Therefore, effect of timing skew dependent on autocorrelation
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
92 / 180
More on autocorrelation intuition
x(t)
Autocorrelation related to speed of signal
R(t)
t
t
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
93 / 180
More on autocorrelation intuition
x(t)
x(t)
Autocorrelation related to speed of signal
t
R(t)
R(t)
t
t
M. El-Chammas (TI)
t
Time-Interleaved ADCs
NEWCAS 2012
93 / 180
Importance of signal statistics
R(τ ) = sinc(2fc τ )
M. El-Chammas (TI)
Time-Interleaved ADCs
(33)
NEWCAS 2012
94 / 180
Importance of signal statistics
R(τ ) = sinc(2fc τ )
(33)
1
R 00 (0) = − (2πfc )2
3
(34)
Using sine wave analysis overconstrains the variance of τ by 3
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
94 / 180
Importance of signal statistics
Same applies to more realistic signals (e.g. WSCS)
If timing skew is a problem, then improve your design space by
knowing your system
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
95 / 180
Importance of signal statistics
Same applies to more realistic signals (e.g. WSCS)
If timing skew is a problem, then improve your design space by
knowing your system
Sidenote: this viewpoint also extends to nonlinearities and jitter
I
See e.g. [Gupta 2006] and [Da Dalt 2002]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
95 / 180
Questions?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
96 / 180
Part IV
Design of Time-Interleaved ADCs
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
97 / 180
The coolest ADCs from the past 10 years
Agilent, 2003, ISSCC
Terranetics, JSSC 2006
Nortel, ISSCC 2010
Fujitsu, OFC 2010
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
98 / 180
Interleaving 80 pipeline ADCs
20 GS/s 8 bit ADC
Correct for gain, offset, and timing skew [Poulton 2003]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
99 / 180
Interleaving 4 pipeline ADCs
1 GS/s 11 bit ADC
Correct for gain and offset [Gupta 2006]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
100 / 180
Interleaving 16(0) SAR ADCs
40 GS/s 6 bit ADC
Correct for gain, offset, and timing skew [Greshishchev 2010]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
101 / 180
A 56 GS/s ADC
56 GS/s 8 bit ADC and interleaved 4x80 ADCs [Dedic 2010]
M. El-Chammas (TI)
Time-Interleaved ADCs
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102 / 180
Choosing the design space
1
You have: input signal statistics + bit resolution + application space
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
103 / 180
Choosing the design space
1
You have: input signal statistics + bit resolution + application space
2
Calculate acceptable bounds on time-varying errors
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
103 / 180
Choosing the design space
1
You have: input signal statistics + bit resolution + application space
2
Calculate acceptable bounds on time-varying errors
3
Choose sub-ADC architecture (beyond scope of tutorial)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
103 / 180
Choosing the design space
1
You have: input signal statistics + bit resolution + application space
2
Calculate acceptable bounds on time-varying errors
3
Choose sub-ADC architecture (beyond scope of tutorial)
4
Choose interleaving factor
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
103 / 180
Choosing the design space
1
You have: input signal statistics + bit resolution + application space
2
Calculate acceptable bounds on time-varying errors
3
Choose sub-ADC architecture (beyond scope of tutorial)
4
Choose interleaving factor
5
Design clocking network
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
103 / 180
Choosing the design space
1
You have: input signal statistics + bit resolution + application space
2
Calculate acceptable bounds on time-varying errors
3
Choose sub-ADC architecture (beyond scope of tutorial)
4
Choose interleaving factor
5
Design clocking network
6
Deal with time-varying errors
Looks simpler than it is
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
103 / 180
Sub-ADC architecture
Extremely low end resolution and high end resolution choice is easy
I
I
Flash ADCs for 3 bits
Sigma-Delta for 24 bits
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
104 / 180
Sub-ADC architecture
Extremely low end resolution and high end resolution choice is easy
I
I
Flash ADCs for 3 bits
Sigma-Delta for 24 bits
SAR, pipeline, ...
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Sub-ADC architecture
10
10
P/fs [Joules]
10
10
10
http://www.stanford.edu/~murmann/adcsurvey.html
-6
-7
-8
-9
FOM
P
fs 2ENOB
10
10
fJ
conv-step
-10
ENOB
10
100
-11
Flash
Pipeline
SAR
Sigma-Delta
Other
-12
-13
20
30
40
50
60
70
SNDR [dB]
80
90
100
SNDR[ dB ] 1.76
6.02
110
[Image from Murmann class notes]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
105 / 180
Interleaving can lower power*
Lessons from parallel processing [Horowitz 2006]
* at the expense of complexity, area, and headache
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
106 / 180
Interleaving can lower power
[Maloberti 2008]
11-bit ADC at 100 MS/s needs ∼ 23 mW
At 800 MS/s needs ∼ 700 mW
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
107 / 180
Interleaving can lower power
75
70
65
Power [mW]
60
55
50
45
40
35
30
3
4
5
6
7
8
Interleaving Factor
9
10
11
12
Increasing fs will force you to hit a technological wall
True even in the smallest ADC element - the comparator
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
108 / 180
Interleaving can lower power - with diminishing returns ...
11-bit ADC at 800 MS/s needs ∼ 700 mW
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
109 / 180
Interleaving can lower power - with diminishing returns ...
11-bit ADC at 800 MS/s needs ∼ 700 mW
At 100 MS/s needs ∼ 23 mW ⇒ 184 mW with N = 8
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
109 / 180
Interleaving can lower power - with diminishing returns ...
11-bit ADC at 800 MS/s needs ∼ 700 mW
At 100 MS/s needs ∼ 23 mW ⇒ 184 mW with N = 8
At 200 MS/s needs ∼ 50 mW ⇒ 200 mW with N = 4
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
109 / 180
Interleaving can lower power - with diminishing returns ...
11-bit ADC at 800 MS/s needs ∼ 700 mW
At 100 MS/s needs ∼ 23 mW ⇒ 184 mW with N = 8
At 200 MS/s needs ∼ 50 mW ⇒ 200 mW with N = 4
At 400 MS/s needs ∼ 150 mW ⇒ 300 mW with N = 2
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
109 / 180
Interleaving can lower power - with diminishing returns ...
11-bit ADC at 800 MS/s needs ∼ 700 mW
At 100 MS/s needs ∼ 23 mW ⇒ 184 mW with N = 8
At 200 MS/s needs ∼ 50 mW ⇒ 200 mW with N = 4
At 400 MS/s needs ∼ 150 mW ⇒ 300 mW with N = 2
Is an interleaving factor of 8 really the best?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
109 / 180
Clocking network
Input Clock
0(t)
Ts
Phase Generator
1(t)
Ts
........
2(t)
Ts
0(t)
1(t)
N-1(t)
N-1(t)
t
Sub-ADC Clocks
Phase Generator
Need to provide N clocks to sub-ADCs
(t) offset
(t)
Ideally
by Ts
0
1
M. El-Chammas (TI)
N-1(t)
Time-Interleaved ADCs
NEWCAS 2012
110 / 180
Clocking network
Phase locked loops and delay locked loops
Can use frequencies lower than sub-ADC sample rates
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
111 / 180
Clocking network
Clock-gating
Use full-rate clocks and control sub-ADC clock with digital logic (e.g.
[Louwsma 2008])
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
112 / 180
Clocking network
Shift registers (e.g. [Gao 2008])
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Time-varying errors?
You’ve chosen your sub-ADC architecture
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
114 / 180
Time-varying errors?
You’ve chosen your sub-ADC architecture
and your interleaving factor
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
114 / 180
Time-varying errors?
You’ve chosen your sub-ADC architecture
and your interleaving factor
and designed your clocking network
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
114 / 180
Time-varying errors?
You’ve chosen your sub-ADC architecture
and your interleaving factor
and designed your clocking network
How do you deal with time-varying errors?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
114 / 180
Time-varying errors?
You’ve chosen your sub-ADC architecture
and your interleaving factor
and designed your clocking network
How do you deal with time-varying errors?
Two approaches: correct by design
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
114 / 180
Time-varying errors?
You’ve chosen your sub-ADC architecture
and your interleaving factor
and designed your clocking network
How do you deal with time-varying errors?
Two approaches: correct by design or correct with calibration
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
114 / 180
Approach 1: by design
voffset ≈ √
3
mV /µm
WL
(35)
Pelgrom’s Model
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
115 / 180
Approach 1: by design
voffset ≈ √
3
mV /µm
WL
(35)
Pelgrom’s Model
12-bit ADC, 1 Vp−p requires less than 0.2 mV offset
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
115 / 180
Approach 1: by design
voffset ≈ √
3
mV /µm
WL
(35)
Pelgrom’s Model
12-bit ADC, 1 Vp−p requires less than 0.2 mV offset
WL > 225µm2
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
115 / 180
Approach 1: by design
voffset ≈ √
3
mV /µm
WL
(35)
Pelgrom’s Model
12-bit ADC, 1 Vp−p requires less than 0.2 mV offset
WL > 225µm2
In 65 nm CMOS, W > 3.4 mm ...
Just increasing transistor size not acceptable
(This also ignores other sources of error!)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
115 / 180
Approach 1: by design
There exist analog offset-minimization techniques for amplifiers and
comparators
[Suarez 1975]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
116 / 180
Approach 1: by design
There exist analog offset-minimization techniques for amplifiers and
comparators
[Suarez 1975]
Most of these are extremely old (and still valid)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
116 / 180
Approach 1: by design
Trimming
Dynamic techniques: auto-zeroing or chopping
[Makinwa 2002]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
117 / 180
Approach 1: by design
Introduce redundancy
[Ginsburg 2008]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
118 / 180
Approach 1: by design
Introduce redundancy
[Ginsburg 2008]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
119 / 180
Some design techniques for timing skew
Timing skew problem exists between track-and-holds
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
120 / 180
Some design techniques for timing skew
Timing skew problem exists between track-and-holds
Use a front-end sampler
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
120 / 180
Front-end sampler
[Poulton 1987]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
121 / 180
Front-end sampler
Possible Solution: Hide Timing Skew
Add a sampler to the ADC front-end and use a full-rate clock
S. Gupta et al, “A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth
Scalable Time-Interleaved Architecture “, IEEE JSSC, Dec. 2006, vol. 41, pp. 2650 - 2657
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012 28 122 / 180
Front-end sampler
Possible Solution: Hide Timing Skew
Add
Add a
a sampler
sampler to
to the
the ADC
ADC front-end
front-end and
and use
use a
a full-rate
full-rate clock
clock
to hold the input every clock period
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012 29 123 / 180
Front-end sampler
Possible Solution: Hide Timing Skew
Sub-ADC clocks have some margin for error
Requires a full-rate clock and a sampler
that can settle fast enough
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012 31 124 / 180
Front-end sampler
[Gupta 2006]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
125 / 180
Use a better clocking scheme
Front-end samplers have limited application
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
126 / 180
Use a better clocking scheme
Front-end samplers have limited application
[Louwsma 2008]
10 b, 1.35 GS/s
Transistor threshold limitation
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
126 / 180
Questions?
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
127 / 180
Part V
Calibration
M. El-Chammas (TI)
Time-Interleaved ADCs
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128 / 180
Experience is simply the name we give our mistakes
- Oscar Wilde
M. El-Chammas (TI)
Time-Interleaved ADCs
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Approach 2: use calibration
Straightforward for offset and gain
Not as trivial for timing skew
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
130 / 180
Calibration = estimation + correction
Definition
Estimation: An approximation of the value or extent of something
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
131 / 180
Calibration = estimation + correction
Definition
Correction: The action or process of correcting something
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Calibration = estimation + correction
Definition
Estimation: An approximation of the value or extent of something
This creates a feedback loop ⇒ Compensate for mismatch!
Definition
Correction: The action or process of correcting something
M. El-Chammas (TI)
Time-Interleaved ADCs
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Types of calibration
Digital vs. mixed-signal
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Types of calibration
Digital vs. mixed-signal
Foreground vs. background
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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Digital calibration
ADC0
y0[n]
ADC1
y1[n]
Time-Interleaved ADCs
Adaptive
Filter
~y0[n]
Digital
Backend
Detection
x(t)
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Adaptive
Filter
~y1[n]
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Mixed-signal calibration
y0[n]
ADC0
ADC1
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Digital
Backend
Detection
x(t)
y1[n]
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Foreground calibration
Input
Output
Test
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Foreground calibration
Input
No
Output
Test
Detection
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Background calibration
Input
Output
Detection
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Offset and gain “almost” solved problem
Still a research topic
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Offset and gain “almost” solved problem
Still a research topic
But ... there is a popular solution
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Correcting offset
Estimation ... (calculate the mean)
X
oi ∝
Di,j
(36)
j
Correction ... (subtract the mean)
D̂i,j = Di,j − oi
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Time-Interleaved ADCs
(37)
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Correcting gain
Estimation ... (calculate the gain)
X
Gi ∝
(Di,j )2
(38)
j
Correction ... (divide by the gain)
D̂i,j = Di,j /Gi
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Time-Interleaved ADCs
(39)
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Example 1 (1998)
[Fu 1998]
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Example 1 (1998)
[Fu 1998]
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Example 1 (1998)
10-bit, 40 MS/s, two-way interleaved ADC [Fu 1998]
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Example 2 (2001)
[Jamal 2001]
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Example 2 (2001)
[Jamal 2001]
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Example 3 (2007)
[Oh 2007]
Makes use of pilot tones in OFDM systems
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Example 3 (2007)
[Oh 2007]
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Time-Interleaved ADCs
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Example 3 (2007)
[Oh 2007]
6-bit, 200 MS/s
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Time-Interleaved ADCs
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Example 4 (2012)
[Liu 2012]
8-bit, 600 MS/s SAR ADC
Correct offset, gain, inter-channel nonlinearity with equalization
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And timing skew?
Still ongoing research
No single winner
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Time-Interleaved ADCs
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Example 1 (2001)
[Jamal 2001]
Requires fractional delay filter
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Time-Interleaved ADCs
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Example 1 (2001)
[Jamal 2001]
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Example 2 (2003)
[Poulton 2003]
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Example 2 (2003)
[Poulton 2003]
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Example 2 (2003)
Foreground calibration
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Time-Interleaved ADCs
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Example 2 (2003)
Foreground calibration
Apply pulse train with fast edges
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Time-Interleaved ADCs
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Example 2 (2003)
Foreground calibration
Apply pulse train with fast edges
Use FFT to measure phase delay of T/H
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Time-Interleaved ADCs
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Example 2 (2003)
Foreground calibration
Apply pulse train with fast edges
Use FFT to measure phase delay of T/H
Adjust time delay (using delay cells)
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Time-Interleaved ADCs
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Example 2 (2003)
Foreground calibration
Apply pulse train with fast edges
Use FFT to measure phase delay of T/H
Adjust time delay (using delay cells)
Rinse and repeat
[Poulton 2003]
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Time-Interleaved ADCs
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Example 3 (2005)
[Elbornsson 2005]
Digital and background calibration
Uses cost function based on input statistics
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Time-Interleaved ADCs
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Example 3 (2005)
[Elbornsson 2005]
Use inverse DTFT to reconstruct signal using timing estimation
Update timing estimation with cost function
I
i.e. has cost function decreased or increased?
Requires bandlimited signal
I
Common limitation of many blind calibration algorithms
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Time-Interleaved ADCs
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Example 4 (2008)
Use information between channels
[Haftbaradaran 2008]
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Time-Interleaved ADCs
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Example 4 (2008)
[Haftbaradaran 2008]
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Time-Interleaved ADCs
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Example 4 (2008)
[Haftbaradaran 2008]
Has 0.86 ps delay change (on average)
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Time-Interleaved ADCs
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Example 4 (2008)
[Haftbaradaran 2008]
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Time-Interleaved ADCs
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Example 5 (2010)
[Huang 2010]
6-bit 16 GS/s flash ADC
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Time-Interleaved ADCs
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Example 5 (2010)
[Huang 2010]
M. El-Chammas (TI)
Time-Interleaved ADCs
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Example 5 (2010)
[Huang 2010]
Change capacitive load on delay cells (similar to [Poulton 2003])
M. El-Chammas (TI)
Time-Interleaved ADCs
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Example 6 (2010)
[El-Chammas 2010]
5-bit 12 GS/s
Add extra channel (used 1-bit ADC in implementation)
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Time-Interleaved ADCs
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Example 6 (2010)
M. El-Chammas (TI)
Time-Interleaved ADCs
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Example 6 (2010)
Maximize correlation between extra ADC and each sub-ADC by
adjusting delay cell
M. El-Chammas (TI)
Time-Interleaved ADCs
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167 / 180
Example 6 (2010)
Adjust delay cell load (around 0.3 ps resolution)
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Time-Interleaved ADCs
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Example 6 (2010)
Several hundred milliseconds for initial convergence
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Time-Interleaved ADCs
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Example 7 (2011)
[Payne 2011]
12 bit 1GS/s ADC
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Time-Interleaved ADCs
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170 / 180
And many more ...
There are many more approaches for timing skew calibration
M. El-Chammas (TI)
Time-Interleaved ADCs
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171 / 180
And many more ...
There are many more approaches for timing skew calibration
Some require energy free bands, and others don’t
M. El-Chammas (TI)
Time-Interleaved ADCs
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And many more ...
There are many more approaches for timing skew calibration
Some require energy free bands, and others don’t
Some use fractional delay filters, and others tune delay with delay cells
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
171 / 180
And many more ...
There are many more approaches for timing skew calibration
Some require energy free bands, and others don’t
Some use fractional delay filters, and others tune delay with delay cells
On going research in both estimation and correction blocks
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
171 / 180
Current time-interleaved ADCs
4
10
3
Energy [pJ]
10
2
10
1
10
0
ADCs
FOM=1 pJ/conv−step
FOM=0.1 pJ/conv−step
10
−1
10
15
20
25
30
35
40
45
50
55
60
SNDR [dB]
ADCs faster than 1 GS/s (published in ISSCC and VLSI)
[Murmann]
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Time-Interleaved ADCs
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172 / 180
Current time-interleaved ADCs
ADCs faster than 10 GS/s
[Murmann]
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
173 / 180
Making sense of the noise
Time-interleaved ADCs ⇒ can increase sampling rate
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
174 / 180
Making sense of the noise
Time-interleaved ADCs ⇒ can increase sampling rate
Also introduce time-varying errors (offset, gain, timing skew, ...)
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
174 / 180
Making sense of the noise
Time-interleaved ADCs ⇒ can increase sampling rate
Also introduce time-varying errors (offset, gain, timing skew, ...)
System-level analysis improves design space specifications
I
i.e. mismatch constraints and ADC architecture
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
174 / 180
Making sense of the noise
Time-interleaved ADCs ⇒ can increase sampling rate
Also introduce time-varying errors (offset, gain, timing skew, ...)
System-level analysis improves design space specifications
I
i.e. mismatch constraints and ADC architecture
Careful design and layout is a start
I
Not always enough ⇒ use calibration
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
174 / 180
Making sense of the noise
Time-interleaved ADCs ⇒ can increase sampling rate
Also introduce time-varying errors (offset, gain, timing skew, ...)
System-level analysis improves design space specifications
I
i.e. mismatch constraints and ADC architecture
Careful design and layout is a start
I
I
Not always enough ⇒ use calibration
“Optimal” calibration is application and system dependent
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
174 / 180
Making sense of the noise
Time-interleaved ADCs ⇒ can increase sampling rate
Also introduce time-varying errors (offset, gain, timing skew, ...)
System-level analysis improves design space specifications
I
i.e. mismatch constraints and ADC architecture
Careful design and layout is a start
I
I
Not always enough ⇒ use calibration
“Optimal” calibration is application and system dependent
Problems ⇔ Opportunities
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
174 / 180
Thank you
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
175 / 180
Questions?
Email: manar@ti.com, manar.chammas@gmail.com
M. El-Chammas (TI)
Time-Interleaved ADCs
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References (1)
A. Agrawal, A. Liu, P. Hanumolu, and G.-Y. Wei, “An 8×5 Gb/s Parallel Receiver With
Collaborative Riming Recovery,” IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp.
3120-3130, Nov. 2009
W. Black and D. Hodges, “Time Interleaved Converter Arrays,” IEEE Journal of
Solid-State Circuits, vol. 15, no. 6, pp. 1022-1029, Dec. 1980
F.H. Blecher, “Junction-transistor Circuits for Analogue-to-binary Code Conversion,
Proceedings of IEEE International Solid-State Circuits Conference, Feb. 1955, pp. 18
N. Da Dalt, M. Hareneck, C. Sandner, and A. Wiesbauer, “On the Jitter Requirements of
the Sampling Clock for Analog-to-Digital Converters,” IEEE Transactions on Circuits and
Systems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1354-1360, Sep.
2002
I. Dedic, “56 GS/s ADC Enabling 100GbE,” OFC 2010
M. El-Chammas and B. Murmann, “General Analysis on the Impact of Phase-Skew in
Time-Interleaved ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers,
vol. 56, no. 5, pp. 902-910, May 2009
M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC
With Background Timing Skew Calibration,” in VLSI Circuits Symposium, Digest of
Technical Papers, June 2010, pp. 157-158
J. Elbornsson, F. Gustafsson, and J.-E. Eklund, “Blind Equalization of Time Errors in a
Time-Interleaved ADC System”, IEEE Transactions on Signal Processing, vol. 53, no. 4,
pp. 1413-1424, Apr. 2005
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
177 / 180
References (2)
D. Fu, K.C. Dyer, S.H. Lewis, and P.J. Hurst, “A Digital Background Calibration
Technique for Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of
Solid-State Circuits, vol. 33, no. 12, pp. 1904-1911, Dec. 1998
X. Gao, E. Klumperink, and B. Nauta, “Advantages of Shift Registers Over DLLs for
Flexible Low Jitter Multiphase Clock Generation,” IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 55, no. 3, pp. 244-248, Mar. 2008
B. Ginsburg and A. Chandrakasan, “Highly Interleaved 5b 250 MS/s ADC with
Redundant Channels in 65nm CMOS,” in Proceedings of IEEE International Solid-State
Circuits Conference, vol. 1, Feb. 2008, pp. 240-610
Y. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida,
D. Pollex, P. Schvan, and S.-C. Wang, “A 40 GS/s 6b ADC in 65nm CMOS,” in
Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2010, pp.
390-391
S. Gupta, M. Inergield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW
Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture,” IEEE
Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2650-2657, Dec. 2006
A. Haftbaradaran and K.W. Martin, “A Background Sample-Time Error Calibration
Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs,”
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 3, pp. 234-238,
Mar. 2008
M. Horowitz, “Scaling, Power and the Future of CMOS,” Workshop on On- and Off-Chip
Interconnection Networks for Multicore Systems, Stanford, CA, Dec. 2006
M. El-Chammas (TI)
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References (3)
C.-C. Huang, C.-Y. Wang, and J.-T. Wu, “A CMOS 6-bit 16-GS/s Time-Interleaved ADC
with Digital Background Calibration,” in VLSI Circuits Symposium, Digest of Technical
Papers, June 2010, pp. 159-160
S. Jamal, “Digital Background Calibration of Time-Interleaved Analog-to-Digital
Converters,” Ph.D. dissertation, U.C. Davis, Davis, CA, 2001
Y.-C. Jenq, “Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and
High-Speed Waveform Digitizers,” IEEE Transactions on Instrumentation and
Measurement, vol. 37, no. 2, pp. 245-251, June 1988
B.E. Jonsson, “ADC Research Trends: Overall publication count,” Converter Passion,
May 2012, Available: http://converterpassion.wordpress.com
W. Liu and Y. Chiu, “Time-Interleaved Analog-to-Digital Conversion With Online
Adaptive Equalization,” in IEEE Transaction on Circ. and Sys. I: Regular papers, to be
published
S. Louwsma, A. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW
Time-Interleaved AD Converter in 0.13 µm CMOS,” IEEE Journal of Solid-State Circuits,
vol. 43, no. 4, pp. 778-786, Apr. 2008
K. Makinwa, “Dynamic Offset-Cancellation Techniques,” Smart Sensor Systems, 2002
F. Maloberti, “High-Performance Data Converters: Trends, Process Technologies and
Design Challenges,” IEEE Asia Pacific Conference on Circuits and Systems, vol. 1, Nov.
2008, pp. 12-16
B. Murmann, EE315B 2010 Class Notes, Stanford University
M. El-Chammas (TI)
Time-Interleaved ADCs
NEWCAS 2012
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References (4)
B. Murmann, “ADC Performance Survey 1997-2012,” [Online]. Available:
http://www.stanford.edu/ murmann/adcsurvey.html
Y. Oh and B. Murmann, “A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM
Pilot Tone Calibration,” in Proceedings of IEEE Custom Integrated Circuits Conf., San
Jose, CA, Sep. 2007, pp. 193-194
R. Payne, et al., “A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC,”
in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2011,
pp. 182-183
K. Poulton, J. Corcoran, and T. Hornak, “A 1-GHz 6-bit ADC System,” IEEE Journal of
Solid-State Circuits, vol. 22, no. 6, pp. 962-970, Dec. 1987
K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C.
Tan, and A. Montijo, “A 20 GS/s 8 b ADC with a 1 MB Memory in 0.18 µm CMOS,” in
Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2003, pp.
318-496
R.E. Suarez, P.R. Gray, and D.A. Hodges, “All-MOS Charge Redistribution
Analog-to-Digital Conversion Techniques–Part II,” IEEE Journal of Solid-State Circuits,
vol. sc-10, no. 6, pp. 379-385, Dec. 1975
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