Physikalisches Institut
UNI-Heidelberg
Venelin Angelov
Elektronikwerkstatt
© V. Angelov
IKP Uni-Köln 05.08.2013
1
Digital system design with
FPGA
• Logic Box
• SUbmodules available
• Some Designs
• 7x100 MHz ADC
• Dual MALU
• TDC
• The new DL711 Logic Box
• The new ADC SUBmodule
© V. Angelov
IKP Uni-Köln 05.08.2013
2
Logic Box
•
•
•
•
•
Block Diagram
USB Interface
User Design
Top & Contraints Generator
Design Flow
© V. Angelov
IKP Uni-Köln 05.08.2013
3
Block Diagram of DL701/6/9
FPGA
+
4 or 8 SU7xx
SU 0
SU 1
USB Controller
32
32
RESET
i/o
i/o
. . .
32
Top of
the
user
design
i/o
CLK
32
Caddr
CDin
32
CDout
CDout
32
CDin
CRD
CRD
CWR
CWR
CRdy
o
o
o
o
o
i
i
Activity
LED_back
FTDI or Cypress
USB
Interface
CReset
16
DMA_Nwords
32
DMA_Addr
2
+
RES_n
CRdy
CReset
Optional
SU 3|7
Caddr
USB
connector
bytes
JTAG
connector
DMA_dsize
DMA_Ainc
DMA_req
DMA_ena
DMA_ack
CLK
Program
Flash
Digital Clock
Manager (DCM)
Optional
100 MHz
Quartz
Oscillator
© V. Angelov
SerProg
JTAG
DL701/6: xc3s400
DL709/10: xc3s4000
DL711: xc6slx150t
IKP Uni-Köln 05.08.2013
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User Design
User I/Os
read port
CDin
write port
CDout
MS bits of CAddr
CWR
MS bits of CAddr
© V. Angelov
IKP Uni-Köln 05.08.2013
5
Generate Top and UCF files
specifiy the DL7xx type
gen_lb DL709
specifiy the SU7xx cards
-s2 SU704 -s3 SU736
specifiy the template file
-t ../../SRC/TOP/DL709.vhd
-o top.vhd
specifiy the VHDL output file
-u top.ucf
specifiy the UCF output file
This program supports now:
DL701, 706, 709, 710, 711
SU701, 702, 703, 704, 706, 707, 709, 710, 711, 712, 713,
714, 715, 717, 720, 721, 722, 724, 725, 726, 727,
728, 730, 731, 733, 734, 736, 737
© V. Angelov
IKP Uni-Köln 05.08.2013
6
SUbmodules overview
SU701 TTL I/O 16 channels in two groups
SU702 8 channel 14-bit ADC (MAX1149)
SU703 4 channel fast dicriminator with 2xMAX9601 (dual PECL comparator) +
2xMAX537 (4x serial DAC)
SU704 5 channel TTL or NIM I/O
SU705 4M x 16-bit RAM
SU706 100 MS/s 14-bit ADC (ADS5500)
SU707 8 channel LVDS I/O
SU709 8 temperature sensors SMT160-30 / HY-LINE #16092
SU710 2 channel 14-bit DAC
SU711 Delay
SU712 Dual 8 channel 14-bit ADC (MAX1149), like SU720 but without isolation
SU713 Dual 8 channel 14-bit DAC
SU714 ADC ADS5500
SU715 2 channel audio preamplifier
SU716 16M x 32-bit RAM
SU717 Gated integrator with ADS5500
SU720 Dual 8 channel 14-bit ADC (MAX1149), like SU712 but with isolation
© V. Angelov
IKP Uni-Köln 05.08.2013
7
SUbmodules overview
SU721 Dual 8 channel 14-bit DAC, like SU713 but with isolation
SU722 5 channel TTL I/O, like SU700 but with isolation
SU724 Toslink interface
SU725 8 channel ECL input
SU726 32 LEDs
SU727 Toslink interface
SU728 16-bit ADC and DAC
SU730 PSRAM 8M x 16 bit
SU731 4 x H-Bridge, 36V 2A
SU733 Optical In/Out
SU734 DDS Modul with AD9910
SU735 100 MS/s 14-bit ADC
SU736 2 channel fast dicriminator with programmable threshold &
hysteresis and direct NIM outputs (1xMAX9600 dual ECL
comparator + AD5624 4x serial DAC)
SU737 Optical Gigabit Ethernet with TLK2201 (SerDes) and SFP Module
© V. Angelov
IKP Uni-Köln 05.08.2013
8
7x100 MHz ADC Design
7 x 100 MHz 14-bit
ADC SUbmodules
1 x 5 TTL/NIM IO
Submodule
Multievent buffering:
4 events @ 2048
samples …
512 events @ 16
samples
Programmable
presample length
USB2.0 Interface
C, C++ or LabView
© V. Angelov
IKP Uni-Köln 05.08.2013
9
TOP BLOCK DIAGRAM
7x
ADC CLK
ANALOG_IN
SU706
ADC_CLK_IN
ADC_DATA_OUT
14
3
EVENT BUFFER
SPI
CBUS
ADC SPI
TRIGG_IN
DIS/INV
TIMESYNC_IN
DIS/INV
BUSY_OUT
CONTROL
INV
5
4
3
2
ADC DIS DIS INV
ITP TS TRG BUSY
1
0
INV INV
TS TRG
INTERFACE
TO USB CHIP
CONFIGURATION_REGISTER at 0x1000C
USB CHIP
FX2 (CYPRESS)
© V. Angelov
IKP Uni-Köln 05.08.2013
10
ADC CLOCK
7x
St at e mac hi ne
7
En ab le
SY NC
ENA
2
dP ha se
DR
DF
Ra ti o
14
Q
SU706
ADS5500
AD CC LK
CLK
CLK n
2
Rs t
ENA
D
14
Q
AD C Da ta
CLK
O utput DDR
Input DFF
DCM
DC M
CL K
RS T
Q
INC/DEC
CL K 10 0 MH z
Q
CLK
Ra ti o Fre q [M Hz]
0
10 0
1
50
2
33
3
25
dP has e
CL K 10 0 M Hz
0
0 ..1
0 ..2
0 ..3 CL K 10 0 M Hz
AD C CL K 5 0 MH z
Di sc re te ph as e o f th e
SY NC s ign al r ela ti ve to
th e AD CCL K
CL K
DC M CL K
SY NC d Pha se =1
SY NC d Pha se =0
AD C DA TA
DC M Ph ase
-2 55 .. +25 5
15
11 .. 10 9. .8
se t ra tio /d ph ase w he n dP
1 ha se
7
1
0
Note: Set the ratio and
dphase again after changing
the DCM phase even if ratio
DC M re set w he n 1
and dphase remained
UP /D N one s te p w he n bit 7=
1
unchanged!!!
di v ra tio do o ne DC M ph ase s te p w he n n o re set
© V. Angelov
IKP Uni-Köln 05.08.2013
11
ADC SPI INTERFACE
SPI DATA
15..12
Write to ADC_SPI+8 anything to reset all ADCs.
Recommended before setting the ADCs.
Write to ADC_SPI+Channel the 16-bit SPI
Data word for the corresponding function in
ADC[Channel]
1101
This is useful for adjusting the
timing in the data transfer.
0..0
DLL
0
0
0 - DLL on (for 100 MHz)
1 - DLL off (for < 60 MHz)
15..12
1110
In test pattern mode the ADCs send
1010...10
0101...01
(the bits toggle after each ADC clock)
1
10..9
0
TP
0
1
2
3
15..12
11
1111
PD
0
0..0
-
normal
all 0
all 1
test pattern
0
0..0
0 - normal
1 - power down
© V. Angelov
IKP Uni-Köln 05.08.2013
12
ADC CLOCK ADJUST 100 MHz
100 MHz, dphase 0, dll 1
1e+006
0
1
2
3
4
5
6
Bit errors for 4096 system clocks
900000
800000
700000
600000
500000
400000
300000
200000
100000
0
-200
-100
0
100
200
300
DCM delay
© V. Angelov
IKP Uni-Köln 05.08.2013
13
ADC DATA PATH
ch=0..6
DUAL PORT RAM
REG
AIN
ADC[ch]
AOUT_e
WE_e
14
SWAP
REG
MUX
Counter
13..4
even
AIN
AOUT_o
WE_o
busy
ch
2..0
32
31
SIM_MODE
00
Bit 5 in
CONFIGURATION_REGISTER
at 0x1000C
odd
Address Counter AIN, AOUT
test pattern
checker
7x14
sample+1
9..2 bits
SAMPLE
4..11 bits
2
even/odd memory
select
clear &
start
EVENT_SIZE_REGISTER at 0x1000D
© V. Angelov
sample
32
Data
EVENT
00
Addr=0x10 (relative to the
BA_EV_BUFFER)
Test
Pattern
Generator
13 bits
0
Bit 3 in
COMMAND_REGISTER at
0x1000B
Addr (relative to the BA_EV_BUFFER)
31
Addr
0
0
err counter 1
err counter 0
1
err counter 3
err counter 2
. . .
IKP Uni-Köln 05.08.2013
14
EVENT DATA FORMAT
31
READ_ORDER_REGISTER
at 0x1000F
31
30
24
20
adc6..0
r5
1.
2.
3.
4.
r4
r3
r2
r1
r0
i=0
Send r[i]
i=i+1
if r[i]=7 or i=7 exit
else goto 2
The unused ADCs are automatically turned off,
the active ADCs can be read back
4
COMMAND_REGISTER at 0x1000B
RD
CLR
TP
CHK
Read State
Machine Clear
Test Pattern Check
(toggle bits)
SFT
TRG
EB
CLR
0
TS
CLR
2
0
EVENT_SIZE_REGISTER
at 0x1000D
evsize
Timestamp with 10 ns resolution
Readout order
0
16
1
32
2
64
3 128
4 256
5 512
6 1024
7 2048
Ev. in Buffer
00
sample 1
00
sample 0
ch=r0
00
sample 1
00
sample 0
ch=r1
00
sample 1
00
sample 0
ch=r2
00
sample 1
00
sample 0
ch=r3
Time Stamp Clear
Event Buffer Clear
Software Trigger
1. Clear the event buffer at the beginning
and after setting the event size! All
events stored are lost!
2. Clear the read state machine in case of
unexpected data from the event buffer - no
events are lost!
© V. Angelov
Event Id
0
r6
adc_mask
read-only
3
. . .
00
sample 1
00
sample 0
ch=r<n-1>
00
sample 3
00
sample 2
ch=r0
. . .
IKP Uni-Köln 05.08.2013
15
OPERATION
Presamples
Event size
Trigger
Busy
event stored
ADC
Presamples: 10 bit register at 0x1000E,
automatically wrapped to ensure the
trigger is inside the event.
Start value 8
EventSize
Register
0
1
2
3
4
5
6
7
© V. Angelov
Number of
Samples
16
32
64
128
256
512
1024
2048
Number of Events
in the Buffer
512
256
128
64
32
16
8
4
IKP Uni-Köln 05.08.2013
16
Dual MALU
• 32 inputs, NIM or TTL (selectable at each
input)
• Two logical groups consisting of user
programmable subset of the 32 inputs
• In each group:
• Delay gate generators at each input
(100 MHz)
• Four outputs
• 3 of them just discriminators with
programmable thresholds
• one implemented as pattern checker
• Counters at each input and output for
debugging
© V. Angelov
IKP Uni-Köln 05.08.2013
17
Block Diagram
MALU
8 x SU704
32
INPUTS
TTL
32
WIDTH
DELAYS
DOWNSCALE
OR_MASK
THRESHOLDS
TTL
EDGE_R
NIM
32
NIM
EDGE_L
INP_NIM
INP_INV
DIS1R
DISCR2
DIS2R
DISCR3
DIS3R
DISCR4
DIS4R
DISCR1
DIS1L
DISCR2
DIS2L
DISCR3
DIS3L
DISCR4
DIS4L
EDGE_C
SOFT_P
INP_DIS_R
INP_DIS_L
INP_DIS_C
MALU
32
IN
DIS1..4R
OUTPUTS
DISCR1
IN
INP_SHAPER
4
WIDTH
DELAYS
DOWNSCALE
OR_MASK
THRESHOLDS
DIS1..4L
4
32 counters
DATA
32
32
Count
ICNT0..31
ADDR
5
Configuration
USB Controller
8 counters
DIS1..4R
4
DATA
DIS1..4L
32
Count
4
ADDR
3
DCNT 1..4R, 1..4L
31
CNT_CTRL
31
TMAX
© V. Angelov
0
x
C C E
T C
CT - clear timer, CC - clear counters, E - enable
Note: clear commands are automatically
deactivated after 1 clock period
0
max time for counting in 10 ns steps, write 0 for continuous
IKP Uni-Köln 05.08.2013
18
Input edge detection and mask
EDGE_I[i]
used for the fron LEDs
32 channels, i=0..31
SOFT_P[i]
OR2
AND2
D
Q
EDGE_R[i]
right group
TTL[i]
D
Q
CLK
MUX
INP_DIS_R[i]
CLK
0
AND2
Input DFF
1
AND2
NIM[i ]
D
Q
D
Q
EDGE_L[i ]
left group
INP_NIM[i]
CLK
INP_DIS_L[i]
CLK
Input DFF
D
XOR2
Q
CLK
INP_INV[i]
AND2
D
Q
EDGE_C[i]
counters
31
0
INP_INV
31
0
INP_NIM
INP_DIS_C[i]
Note: this is not exactly the real design
Select the NIM input when 1
31
0
INP_DIS_R
31
Disable the channel in the right group when 1
0
INP_DIS_L
31
Disable the channel in the left group when 1
0
INP_DIS_C
31
SOFT_P
CLK
Invert input when 1
Disable the channel in the counter group when 1
0
Send a pulse by software (writing 1 to the corresponding bit(s) in this register)
Note the bits in SOFT_P are automatically cleared 1 clock period after activating
© V. Angelov
IKP Uni-Köln 05.08.2013
19
DGG, Discriminator & Pattern
Cheker
COMPARATOR 1
DOWN COUNTER 1
=0
Delay-Gate
Generators
DISCR1
DISCR1
modulo
DOWNSC1[15..0]
THRESH1[4..0]
DISCR2
COMPARATOR 2
DOWN COUNTER 2
OR_MASK1
AND2
DG
SUM
IN[31..0]
32
6
=0
DISCR2
modulo
DOWNSC2[15..0]
THRESH2[4..0]
OR_MASK2
WIDTH[7..0]
OR4
AND2
DISCR4
OR_MASK3
32 x
DELAY[7..0]
AND2
COMPARATOR 3
DISCR3
DOWN COUNTER 3
DELAY
=0
DISCR3
WIDTH
THRESH3[4..0]
modulo
DOWNSC3[15..0]
Pattern Checker
OR_MASK4
AND2
MUX
0
uses ch0..24 only,
see p.4
PULSER_R/L
IN1
1
IN2
PATT_TRG
31
16 15
0
31
IN3
16 15
0
DG1
PWIDTH
RESERVED
31
OR
MASK
L
OR
MASK
R
WIDTH_L
WIDTH_R
DWNSC12_L/R
DOWNSC2
DOWNSC1
DG2
16 15
0
31
16 15
0
DG3
DELAY
4*n..4n+3
DELAY[4*n+3]
DELAY[4*n+2]
DELAY[4*n+1]
DELAY[4*n]
DWNSC3T_L/R
THRESH3
n=0..7
THRESH2
THRESH1
DOWNSC3
SUM
PATT_TRG
© V. Angelov
IKP Uni-Köln 05.08.2013
20
Pattern Cheker
0
1
2
3
4
5
9
10
14
15
19
20
24
25 Terms
AND any of
then OR all together
© V. Angelov
Pattern Checker
IKP Uni-Köln 05.08.2013
21
TDC
Based on DL709 + 2 x SU704 (5xNIM/TTL)
- 7 channels (start 0..6) and stop, TTL/NIM
- 2.5 ns resolution
- Event builder with timestamp
- Multievent buffering
- USB2.0 readout, C, C++ or LabView (Windows)
© V. Angelov
IKP Uni-Köln 05.08.2013
22
DL711
As DL709 +
- Spartan 6 FPGA XC6SLX150t with SerDes
- Two SFPs
- DRAM
- SDCARD slot
- Interface (now USB2.0) as mezzanine card
- 8 slots for SUbmodule Cards
© V. Angelov
IKP Uni-Köln 05.08.2013
23
SU735
LTC2261 or
compatible
LVDS or
LVCMOS
A
SE/DIff IN
to
Diff OUT
D
very clean
clock
Clock
Cleaner
Si5338
© V. Angelov
Lattice
XO2 FPGA
with boot
flash
LVDS or
LVCMOS
Data Out
SPI
I2C
I2C
diff CLK
Clock In
IKP Uni-Köln 05.08.2013
24
SU735 Prototype
© V. Angelov
IKP Uni-Köln 05.08.2013
25
SU735 Ver1
© V. Angelov
IKP Uni-Köln 05.08.2013
26
EW @ PI UNI-HD (2009)
© V. Angelov
IKP Uni-Köln 05.08.2013
27
EW @ PI UNI-HD (2013)
© V. Angelov
IKP Uni-Köln 05.08.2013
28
Thank You
© V. Angelov
IKP Uni-Köln 05.08.2013
29