MICROINSTRUCTION
SEQUENCING
Microprogram Sequencer M.M. Ch-7, Page-232
The basic components of microprogrammed control unit
are the control memory and the circuits that select the
next address.
The task of Microinstruction sequencing is done by
Microprogram sequencer.
The address selection part is called as microprogram
sequencer.
Microprogram sequencer can be constructed with digital
functions to suit a particular application.
Two imp. factors that must be considered while
designing the microinstruction sequencer:
The size of the microinstruction
The address generation time
Input
Logic
MUX 1
SBR
Incrementer
MUX 2
Select
CAR
Control Memory
Microprogram sequencer for a control Mmemory
CAR – Control Address Register
SBR – Subroutine Register
CD – Condition
BR - Branch
The purpose of microprogram sequencer is to present an
address to the control memory so that a microinstruction
may be read and executed.
The next address logic of the sequencer determines the
specific address source to be loaded into the CAR.
The choice of the address source is guided by the next
address information bits that the sequencer receives from
the present microinstruction.
The control memory is included in the diagram to show
the interaction between the sequencer and the memory
attached to it.
There are two multiplexers in the circuit.
The first multiplexer selects an address from one of the
four sources and routes it into the CAR.
The second multiplexer tests the value of a selected
status bit and the result of the test is applied to an input
logic circuit.
The output from CAR provides the address for the control
memory.
The contents of CAR is incremented and applied to one
of the multiplexer inputs and to the SBR.
The other three input come from the address field of the
present microinstruction, from the output of SBR and
from an external source that maps the instruction.
Variables S0 and S1 select one of the source addresses
for CAR.
Variable L enables the load input in SBR.
The CD (condition) field of the microinstruction selects
one of the status bits in the second multiplexer.
If the bit selected is 1, the T (test) variable is equal to 1,
otherwise it is 0.
The T value together with the two bits from the BR
(branch) field go to an input logic circuit.
The Input logic in a particular sequencer determines the
type of operations that are available in the unit.
Typical sequencer operations are: increment, branch
and jump, call and return from subroutine, load an
external address, push or pop the stack, and other
address sequencing operations.
The binary values of the two selection variables
determine the path in the multiplexer. E.g. S1S0 = 10,
mulltiplexer input number 2 is selected and establishes a
transfer path from SBR to CAR.
Orga nisa si K om put e r I I
M ic ro-progra m m e d Cont rol
(K ont rol T e rm ik roprogra m )
Orga nisa si U nit K ont rol
M ic ro-progra m m e d Cont rol
Use sequences of instructions (see earlier
notes) to control complex operations
Called micro-programming or firmware
CON T ROL U N I T M I CROPROGRAM M ED
Terbagi 2 yaitu :
1. Control Vertikal
Jenis implementasi dimana signal kontrol di kode ke dalam pada bit
, kemudian digunakan setelah dikode.
2. Control Horizontal
Control dimana setiap bit kontrol mengatur 1 operasi gate atau
mesin.
KOMPONEN-KOMPONEN POKOK CONTROL UNIT
MICROPROGRAMMED
1. Instruction Register
Menyimpan instruksi register mesin yang dijalankan.
2. Control Store berisi microprogrammed
Untuk semua instruksi mesin.
Untuk startup mesin.
Untuk memprosesan interupt
3. Address Computing Circuiting
Menentukan alamat Control Store dari mikroinstruksi
berikutnya yang akan dijalankan.
4. Microprogrammed Counter
Menyimpan alamat dari mikroinstruksi berikutnya.
5. Microinstruction Buffer
Menyimpan mikroinstruksi tersebut selama dieksekusi.
6. Microinstruction Decoder
Menghasilkan dan mengeluarkan mikroorder yang
didasarkan pada mikroinstruksi dan opcode instruksi
yang akan dijalankan
I m ple m e nt a t ion (1 )
All the control unit does is generate a set of
control signals
Each control signal is on or off
Represent each control signal by a bit
Have a control word for each micro-operation
Have a sequence of control words for each
machine code instruction
Add an address to specify the next microinstruction, depending on conditions
I m ple m e nt a t ion (2 )
Today s large microprocessor
Many instructions and associated register-level
hardware
Many control points to be manipulated
This results in control memory that
Contains a large number of words
co-responding to the number of instructions to be executed
Has a wide word width
Due to the large number of control points to be manipulated
M ic ro-progra m Word Le ngt h
Based on 3 factors
Maximum number of simultaneous micro-operations
supported
The way control information is represented or
encoded
The way in which the next micro-instruction address
is specified
M ic ro-inst ruc t ion T ype s
Each micro-instruction specifies single (or few)
micro-operations to be performed
(vertical micro-programming)
Each micro-instruction specifies many different
micro-operations to be performed in parallel
(horizontal micro-programming)
V e rt ic a l M ic ro-progra m m ing
Width is narrow
n control signals encoded into log2 n bits
Limited ability to express parallelism
Considerable encoding of control information
requires external memory word decoder to
identify the exact control line being manipulated
H orizont a l M ic ro-progra m m ing
Wide memory word
High degree of parallel operations possible
Little encoding of control information
T ypic a l M ic roinst ruc t ion Form a t s
Com prom ise
Divide control signals into disjoint groups
Implement each group as separate field in
memory word
Supports reasonable levels of parallelism
without too much complexity
Orga niza t ion of
Cont rol M e m ory
Cont rol U nit
Cont rol U nit Func t ion
Sequence login unit issues read command
Word specified in control address register is read into
control buffer register
Control buffer register contents generates control
signals and next address information
Sequence login loads new address into control buffer
register based on next address information from control
buffer register and ALU flags
N e x t Addre ss De c ision
Depending on ALU flags and control buffer
register
Get next instruction
Add 1 to control address register
Jump to new routine based on jump microinstruction
Load address field of control buffer register into control
address register
Jump to machine instruction routine
Load control address register based on opcode in IR
Func t ioning of M ic roprogra m m e d
Cont rol U nit
Wilk e s Cont rol
1951
Matrix partially filled with diodes
During cycle, one row activated
Generates signals where diode present
First part of row generates control
Second generates address for next cycle
Wilk e s's M ic roprogra m m e d Cont rol U nit
Adva nt a ge s a nd Disa dva nt a ge s of
M ic roprogra m m ing
Simplifies design of control unit
Cheaper
Less error-prone
Slower
T a sk s Done By M ic roprogra m m e d
Cont rol U nit
Microinstruction sequencing
Microinstruction execution
Must consider both together
De sign Conside ra t ions
Size of microinstructions
Address generation time
Determined by instruction register
Once per cycle, after instruction is fetched
Next sequential address
Common in most designed
Branches
Both conditional and unconditional
Se que nc ing T e c hnique s
Based on current microinstruction, condition
flags, contents of IR, control memory address
must be generated
Based on format of address information
Two address fields
Single address field
Variable format
Bra nc h Cont rol Logic :
T w o Addre ss Fie lds
Bra nc h Cont rol
Logic : Single
Addre ss Fie ld
Bra nc h Cont rol
Logic : V a ria ble
Form a t
Addre ss Ge ne ra t ion
Explicit
Implicit
Two-field
Mapping
Unconditional Branch
Addition
Conditional branch
Residual control
Ex e c ut ion
The cycle is the basic event
Each cycle is made up of two events
Fetch
Determined by generation of microinstruction address
Execute
Ex e c ut e
Effect is to generate control signals
Some control points internal to processor
Rest go to external control bus or other interface
Cont rol U nit
Orga niza t ion
A T a x onom y of M ic roinst ruc t ions
Vertical/horizontal
Packed/unpacked
Hard/soft microprogramming
Direct/indirect encoding
I m prove m e nt s ove r Wilk e s
Wilkes had each bit directly produced a control
signal or directly produced one bit of next
address
More complex address sequencing schemes,
using fewer microinstruction bits, are possible
Require more complex sequencing logic module
Control word bits can be saved by encoding and
subsequently decoding control information
H ow t o Enc ode
K different internal and external control signals
Wilkes s:
K bits dedicated
2K control signals during any instruction cycle
Not all used
Two sources cannot be gated to same destination
Register cannot be source and destination
Only one pattern presented to ALU at a time
Only one pattern presented to external control bus at a time
Require Q < 2K which can be encoded with log2Q < K bits
Not done
As difficult to program as pure decoded (Wilkes) scheme
Requires complex slow control logic module
Compromises
More bits than necessary used
Some combinations that are physically allowable are not possible to
encode
Spe c ific Enc oding T e c hnique s
Microinstruction organized as set of fields
Each field contains code
Activates one or more control signals
Organize format into independent fields
Field depicts set of actions (pattern of control signals)
Actions from different fields can occur simultaneously
Alternative actions that can be specified by a
field are mutually exclusive
Only one action specified for field could occur at a
time
M ic roinst ruc t ion Enc oding
Dire c t Enc oding
M ic roinst ruc t ion Enc oding
I ndire c t Enc oding
I. A taxonomy of Microinstructions
•The microinstruction cycle is the basic event on the micro programmed processor.
.
•Each cycle is made up of two parts: fetch and execute.
.
•Microinstructions can be classified in a variety of ways. Distinctions that are commonly
made in
the literature include the following:
.
a. Vertical/Horizontal
b. Packed/Unpacked
c. Hard/Soft Programming
d. Direct/Indirect encoding
.
•The degree of packing relates to the degree of identification between a given number of
bits
contains more information.
.
•The term Horizontal and Vertical relate to the relative with of microinstructions.
.
•The hard and soft microprogramming are used to suggest the degree of closeness to the
control
signals and hardware layout
.
II. Microinstruction Encoding
.
•The design of an encoded microinstruction format can be stated in simpler terms:
.
a. Organize the format into independent fields.
.
b. Define each field such that the alternative actions that can be specified by the field are
mutually exclusive.
.
III. LSI-11 Microinstruction execution
.
•The LSI-11 is the first member of the PDP-11 family that was offered as a single-board
processor.
.
•The LSI-11 uses an extremely vertical microinstruction format, which is only 22 bits
wide. The
microinstruction set strongly resembles the PDP-11 machine instruction set that it
implements.
.
IV. IBM 3033 microinstruction execution
.
•The standard IBM 3033 control memory consist of 4k words. The first half of these
contains 108bit microinstructions, while the remainder are used to store 126-bit microinstructions.
.
•The ALU operates on inputs from four dedicated, non-user-visible registers A, B, C and
D.
.