A LOW-VOLTAGE TEMPERATURE-STABLE MICROMECHANICAL
PIEZOELECTRIC OSCILLATOR
Reza Abdolvand, Hossein Mirilavasani, and Farrokh Ayazi
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
(Tel: +1 -404-894-9496, E-mail: rezaagece.gatech.edu)
Abstract: We present a low-power 82MHz reference oscillator that utilizes a temperature-stable thinfilm piezoelectric-on-silicon resonator as the frequency-selective element.
Low impedance
micromachined resonators are designed and fabricated using an arraying technique. As a result, the
transimpedance amplifier in the oscillator loop is reduced to a single active component (one transistor)
and 3 resistors, which is very power-efficient (2.2mW at l1lV supply). By employing the buried oxide
layer of the SOI substrate as a part of the structural stack of the composite resonator, a very small (
2ppmr/C) temperature coefficient of frequency (TCF) is obtained for the oscillator.
Keywords: reference oscillator, temperature-stable, piezoelectric, arraying technique.
1. INTRODUCTION
The realization of micromachined high-Q
frequency-selective components for use in
temperature-stable, low-phase noise oscillators
has been an active research area for more than a
decade. Significant progress has been made in
developing oscillators that utilize siliconmicromachined capacitive resonators with Q
values comparable to that of a quartz resonator [1,
2]. However, capacitive resonators require
relatively high DC polarization voltages (5-20V)
for operation, which complicates the design of the
oscillator circuit in today's low-voltage CMOS
processes. Moreover, the motional impedance of
capacitive resonators is much larger than that of a
quartz resonator, and their power handling is
lower. These resonators are usually operated at
low pressures (mTorr regime), which makes their
packaging process costly and challenging. Also,
the temperature compensation techniques
demonstrated so far lose efficiency at high
frequencies.
The thin-film piezoelectric-on-substrate (TPoS)
resCoato r technology introduced in our group [3]
has the potential to address some of the issues
mentioned above. This technology enables lowimpedance
high-frequency
resonators
with
and good linearity.
TPoS resonators do not require vacuum packages
and most importantly no bias voltage is necessary
relatively high quality factors
for their operation,
which
is
a
feature considering the low operating voltage of
the current integrated circuits.
In this work, we introduce an arraying
technique for TPoS resonators that can
deterministically reduce their motional impedance
to less than 1OOQ and effectively suppress the
spurious resonance modes. The temperature
coefficient of frequency (TCF) of TPoS resonators
is also significantly reduced by incorporating the
buried oxide layer of the SOI substrate in the
resonator structure. The oxide layer provides a
passive temperature compensation mechanism
enabling near-zero-TCF devices, provided the
thickness of the layers in the composite stack is
adequately controlled. These low-impedance
temperature-stable resonators are then utilized in a
very simple (single transistor), low-voltage and
low-power oscillator circuit and the oscillator
performance is reported.
2. RESONATOR DESIGN
The high-order lateral bulk acoustic mode of a
piezoelectric-on-substrate structure can be excited
hy matching the pattern 01f the metallic electrodes
with the periodic polarity of the strain field on the
surface of the resonator as shown in Fig. l.a [4].
Although the motional impedance of the highorder TPoS resonators are improved, increasing
the resonance order to enable very low-impedance
values gives rise to some issues.
very attractive
53
-4244-0842-3/07/$20.00c2007 IEEE
Fig. I Schematic viewgraphs of (a) a third-order
and (b) a two-resonator coupled array TPoS
resonator.
The wide freestanding resonant structures
supported by small beams at nodal points (Fig. I a)
are not constrained enough to suppress excitation
of unwanted resonance modes. Increasing the
dimension of the plate raises the number of
spurious modes that are coupled strong enough to
be excited.
In order to solve this problem, a coupled array
of individual resonators is used in this work (Fig.
I.b). Each of these resonators is supported with a
separate set of support beams, which improves the
rigidity of the resonant structure and consequently
suppresses the vibration amplitude of the spurious
modes. The motional impedance of the resulted
coupled array resonator should ideally be
inversely proportional to the number of resonators
existed in the array.
The important modification relative to the
process described in [3] is the release step where
the SOI buried oxide (BOX) layer is etched from
the top in an inductive coupled plasma etcher
using the same mask layer that defines the device
structure (mask 4) . This way the BOX layer
attached to the resonant structure is optionally
kept intact in order to improve the temperature
stability of the resonator.
4. MESUREMENT RESULTS
Top-view optical viewgraphs of a third-order
device and an arrayed device consisting of four
resonators are shown in Fig. 3. These devices are
fabricated on 5pm thick SOI substrate and the
BOX layer is removed from the backside. The
center-to-center top electrode pitch size for all of
the devices discussed in this work is 40tm. The
test set-up consists of a Suss high-frequency probe
station, cascade GSG micro-probes, and an
Agilent E8364B network analyzer. A measured
wide-span (50MHz) frequency response of a thirdorder resonator and a 12-resonator coupled array
device is shown in Fig. 4 and Fig. 5, respectively.
3. FABRICATION PROCESS
The process flow is briefly described in Fig. 2.
Begin with an SOi substrate, 26gtm thick device layer
Evaporate and pattern Goid
(Maski). Sputter 0.5gtm ZnO.
Evaporate and pattern
Fig. 3 Optical viewgraphs of (a) a third-order and
(b) four-resonator coupled array TPoS resonators.
aluminum (Mask2)
Pattern ZnO to access bottom
electrodes (Mask3)
Etch ZnO, pattern device
structure in silicon (Mask4)
Etch silicon from the backside
(Ma k5) and the buried oxide
from the top (release).
LII Metal
d Silicon
Oxide
ZnO
Fig. 4 Wide-span (5OMHz) frequency response
plot of a third-order TPoS resonator
Fig. 2 Schematic diagram of the process flow
54
-4244-0842-3/07/$20.00c2007 IEEE
resonator with excitation source power ranging
from -5dBm to 1 5dBm. The I dB compression
point is measured to be at l5dBm. For the 12resonator device, the power handling is
significantly improved, showing only 0.2 dB
compression at 1 5dBm of input power, as
illustrated in Fig. 8.
8{,,,.............................,.............
-10
94.7 MHz
2000
Fig. 5 Wide-span (50MHz) frequency response
plot of a typical 12-resonator coupled array.
-0
x, a,,
-0dBm
-15
a
5 dBm
O1 0dBm
-20
15 dBm
cn _25
Unlike the third-order device the frequency
response of the coupled array is spurious-free in
50MHz vicinity of the primary resonance peak.
Measured frequency responses of arrayed devices
with 4, 6, and 12 resonators located on the same
die of the processed wafer are shown in Fig. 6.
-30
-35
94.7
95
95.1
94.9
Frequency (MHz)
94.8
95.2
95.3
Fig. 7 Linearity of a third-order TPoS resonator
-5
4-resonator
0
alrlray
5
-10
12-resonator
---------
--
arlray
-15 dBm
-10
-~~~~
~ ~~
~
~
~
15 dB
~
--15
u)
-20
-25
-40
-45
,
30
-
94.2
-50
95.5
96
96.5
97
97.5
Frequency (MllHz)
The :motional i:mpedlances are ~550Q for t:he 4resonator, 21 0f2 fo:r the 6-resonato:r and 111 0:)2 for
t:he 12 -resonator array. The predlicted inverse
lproportionality of t:he :motional imlpedlance with
the number of resonators in the array holds with
goudr precisior n fr th tWu rgetr
la
devics.
Thesern
results confirm tha tthe motional impedance of the
coupledL array device can be systematically
1
a
Tepwr hndln of th arae dvcs is
aso improved, since te actuation area can be
ifncrae
94.7
94.8
5. OSCILLATOR DESIGN
Fig 6 Frequency reponse of 4, 6, and 12
resonator coupled arrays.
r
94.4
94.5
94.6
Frequency (MHz)
Fig. 8 Linearity of a 12-resonator coupled array
TPoS resonator
-55
-60
95
94.3
7: shows thel
siniianl
Fiur
reco d frequency response of te trd-order
The resonators developed in this work are
suitable for oscillator applications. The low
motional impedance of the resonator reduces the
number of required gain stages to sustain
oscillation. The excellent power handling of these
devices improves the far-from-carrier phase noise
of the oscillator and eliminates the need for an
automatic level control circuit to operate the
resonator in the linear region [2]. In addition,
these resonators are free of spurious modes,
eliminating the possibility of locking to an
undesired mode.
In order to sustain oscillation, the amplifier
should create 180 degrees of phase shift, since the
5,
-4244-0842-3/07/$20.00c2007 IEEE
shown in Fig 1 1
output signal of the resonator is 180 degrees outof-phase relative to the input signal. Coupled array
resonators fabricated on a 2ptm thick S0I substrate
are utilized in the oscillator. The resonance
frequency of these devices is reduced to -82MHz
(compared to the presented -95MHz devices)
because of the lower acoustic velocity of the
2jtm BOX layer incorporated in the structure.
The TIA is compromised of a single NPN
transistor in common-emitter configuration (Fig.
9). An Emitter degeneration resistor is used to
improve the linearly while maintaining sufficient
voltage headroom for oscillation. The feedback
resistor eliminates the need for separate biasing
network and improves the overall phase-noise
performance of the oscillator.
81.954
-2ppm/0C
81.952
N
81.95
>%
81.948
U
-\-
aD 81.946
C:r
2 81.944
81.942
81.94
20
40
60
80
Temperature (degrees C)
Fig. 11 Measured TCF plot of the oscillator
6. CONCLUSION
_7
hmZ±
In this paper, coupled array of TPoS resonators
are introduced, which offer significantly improved
motional impedance and power handling with
suppressed spurious resonance modes. A passive
is
temperature
compensation
technique
implemented by incorporating the buried oxide
layer of the SOI substrate in the stack of resonant
structure. The resulted low-impedance devices are
utilized in a single transistor low-voltage and lowpower oscillator circuit with remarkable far-from
carrier phase noise of -137dBc/Hz and -2ppm/0C
temperature coefficient of frequency.
Fig. 9 Schematic circuit diagram and output
waveform of the single-transistor oscillator
The phase noise of the oscillator is shown in
Fig. 10 (after buffering the output signal). The
phase noise is measured using an E5500 Agilent
phase noise analyzer. A close-to-carrier phase
noise of -72dBc/Hz at 1kHz offset and a phase
noise floor of -137dBc/Hz are measured for the
oscillator.
REFERENCES
[1] K. Sundaresan, G. K. Ho, S. Pourkamali, F.
Ayazi, "A low phase noise 100MHz silicon BAW
reference oscillator," IEEE Custom Integrated
AFi.
Ce1
1M3 n2
bue6d07
Circuits, Sept. 2006, pp. 841 -844A.
[2] Y. Lin, S. Lee, S-S Li, Y. Xie, Z. Ren, C.T.-C.
5OE-----------< - ----------------------- -----------------Nguyen, "Series-resonant VHF micromechanical
resonator reference oscillators," IEEE Journal of
Solid-State Circuits, Vol.39, Dec. 2004, pp. 247713t
----~~~~~~~~~~~~~~~~~----------2491.
[3] S. Humad, R. Abdolvand, G. K. Ho, G. Piazza,
-1
F.
environmental
chamber
and the resulted plot isr S Ayazi, "High frequency micromechanical piezodE
-S -m
130
on-silicon block resonators," Technical Digest.
IEDM'03, pp. 39.3.1- 39.3.4, 8-10 Dec. 2003
[4] G K. Ho, R. Abdolvand, and F. Ayazi, "High
order composite bulk acoustic resonators, Proc.
/lAIU
[dB I lz]
fL
HzU
WIIVIl\JIIIllV2lItAI~~~~~~~~~~~~~(f
20th IEEE International Conterence on Micro
Electro Mechanical Systems (MEMS 2007),
Kobe, Japan, Jan. 2007, pp. 791 794.
SIE+6 H
2 Nov 2006
30
14
---
----------
--
-3
--
--
15
------------------~
-
~~~~
,1
---------
-
------
-I-
U
lI vs
l
6
-4244-0842-3/07/$20.00c2007 IEEE