Course AE0B38APH - FPGA Application
1) numbers, characters, strings
2) basic data types, operators
Lecture topic 3,4
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Numbers in VHDL
Default number representation – decimal system
There are two types of literals:
Integer (examples: 12 3 10E6 1e2 ) without decimal
point
Real (examples: 1.2 25.1 3.14e-2) with decimal point
Negative numbers (for example : -5) –
combination of a negation operator and an integer
literal !
To express a number in a base different from
base „10“ - it must be used
base#number#
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Numbers in VHDL
Examples:
base 2 : 2#001001# dec. 9
base16 : 16#10#
dec. 16
For improving the readability of large numbers:
put underscores in number
2#0010_0010_1110_0000_1122#
236_789
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Characters, Strings and Bit-strings
A character literal in VHDL code: put a single
quotation mark (examples: ‘a’, ‘H’, ‘,’)
A string of characters: double quotation mark
(examples: ”I am string”, “H”, “,”)
A bit string represents a sequence of bit values:
(examples: B”110011_110011”
X”A0FF0C”
O”123” )
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Predefined data types
Data types defined in Package of the std library
bit
- values ‘0’ ‘1’ (constant A:bit:=1;)
bit_vector - array with each element of type bit
(signal IN:bit_vector( 8 downto 0); )
Boolean - values FALSE,TRUE
(variable TEST: boolean:=FALSE; )
character –any legal VHDL character
(variable chr: character :=’Y’; )
interger – range is implementation dependent, but include at
least –(231 -1) to + (231 -1)
(constant CONST1: integer :=129; )
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Predefined data types
Data types defined in Package of the std library:
natural - integer starting with 0 up to the max specified in
the implementation
(variable VAR1: natural :=2;)
positive - integer starting from 1 up the max specified in the
implementation
(variable VAR2: positive :=2;)
real – floating point number in the range of –1.0 x 1038 to
+1.0x 1038 (can be implementation dependent)
(variable VAR3: real :=+64.2E12;)
string – array of which each element is of the type character
(variable VAR4: string(1 to 6):= “@$#ABC”;)
time - an integer number of which the range is
implementation defined; units can be expressed in sec, ms, us,
ns, ps, fs, min and hr.
(variable DELAY: time :=5 ns;)
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Package STD
For using all types above, the VHDL code must
includes following lines:
library std;
use std.standard.all;
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User-defined types
syntax:
type identifier is type_definition;
examples:
type small_int is range 0 to 1024;
type my_word_length is range 31 downto 0;
subtype data_word is my_word_length range 7 downto 0;
subtype int_small is integer range -1024 to +1024;
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Declaration of package
Package can be used for declaration of “my_data_types”
examples:
package my_types is
type small_int is range 0 to 1024;
type my_word_length is range 31 downto 0;
subtype data_word is my_word_length is range 7
downto 0;
type cmos_level is range 0.0 to 3.3;
end package my_types;
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Enumerated types
syntax:
type type_name is (identifier list or character literal);
examples:
type my_3values is (‘0’, ‘1’, ‘Z’);
type PC_OPER is (load, store, add, sub, div, mult, shiftl,
shiftr);
type hex_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, 8’, ‘9’, ‘A’,
‘B’, ‘C’, ‘D’, ‘E’, ‘F’);
type state_type is (S0, S1, S2, S3);
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Package std_logic_1164
Contains definition of enumerated type of std_ulogic
type STD_ULOGIC is (
‘U’,
-- uninitialized
‘X’,
-- forcing unknown
‘0’,
-- forcing 0
‘1’,
-- forcing 1
‘Z’,
-- high impedance
‘W’,
-- weak unknown
‘L’,
-- weak 0
‘H’.
-- weak 1
‘-‘);
-- don’t care
For using all types above, the VHDL code must includes following
lines:
library ieee;
use ieee.std_logic_1164.all;
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Array and record type
Composite data object consist of a collection of
related data elements in the form an array or record
syntax for array definition:
type array_name is array (indexing scheme) of
element_type;
type MY_WORD is array (15 downto 0) of std_logic;
type YOUR_WORD is array (0 to 15) of std_logic;
type VAR is array (0 to 7) of integer;
type STD_LOGIC_1D is array (std_ulogic) of
std_logic;
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Multidimensional array
type MY_MATRIX3X2 is array (1 to 4, 1 to 2) of
natural;
type YOUR_MATRIX4X2 is array (1 to 3, 1 to 2) of
integer;
type STD_LOGIC_2D is array (std_ulogic, std_ulogic)
of std_logic;
Application of MY_MATRIX data types:
variable DATA_ARR: MY_MATRIX :=((0,2), (1,3), (4,6),
(5,7));
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Unconstrained array type
syntax:
type array_name is array (type range <>) of
element_type;
examples:
type MATRIX is array (integer range <>) of integer;
type VECTOR_INT is array (natural range <>) of
integer;
type VECTOR2 is array (natural range <>, natural range
<>) of std_logic;
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Record Type
syntax:
type name is
record
identifier :subtype_indication;
:
identifier :subtype_indication;
end record;
Example:
type MY_MODULE is
record
RISE_TIME :time;
FALL_TIME : time;
SIZE
: integer range 0 to 200;
DATA
: bit_vector (15 downto 0);
end record;
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Type conversions
VDHL is a strongly typed language – it is not possible to
assign a value of one data type to a signal of a different data
types !!!
For example package std_logic_1164 allows the following
conversions:
function to_bit(arg: std_ulogic) ret. to_bit
function to_bitvector(arg: std_logic_vector) ret. bit_vector
function to_bitvector(arg: std_ulogic_vector) ret. to bit_vector
function to_StdULogic(arg: bit) ret. std_ulogic
function to_StdLogicVector(arg: bit_vector) ret. std_logic_vector
function To_StdUlogicVector(arg: bit_vector) ret. std_logic_vector
function To_StdLogicVector(arg: std_ulogic) ret. std_logic_vector
function To_StdUlogicVector(arg: std_logic) ret. std_ulogic_vector
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Type conversions - package std_logic_arith
function CONV_INTEGER(ARG:
function CONV_INTEGER(ARG:
function CONV_INTEGER(ARG:
function CONV_INTEGER(ARG:
INTEGER) ret. INTEGER;
UNSIGNED) ret. INTEGER;
SIGNED) ret. INTEGER;
STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG:
function CONV_UNSIGNED(ARG:
function CONV_UNSIGNED(ARG:
function CONV_UNSIGNED(ARG:
function CONV_SIGNED(ARG:
function CONV_SIGNED(ARG:
function CONV_SIGNED(ARG:
function CONV_SIGNED(ARG:
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INTEGER; SIZE: INTEGER) ret. UNSIGNED;
UNSIGNED; SIZE: INTEGER) ret. UNSIGNED;
SIGNED; SIZE: INTEGER) ret. UNSIGNED;
STD_ULOGIC; SIZE: INTEGER) ret. UNSIGNED;
INTEGER; SIZE: INTEGER) ret. SIGNED;
UNSIGNED; SIZE: INTEGER) ret. SIGNED;
SIGNED; SIZE: INTEGER) ret. SIGNED;
STD_ULOGIC; SIZE: INTEGER) ret. SIGNED;
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Type conversions - package std_logic_arith
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
ret. STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE:
INTEGER) ret. STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
ret. STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE:
INTEGER) ret. STD_LOGIC_VECTOR;
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Operators
Logical
Relation
Shift
Addition
Unary
Multiplying
Miscellaneous
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Logical operators
and, or, nand, nor, xor, xnor
Defined for bit, bolean, std_logic and std_ulogic
Can be applied to signals, variables and constants
NAND and NOR are not associative
X nand Y nand Z - bad syntax
(X nand Y) nand Z - correct syntax
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Relational operators
=
/=
<
<=
>
<=
equlity (for any types)
inequality (for any types)
small than (for scalar, dicrete array types)
small than or equal (for scalar, dicrete array types)
greater than (for scalar, dicrete array types)
greater than or equal (for scalar, dicrete array
types)
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Examples of using relational operators
variable STS
: Boolean;
constant A
: integer :=24;
constant B_COUNT
: integer :=32;
constant C
: integer :=14;
STS <= (A < B_COUNT) ; -- will assign the value
“TRUE” to STS
STS <= ((A >= B_COUNT) or (A > C)); -- will result in
“TRUE”
STS <= (std_logic (‘1’, ‘0’, ‘1’) < std_logic(‘0’, ‘1’,’1’));-makes STS “FALSE”
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Shift operators
SLL - Shift left logical (fill right vacated bits with
the 0)
SRL - Shift right logical (fill left vacated bits with 0)
SLA - Shift left arithmetic (fill right vacated bits
with rightmost bit)
SRA - Shift right arithmetic (fill left vacated bits
with leftmost bit)
ROL - Rotate left (circular)
ROR - Rotate right (circular)
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Examples of using shift operators
variable A: bit_vector :=”101001”;
A sll 2
A srl 2
A sla 2
A sra 2
A rol 2
A ror 2
results in
results in
results in
results in
results in
results in
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“100100”
“001010”
“100111”
“111010”
“100110”
“011010”
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Addition operators
+ addition
- substraction
& concatenation
Examples :
signal MYBUS
:std_logic_vector (15 downto 0);
signal STATUS
:std_logic_vector (2 downto 0);
signal RW, CS1, CS2 :std_logic;
signal MDATA
:std_logic_vector ( 0 to 9);
MYBUS <= STATUS & RW & CS1 & CS2 & MDATA;
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Unary operators
They are used to specify the sign of a numeric type
+ identity
- negation
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Multiplying operators
Perform mathematical functions on numeric types (integer
or floating point)
*
/
mod
rem
- multiplication
- division
- modulus
- remainder
A rem B is the same as A –(A/B)*B (in which A/B in an
integer)
A mod B = is the same as A – B * N (in which N is an
integer)
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Miscellaneous operators
** - exponetiation (any numeric type)
abs – absolute value (any numeric type)
not – logical negation (any bit or boolean type)
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Any questions
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