Binary to BCD
10/3/08
Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BCD
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
Dec
0
1
2
3
4
5
6
7
8
9
16 = 10 + 6
17 = 11 + 6
18 = 12 + 6
19 = 13 + 6
20 = 14 + 6
21 = 15 + 6
We will now present, without proof, an
algorithm for converting binary to BCD.
1
Algorithm for converting N-bit binary number to BCD:
1.
2.
3.
4.
5.
6.
7.
Set up a Result Shift Register (RSR) and a Binary Shift Register (BSR).
Clear the RSR and load Binary value into BSR. Set count to 1.
Shift most significant bit (MSB) of BSR into least significant bit (LSB) of RSR.
If cont = N then exit else:
Check each BCD digit of RSR. For BCD digits  5 add 3 to that digit.
Increment count.
Go to step 3.
Example: Consider 0FFH = 255. Let N = 12.
Count
RSR
BSR
1
0000 0000 0000 0000 1111
0000 0000 0000 0001 1111
0000 0000 0000 0001 1111
2
0000 0000 0000 0011 1111
0000 0000 0000 0011 1111
3
0000 0000 0000 0111 1111
0000 0000 0000 0111 1111
4
0000 0000 0000 1111 1111
0000 0000 0000 1111 1111
5
0000 0000 0001 1111 1110000 0000 0001 1111 1116
0000 0000 0011 1111 11-0000 0000 0011 1111 11-7
0000 0000 0111 1111 1--0000 0000 0011
1111 1--1111 ---8
1111
11111111-11-1--1------------------------------
10
111- ---- ---111- ---- ---11-- ---- ----
11
11-- ---- ---1--- ---- ----
12
1--- ---- ------- ---- ----
9
Step
2
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
2
Algorithm for converting N-bit binary number to BCD:
1. Set up a Result Shift Register (RSR) and a Binary Shift Register (BSR).
2. Clear the RSR and load Binary value into BSR. Set count to 1.
3. Shift most significant bit (MSB) of BSR into least significant bit (LSB) of RSR.
4. If cont = N then exit else:
5. Check each BCD digit of RSR. For BCD digits  5 add 3 to that digit.
6. Increment count.
7. Go to step 3.
Example: Consider 0FFH = 255. Let N = 12.
Count
RSR
BSR
1
0000 0000 0000 0000 1111
0000 0000 0000 0001 1111
0000 0000 0000 0001 1111
2
0000 0000 0000 0011 1111
0000 0000 0000 0011 1111
3
0000 0000 0000 0111 1111
0000 0000 0000 0111 1111
4
0000 0000 0000 1111 1111
0000 0000 0000 1111 1111
5
0000 0000 0001 1111 1110000 0000 0001 1111 1116
0000 0000 0011 1111 11-0000 0000 0011 1111 11-7
0000 0000 0111 1111 1--0000 0000 0011
0000 0000 1010 1111 1--8
0000 0001 0101 1111 ---0000 0000 0011
0000 0001 1000
9
0000 0011 0001 111- ---0000 0011 0001 111- ---10
0000 0110 0011 11-- ---0000 0011 0000
0000 1001 0011 11-- ---11
0001 0010 0111 1--- ---0000 0000 0011
0001 0010 1010 1--- ---12
0010 0101 0101 ---- ----
1111
11111111-11-1--1------------------------------
----------------------
Step
2
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
5 – add 3 if  5
3 - Shift
3
Func_to_BCD
Using the above algorithm write the function to_bcd that converts a 16 bit unsigned binary value to BCD.
-- func_to_bcd.vcd V 1.2 10/12/07
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package func_to_bcd is
function to_bcd (binary: std_logic_vector) return std_logic_vector;
end func_to_bcd;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package body func_to_bcd is
------------------------------------------------------------------------Function: to_bcd - Converts 16 bit input to BCD. If input > 9999 then
-returns x"9999".
-- Input: binary - 16 bit unsigned value.
-- Returns: BCD unsigned.
-- Ussage: BCD = to_bcd(binary);
----------------------------------------------------------------------function to_bcd(binary: std_logic_vector) return STD_LOGIC_VECTOR is
variable rsr : std_logic_vector(15 downto 0); -- Shift reg for BCD result
begin
if CONV_INTEGER(binary) > 9999 then
rsr := x"9999";
else
-- Enter your code to complete this function
end if;
return rsr;
end to_bcd;
end func_to_bcd;
4
-- tb_to_bcd.vhd Version 1.1 by Dr. Jerry H. Tucker
-- Test bench for to_bcd.vhd
-- Created 10/12/07
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
use func_to_bcd.all;
-- uses to_bcd in package func_to_bcd.vhd
entity tb is
end tb;
architecture test of tb is
signal bi, bcd: std_logic_vector(15 downto 0) := x"ffff";
signal int: integer;
begin
-- Use linear feedback shift register to
-- generate random binary values.
bi <= (bi(5) xor bi(3) xor bi(2) xor bi(0)) &bi(15 downto 1) after 5 ns;
int <= conv_integer(bi); -- Get integer value of binary
bcd <= to_bcd(bi);
end test;
5
6
Divide by 3
x
x
1
1 1 1


x
 x   2  3  ... 
3 4 1
4 1
4 4 4

Algorithm:
1. Sum = 0
2. P = x
3. If P = 0 then exit
4. P = P/4
5. Sum = Sum + P
6. GOTO 3
Example 256/3 = 85 or 0101 0101 X = 100000000
P
100000000
00100000
00001000
00000010
00000000
Sum
00000000
00100000
00101000
00101010
00101010
7
Homework #10
Due Wednesday 10/8/08
For this homework you and your lab partner may work together and turn in a joint
solution. Do not discuss the homework with anyone else other than the instructor.
The file pkg_func.vhd is provided. You are to complete the functions in this
package and develop a separate test bench for each function. Turn in all source
code and simulation waveforms. For each problem write a short paragraph
describing how you concluded from the test bench that the function was working
correctly. Do not turn in solutions that do not compile.
1. Using the algorithm we developed in class, complete the function to_bcd and
develop a test ench. Assume the input and returned value are both 16 bits.
2. Using an algorithm you developed, complete the function log2 and develop a
test ench. Write a short paragraph describing your algorithm. Assume the
input is 16 bits, and the returned value is 8 bits. Return the integer of log base
2 of the input, unless log base 2 is negative then return 0.
3. Using the algorithm we developed in class, complete the function div_by_3
and develop a test ench. The function must work for all input lengths greater
than 2. assume the return length is the same as the input length.
Hint: You may need the use some of the arithmetic conversions shown
below.
slv_1 <= CONV_STD_LOGIC_VECTOR(n, 3);
u_1 <= CONV_UNSIGNED(n, 3);
s_1 <= CONV_SIGNED(n, 3);
i_1 <= CONV_INTEGER(slv);
8
------------------------------------------------------------------------Function: to_bcd - Converts 16 bit input to BCD.
-- If input > 9999 then returns x"9999".
-- Input: binary - 16 bit unsigned value.
-- Returns: BCD unsigned.
-- Ussage: BCD <= to_bcd(binary);
----------------------------------------------------------------------function to_bcd(binary: std_logic_vector) return STD_LOGIC_VECTOR is
variable rsr : std_logic_vector(15 downto 0); -- Shift reg for BCD result
variable bsr : std_logic_vector(15 downto 0); -- Shift reg for binary input
variable correction : std_logic_vector(15 downto 0); -- Add to do BCD correction
begin
if CONV_INTEGER(binary) > 9999 then
rsr := x"9999";
else
-- Enter your code here
end if;
return rsr;
end;
9
--------------------------------------------------------------- Function: LOG2 - Returns integer of 16 bit input unless LOG2
-is negative then 0 is returned.
-- Inputs: x - a 16 bit std_logic_vector
-- Returns: 8 bit std_logic_vector containg integer of log base 2
-- Ussage: log <= Log2(X);
---------------------------------------------------------------function log2(x: std_logic_vector) return std_logic_vector is
variable log: std_logic_vector(7 downto 0);
begin
-- Enter your code here
return(log);
end;
10
---------------------------------------------------------------- Function: Div_by_3 - Divides input by 3
-- Inputs: X - a std_logic_vector
-- Returns: a std_logic_vector
-- Note that both standart logic vectors must be of the form
-- std_logic_vector(n downto 0), and n is the same for
-- both the input and the output.
-- Do not make assumptions about the value of n.
-- The function must work for any n > 2.
---------------------------------------------------------------function Div_by_3(x: std_logic_vector) return std_logic_vector is
variable Sum, P: std_logic_vector(x'length - 1 downto 0);
begin
-- Enter your code here
return(Sum);
end;
end pkg_func;
11