Significant improvement of the performance of ZnO nanowire field-effect transistor by
annealing SiO2 gate dielectrics in forming atmosphere
Haolei Qian, Yewu Wang*, Yanjun Fang, Lin Gu, Ren Lu, and Jian Sha*
Department of Physics & State Key Laboratory of Silicon Materials, Zhejiang University, Hangzhou 310027, P.
R. China
Supporting Information
FIG.S1. The drain current-gate voltage (Ids-Vg) transfer curves for all fabricated U-FETs.
*
Corresponding authors. Email: yewuwang@zju.edu.cn and phyjsha@zju.edu.cn
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FIG.S2. The drain current-gate voltage (Ids-Vg) transfer curves for all fabricated H-FETs.
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U-FET
H-FET
SS(V/Dec)
10
1
100
200
300
400
Diameter(nm)
FIG.S3. The sub-threshold swing Vs ZnO nanowire diameter plots of U-FETs and H-FETs.
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