Chapter 9
Input/Output
9.1
(BL1+) Without interrupt capability, the system would have no practical way of determining when
a DMA transfer is complete, thus no way of knowing when it is safe to proceed with processing of
the data used in the transfer.
9.2
(BL1+) The use of a separate disk controller frees the CPU to perform other tasks. In particular, the
disk controller can manage DMA transfers, which otherwise would have to be done by the CPU.
The disk controller also manages the movement of the disk head and reading or writing of the data
on the disk. Again, without the disk controller, the CPU would be forced to perform these
operations.
9.3
(BL1+) DMA is rarely used with computer terminals because the amount and rate of data transfer
is too little to justify the effort. It takes several instructions to initiate a DMA transfer, whereas a
single piece of data can be transferred from the keyboard to the CPU using one programmed I/O
instruction. Furthermore, it is desirable in many cases to accept keystrokes one at a time, as they
occur, for immediate action, rather than buffering them for later DMA transfer.
9.4
(all BL1+)
a & b. The disk controller interrupts the CPU to notify it that the transfer is complete and the
data ready for use. If there were no interrupt capability, the program that is using the data would
have to wait long enough to assure that the data transfer is complete, in order to prevent data
corruption. But how long is “long enough?”
c. When the interrupt occurs, it causes the CPU to suspend execution of the program being
executed, then it saves the crucial parameters for later return to that program, and jumps to an
interrupt handler program. The interrupt handler notifies the program that the data is available
for use. Control is then returned to the program.
9.5
(BL1+) Before a tape controller can manage a DMA transfer, it must have five pieces of
information:
w Where the data is stored (or to be stored) in memory
w Where the data is located (or to be located) on tape
w How much data is to be transferred
w Which direction, tape-to-memory or vice-versa
w When, exactly, to initiate the transfer
Programmed output instructions would be used to send this information to the tape controller.
9.6
(BL1) An interrupt vector is the pointer to an address in memory that contains the program routine
for processing the interrupt.
9.7
(BL1) Polling is a technique in which a program uses programmed I/O to send out requests to I/O
devices for determining the status of the device. The device returns a message word that describes
the requested information. Polling is usually used for identifying I/O device events which require
attention when interrupts are not available. The CPU checks each device periodically for such
events. The disadvantage is the overhead required to use polling. A device must be polled
frequently enough to assure that data held by the I/O device awaiting transfer is not lost. If there are
a large number of devices to be polled, much of the CPU's time is wasted doing polling instead of
other, more useful processing. The use of interrupts is a better way of managing I/O requests.
9.8
(BL2) Once the starting block on the CD-ROM is found, the CD-ROM will be instructed to
transmit data to memory, continuously, block by block, using DMA. No seek time will be required,
since the head will be correctly positioned for the next block at the completion of each previous
block due to the fact that all the blocks are stored in sequence on a single, spiral track. The CPU
will attempt to create a buffer in memory large enough to hold several blocks simultaneously, so
that the CD-ROM can transfer blocks to memory before they are needed. The memory buffer
would be used in rotation to maximize the ability of the CD-ROM to stay ahead of the display of
each image. For maximum efficiency, the CD-ROM DMA transfer will receive highest priority for
memory access as well as highest priority for use of the bus connecting the CD-ROM and memory.
9.9. (BL2+) To initiate printing, the computer sets up a DMA transfer of one or more blocks of data from
memory to th printer's buffer. The initial transfer will also provide metadata to the printer to control
the type of printer output being requested. As the printer prints blocks of data, it sends interrupts to
the computer, requesting additional DMA block transfers. The printer will normally do this when
the buffer is running low, since the printer buffer normally holds several blocks at a time, however
some printers will wait until the buffer is empty before requesting additional blocks. The printer
will send an interrupt to the computer when printing is complete. This allows the computer to clear
the memory buffer and to close the print driver operation.
The printer must also have the capability to create interrupts that indicate printer problems. These
will suspend printing and result in messages to the user to fix the problem. The printer holds the
current print block in its buffer, with a pointer to the location where printing was suspended.
9.10 (BL2) A disk is a block-oriented device. Data is transferred between the disk and memory only in
fixed-size blocks, using DMA. A keyboard is a character-oriented device. The character-oriented
device transfers data a character at a time, using programmed I/O. In some systems, certain
character-oriented devices, particularly printers, transfer data using DMA under some conditions,
but the process is different, since the block is of variable size, as determined by the actual number
of characters on a particular page, for example.
9.11 (BL2-) An interrupt occurs at the onset of an event when a device requires attention or action, for
example a key is struck on a keyboard, a sensor detects a power failure, or an attempt is made to
execute an illegal instruction. These events are unexpected. Completion interrupts indicate that a
request made by a program has been completed. These interrupts are expected— indeed, awaited—
since they often mean that program processing may resume. The completion of a disk block read is
an example of a completion interrupt.
9.12 (BL2-) In general, an interrupt serves to allow external access to the CPU to notify the CPU of
external events that require attention or action by the CPU. Without interrupts, the CPU would be
required to take an active and continuous role in searching for external events, or risk losing
information that might be important to the system. Polling would have to be used for this purpose.
The cost of polling is CPU overhead, since each polling action requires the use of an output
instruction followed by an input instruction. The additional CPU burden can be severe under some
conditions, for example when the number of polled devices is large and the polling must be done
frequently. The overall effect is a reduction in system performance.
9.13 (BL2) Both are forms of polling, which uses the CPU to determine the occurrence of events. In the
case of polled interrupt processing, however, the event, an interrupt is known, so the polling is only
necessary when an interrupt occurs. The polling is used only to determine the source of the
interrupt.
9.14 (BL2-) When multiple interrupts occur, the first interrupt causes a suspension of the program
executing at the time, storage of that program's critical parameters, and transfer of control to the
program that handles the particular interrupt. When a second interrupt occurs, its priority is
compared to that of the original interrupt. If its priority is higher, it takes precedence, and the
original interrupt program is itself suspended. Otherwise, processing of the original interrupt
continues, and the new interrupt is held until the original interrupt program is complete. When the
higher priority interrupt process is completed, the lower interrupt is processed. If no further
interrupts occur and if no interrupt results in suspension of all CPU processing, control eventually
returns to the original program, which then resumes processing.
In general, multiple interrupts result in a queue of interrupt handler programs which will be
executed in the order of the priorities associated with each interrupt. The top priority program in the
queue executes unless it is replaced by an interrupt of even higher priority.