A Fast Lock and Adjustable Dual-Slope PLL with an Automatic Current
Controller
Kuo-Jen Lin (林國珍), Chih-Sheng Yang (楊智勝) and Chao-Chia Cheng (鄭劭家)
Department of Microelectronics Engineering, Chung Hua University
No. 707, Sec. 2, Wufu Rd., Hsinchu, 30012, Taiwan, R.O.C.
Tel: 03-518-6868 Fax: 03-518-6891
Email: kuojenlin@chu.edu.tw, s7186@hotmail.com, saujia@chu.edu.tw
Abstract
In this paper, we proposed a novel PLL with a current-controlled charge-pump followed by a second order
loop filter. The current-controlled charge-pump could speed up the lock time of PLL by using a dual-slop
technique. In our design, the current-controlled circuit receives the phase difference and the voltage of loop filter,
and controls the charge-pump to produce different amount of current for reducing the lock time of PLL. The PLL
has been designed using TSMC 0.18um 1P6M Mixed-Signal process and the simulation results are obtained by
HSPICE.
Key word: charge-pump, loop filter, phase-locked loop, lock time
1. Introduction
of current to speed up the lock time. In [6], the authors
Phase-locked loops (PLLs) are critical elements
proposed an adaptive bandwidth controller and
and are widely used in wireless telecommunications
charge-pump circuit to adjust the current for LF.
systems. The PLL uses the feedback to reduce the
When PLL is out of lock, the adaptive bandwidth
phase difference (or phase error) between the
controller will drive the charge-pump to provide a
reference signal and the locally generated signal. Most
large current for LF. When PLL is in-lock, the
of PLL circuits will use a phase frequency detector
adaptive
(PFD) to detect the phase difference. The PFD will
charge-pump provide a small current for LF. In the
control the charge-pump to produce a current, which
result, the amount of current will speed up lock time
adjust the control voltage through a loop filter (LF).
of PLL. In [7], the authors use a dual-slop PFD and
The voltage-controlled oscillator (VCO) generates a
charge-pump to achieve fast locking PLL. The
frequency that varies with the control voltage.
dual-slop is generated by a coarse-tuning loop and a
In modern frequency synthesizers and mobile
communication devices, strict requirements and
bandwidth
controller
will
let
the
fine-tuning loop. The dual-slop results will decrease
the lock time of PLL.
standards are put on phase noise and spurious levels.
In this paper, we propose a current-controlled
The dominant block causing the spurs is the
charge-pump to reduce the lock time of PLL. We
charge-pump. This is due to current mismatch,
design a current-controlled circuit to receive the up
leakage
Many
and down signal from PFD, and receive the voltage
charge-pumps have been proposed [1, 2, 3, 4].
from LF, then compare them to generate a control
However, all of them operated at lower speed. In [5],
signal for charge-pump. The charge-pump could
the authors use external signal to control the amount
produce a small current and a large current depend on
current
and
timing
mismatch.
the control signal. The proposed loop filter is designed
 e . When PLL is near lock, the VLF is large shown in
to eliminate the spurs.
Fig. 13. So, we can say d is change to a large value
due to the large value of VLF. A large current (IL) is
2. Adjustable dual-slope PLL
A. Automatic current-controlled charge-pump
added which is controlled by VC. The IL circuit is
shown in Fig. 6. If up =1 and dn = 0, then M1 is off,
A current-controlled circuit (CCC) is proposed to
M2 is on, the VCc1 is discharged to ground. When
determine when to use a large current. The block
VLF> VCc1, VC is in high level, then ILF = IS. The
diagram of proposed PLL is shown in Fig. 1. A
dual-slop characteristics could be observed at VLF
typical charge-pump and our dual-slope charge-pump
shown in Fig. 7.
are shown in Fig. 2. In Fig. 2(a), only the small
When PLL is out of lock, the loop bandwidth is
current bias (IS) constructs the charge-pump, but in
wide with larger current. When PLL is in-lock, the
Fig. 2(b), a large current bias (IL) and IS construct the
loop bandwidth is narrow with smaller current. The
dual-slope charge-pump circuit. If the dual-slope
average
charge-pump is used and PLL is out of lock, the
charge-pump is
current
supplied
charge-pump with IL is turn on, and the loop filter is
I LF 
quickly charged or discharged. If PLL is in-lock, the
by
current-controlled
(I L  I S )e '  I S e
.
2
charge-pump with IL will be disabled. In order to
speed up the lock time, the adjustable pulse width of
the phase delay d is used to control the turn-off
range of charge-pump with IL. The transfer functions
of charge-pump for initialization and near lock are
shown in Fig. 3(a) and Fig. 3(b), respectively. For
adding a large current IL early, d is set to a smaller
value shown in Fig. 3(a) at the initialization. When
PLL is near lock or far from initialization, the d is set
to a large value for delaying the joint of IL as shown in
Fig. 1 Block diagram of proposed PLL
Fig. 3(b). The adjustable d could prevent the large
current from charging over the condition of lock to
reduce the lock time. In Fig. 4, the IS is only used
IS
in the period of d , and both IL and IS are used in
the period of e , where the sum of d
and e is
the phase error  e .
up
Loop Filter
up
dn
dn
Vc
CCC
IL
IS
up
Loop Filter
dn
If PLL is out of lock, the large phase error will
IS
start to charge the Cc1 shown in Fig. 5, and then a low
IL
IS
level signal is generated at the control point by
comparing with VLF. If  e is large, Cc1 is charged by
I1 shown in Fig. 5, and if VCc1> VLF, Vc is from high
to low, then ILF = IL + IS, and the VLF is increased. In
this case, the VLF is like the d , the VCc1 is like the
(a)
(b)
Fig. 2 (a)The typical charge-pump
(b)The dual-slope charge-pump
ILF
ILF
M1
 d
 d
e
d
VLF
+
I1
e
d
dn
up
M2
Vc
CC1
Fig. 5 The current-controlled circuit
(a)
(b)
Fig. 3 (a) Transfer function for initialization
(b) Transfer function near lock
up
e
Vc
e
Vctrl
d
IS
IS+IL
Fig. 6 The charge-pump circuit with IL
t
Fig. 4 Waveforms in current-controlled circuit
Fig. 7 The control voltage on the loop filter (VLF)
B. Voltage Controlled Oscillator
The
LC-tank
VCO
is
the
complementary
cross-coupled structure which needs less power
consumption for the same phase noise in this design.
The current of the complementary cross-coupled
structure has twice as large comparing with
Fig. 8 Schematic diagram of VCO
cross-coupled structure, and has a good symmetrical
waveform that is related with low phase noise.
Therefore, we take the complementary cross-coupled
In Fig. 12, the lock time of the proposed PLL and
structure as the core structure. The phase noise is
the conventional PLL are 8µs and 38µs, respectively.
related with quality factor Q of the resonance tank [8].
Thus, the lock time of the proposed PLL is reduced by
The low phase noise requires a high Q. To achieve
about 79% in comparison with the conventional PLL.
low power and low phase noise the maximal L/R and
In Fig. 13, the VC is controlled by phase error, and the
L/C ratios are required [9]. Hence, we use two
ILF follows the VC to provide IL+IS or IS. The output
varactors in parallel to decrease the effective
voltage of LF is VLF which is depended on the ILF.
resistance. The final design of LC VCO schematic is
shown in Fig. 8. The detail of the proposed PLL
including CCC and charge-pump is shown in Fig. 9.
C. Other Circuits of the PLL
The PFD used in this work takes the form
described in [10]. The Frequency Divider is cascaded
by 7 TSPC D Flip-Flop to form a divider by 128.
3. Simulation Results
The current-controlled charge-pump PLL circuit
is designed using TSMC 0.18µm 1.8v 1P6M
Mixed-Signal CMOS process model with HSPICE
Fig. 10 Tuning range of the VCO
simulation tool.
The simulation result of frequency variation for
control voltage is shown in Fig. 10. The tuning range
is 500MHz (2.26~2.76GHz) for control voltage
variation from 0 to 1.8V. The performance of phase
noise is shown in Fig.11 for a carrier frequency of
2.4GHz, where phase noise is -123.2dBc @1MHz.
Fig. 11 The phase noise for VCO operating at
2.4GHz
4. Conclusion
In this paper, the current-controlled charge-pump
is proposed for using in PLL to accelerate the lock
time. Some simple digital control logic and an analog
comparator are used to form a CCC to control the
loop bandwidth effectively. The lock time is less than
Fig. 9 The proposed PLL with current-controlled
charge-Pump
8µs shown in the simulation. The lock time of our
proposed PLL is reduced by about 79% in comparison
with the conventional PLL.
[6] C. Hur,Y. Choi, H. Choi, and T. Kwon, “A low
jitter phase-lock loop based on a new adaptive
bandwidth
controller,”
in
proc.
IEEE
Asia-Pacific Conference on Circuits and Systems,
vol. 1, pp.421-424, Dec. 2004.
[7] K. H. Cheng, W. B. Yang, et al., “A dual-slope
phase frequency detector and charge pump
architecture
to
achieve
fast
locking
of
phased-locked loop,” in proc. IEEE ISCAS, vol.
1, pp. 777-780, May 2004.
[8] M.
Fig. 12 The control voltage for the proposed PLL
and the conventional PLL
Tiebout,
“Low-power
low-phase-noise
differentially tuned quadrature VCO design in
standard CMOS,” IEEE J. Solid-State Circuits,
July 2001, pp. 1018-1024.
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Fig. 13 The relation of the control signal and thecurrent of the charge-pump