Next-Generation SoC Platform for Terrestrial and Space Applications
Developed in collaboration with UMC, the 65nm embedded flash process enables the
development of programmable SoCs with an order of magnitude greater logic density and twice
the performance with less than half the power of previous generations.
by Esam Elashmawi, Microsemi
Microsemi’s SoC Product Group (formerly Actel) has completed a two-year technology
development effort to produce a platform for its next-generation systems on chips (SoCs). With
the acquisition of Actel, Microsemi adds customizable systems on chips (SoC) to its portfolio of
high-performance, high-reliability analog/RF devices and mixed signal integrated circuits. The
combined companies share a common focus on defense, security and industrial markets,
providing high-reliability solutions for both terrestrial and space applications. With this focus
and alliance, a new platform is needed for future programmable SoC development—a platform
that can address the requirements of both space and high-reliability terrestrial applications.
In November 2010, Microsemi, a manufacturer of high-performance analog/mixed signal
integrated circuits, high-reliability semiconductors and RF subsystems, acquired Actel. As a
result of the integration, Actel is now the SoC Products Group of Microsemi.
Both companies have long targeted the same markets with their products (security, defense,
aerospace and industrial), often doing business with the same customers. Moreover, both
companies have a shared vision of developing low power, highly reliable, highly secure
products. With the acquisition, there is a renewed focus on developing an SoC platform that can
address the needs of terrestrial applications as well as those for space.
Requirements for a Next-Generation SoC Platform
Since no single product can address all market needs, in developing the next-generation SoC
platform, the designers focused on addressing specific market needs.
For the terrestrial market, the choice is between addressing the needs of the datapath or the
requirements for sense and control. Datapath needs are seen primarily in communications
markets, where there is a need for extremely dense logic, high-performance, abundant block
RAM, and signal processing at the expense of power and integration. This market segment
typically has been addressed by large SRAM-based FPGAs.
In contrast, the needs for sense and control as typified by industrial, medical and
military/aerospace customers are integration, security and reliability rather than high density and
speed. These applications typically have used a combination of FPGAs, microcontrollers and a
number of ASSPs and discretes.
As with the terrestrial market, the space market can be split into two distinct segments: control
bus and data payload. The control bus is responsible for basic operation of the satellite, while the
data payload performs the actual mission. Both of these areas require radiation tolerance and
high reliability, but place different demands on programmable logic. The control bus performs
fixed, must-not-fail functions that are typically implemented in nonvolatile, radiation-tolerant
FPGAs. The payload typically needs greater density and performance that have often been
addressed by ASICs. However, there is a desire for programmable logic in these applications.
65nm Flash – a New Foundation
In collaboration with UMC since 2008, Microsemi’s SoC Products Group has been working on a
new process to power its next-generation products—65nm flash. This effort represents the
industry’s first embedded 65nm flash process optimized for logic performance. The recently
announced process offers some significant advantages over the company’s previous generation
of flash process, providing twice the performance, an order of magnitude greater logic density
and improved power performance.
These improvements do not come at the expense of the traditional strengths of flash-based
FPGAs, as this new flash platform still delivers single event upset (SEU) immunity for its
configuration memory, as well as enhanced IP security. CMOS memory structures, for example
static RAM cells and flip-flops, are susceptible to upset (change of state) when bombarded with
high-energy particles. These particles can be alpha particles, neutrons, protons or a wide range of
heavy ions, resulting from the collision of cosmic rays colliding with particles in the upper
atmosphere and from secondary collisions from particles liberated by cosmic rays.
When these charged particles strike the silicon substrate of an IC, they leave an ionization trail.
Similarly, when a high-energy particle, for example a neutron, strikes the substrate, it collides
with atoms in the substrate, liberating a shower of charged particles that then leave an ionization
trail. This ionization can result in a charge sufficient enough to overpower the gate and cause a
change in state (bit flip) of the memory element. This change in state is referred to as a singleevent upset (SEU). The configuration memory of SRAM-based FPGAs is susceptible to this type
of upset, which could possibly cause changes in device functionality.
The 65nm flash SoC platform is the basis for fourth-generation radiation-tolerant (RT) devices,
offering designers up to 20 million gates and a large amount of flip-flops, memory and hardened
embedded IP cores. The devices will include digital signal processing (DSP) blocks, PLLs and
high-speed interfaces (such as SpaceWire, DDR2/3, PCI Express).
The new architecture provides mitigation to total dose radiation and single event effects (SEE).
The configuration switches are inherently immune to upsets, while the user flip-flops are
implemented with built-in triple-module redundancy (TMR), eliminating the need for boardlevel mitigation schemes.
The New SoC Platform
At the heart of the new flash-based SoC platform is a new logic module. Unlike past flash
architectures, the new platform is based on a logic module composed of one 4-input LUT and
one D-type flip-flop (Figure 1). A 4-input LUT structure was chosen over a 6-input LUT because
of the better power versus performance curve. The new flash-based FPGA architecture is highly
secure, immune to single event upset, IP-friendly and is also optimized for sense and control
applications.
The new architecture, when combined with the 65nm flash process, enables a great leap in
density. New products developed using the platform will offer logic densities of tens of millions
of gates, empowering designers to implement more complex designs.
Moreover, the architecture was designed to be IP-friendly, enabling the integration of higher
functions such as DSP blocks, SERDES, MCUs, analog blocks, etc. Basically any IP block that
is compatible with the base 65nm UMC CMOS process is a possible candidate for integration.
Blocks currently slated for inclusion in platform products are the ARM Cortex-M3 MCU, an 18
x 18 multiple/accumulate for DSP functions, plus SERDES functionality (Figure 2).
Optimized for Low Power
The need for low power operation is no longer just a concern for handheld/portable devices. As
system complexity grows, the need for reducing the power demand of individual devices
increases. With this requirement in mind, the development team focused on reducing the
dynamic power of the new flash platform, achieving a 65% reduction in dynamic power over the
previous generation technology (Figure 3).
But reducing dynamic power is only part of the solution for achieving low-power operation. In
any system, not all parts of the system need to operate 100% of the time. As a consequence,
significant power savings can be achieved by turning off parts of the system. Normally
selectively powering down certain parts of the system is a complex task. However, this technique
has been greatly simplified with Flash*Freeze technology.
Introduced in earlier product generations, Flash*Freeze technology permits the easy entry and
exit from an ultra-low-power mode, retaining SRAM and register data without a need to turn off
supplies, I/Os, or clocks at the system level. For the 65nm flash platform, this capability has been
enhanced and improved, adding more intelligent control of power within a device.
Security Built In
Microsemi’s SoC Group has a long history of supplying highly secure products, preventing
overbuilding and IP theft. At its root, flash technology is secure. The microscopic size and sheer
number of flash switches in a device make it essentially impossible to locate each cell and
identify its programmed state.
The new SoC platform builds on this security leadership, improving configuration security, as
well as enhancing tamper protection. For example, hard IP (enhanced with optional soft IP) has
been added to the platform to thwart attempts to use differential power analysis (DPA) to
discover the internal workings of a design. Additional security and anti-tampering technologies
are in the product plans.
Communication is essential in all systems. In addition to industry standard communication
interfaces, such as USB, CAN, SPI, I2C and UARTs, the new platform also includes support of
high-speed serial interfaces with the inclusion of SERDES functionality. When combined with
the embedded, hard IP, this functionality enables the support for a wide range of serial
communication standards such as PCI Express 2.0, XAUI and Gigabit Ethernet. This new
process enables a range of new devices targeted at both terrestrial and space applications,
offering an order of magnitude better density, higher performance and lower power over
previous generations.
Microsemi, Irvine, CA. (800) 713-4113. [www.microsemi.com].