Gigabit Ethernet Design Project
Final Report
ECE4430 – Group 3
By: Ashley Lee and Shaun Rosemond
Date: December 11, 2001
Table of Contents
Title
Page Number
Abstract
2
Background
3
Design
8
Results
20
Conclusion
30
Resources
31
Appendix
I. Abstract
II. Background
With the advancement of technology, the need for increased performance and
speed has been driven with the arrival of multimedia, VoIP (Voice over Internet
Protocol), and other business applications such as databases, applications, and data
warehousing. As Figure 1 shows, server bottlenecks and increased traffic from more
users are the leading reason for most companies purchasing higher performance network
devices.
Figure 1. Factors Driving High Performance Purchases
Theory Behind Gigabit Ethernet
With the advancement of Ethernet to Fast Ethernet to Gigabit Ethernet in 1998,
the ability to achieve faster speeds while maintaining cost effectiveness is still possible.
With Gigabit Ethernet, speed of up to 1000 Mbps is achieved, which is ten to a hundred
times the speed of Ethernet. This advancement required changes to be made in the
physical layer of the OSI model. From the Data Link layer and up, Gigabit Ethernet
operates the same as Ethernet and Fast Ethernet. Due to the existing high-speed physical
interface technology of FiberChannel, changes were made to combine the IEEE 802.3
Ethernet and ANSI X3T11 FiberChannel standards. These resulted in the IEEE 802.3z,
for fiber and copper, and IEEE802.3ad standards, for Category 5 unshielded twisted pair
(UTP) cable.
For the differences between Fast Ethernet and Gigabit Ethernet, a look at the
physical layer must be done. The allowable configurations are short-wave (SX), longwave (LX), long-haul (LH), and copper physical interfaces (CX); only short-wave, longwave and copper will be supported at first. For the fiber-optic communications, the
encoding scheme is very similar to the 8B/10B encoding scheme, which is the same
encoding scheme used for FiberChannel. For Gigabit Ethernet, a 1.25-gigabaud signaling
will be used instead of the 1.062-gigabaud signaling used for FiberChannel.
Since
copper systems cannot use this encoding scheme, the encoding is instead performed by
the 1000Base-T physical sublayer (PHY).
Over fiber, short and long-wave lasers will be supported, and the standards are
defined as 1000Base-SX and 1000Base-LX. Multimode fiber is used in conjunction with
short or long-wave lasers, while single-mode fiber is used in conjunction with long-wave
lasers. Long-wave lasers operate at a wavelength between 1270 and 1355 nm and can be
used over distances up to 3 km, although it increases the cost of the system. Short-wave
lasers operate at a wavelength between 770 and 860 nm. Since short-wave lasers are
produced in mass for CD applications, they are less expensive. Also, short-wave systems
are used primarily with multimode fiber, which is supported at diameters of 62.5 and 50
microns. The main difference between the two is the ability to transmit light. Since
multimode fiber at 50 microns transmits better than fiber at 62.5 microns, the 50 micron
fiber is primarily used in Gigabit Ethernet. These short-wave systems over multimode
fiber can be operated up to a distance of 500 m.
For copper systems, a 150 Ohm balanced shielded copper cable can be used. The
1000Base-CX standard, within the IEEE 802.3z protocol, is defined for these
applications, but will only operate for distances less than 25 meters. The IEEE 802.3ad is
also defined for copper systems. This standard, 1000Base-T, uses the unshielded twisted
pair cable and operates by transmitting signals over four pairs of category 5 UTP cable.
This method allows distances under 100 meters, but is four times further than the
1000Base-CX standard. In Figure 2, a diagram of both the IEEE 802.3z and IEEE
802.3ad standards and the respective media types are shown.
Figure 2. Layout of IEEE 802.3z and 802.3ad Physical Layers.
Within the physical layer, the Media Access Control layer (MAC) contains the
Ethernet frame format. To maintain compatibility across Ethernet, Fast Ethernet, and
Gigabit Ethernet, the standard Ethernet frame format has been preserved. One difference:
the length field has replaced the type field within the packet. Within the Logical Link
Control (LLC), the DSAP, SSAP, and Control fields determine access into upper layers
using the LLC protocol data units (PDUs). Since protocols such as IP do not follow the
OSI model with which these correspond to, a new Subnetwork Access Protocol (SNAP)
frame was formed to circumvent this problem. With both DSAP and SSAP set to “0 x
AA”, the SNAP header will follow. Figure 3 shows the final Ethernet frame that will be
sent across Gigabit Ethernet.
Figure 3. Ethernet Frame Format
IEEE 802.3z Eye Mask
One significant mark of successful data transfer is an “eye pattern” between the
superimposed images of the data waveforms from a transmitting source on an
oscilloscope. According to the IEEE standard 802.3z for 1000BASE-LX receivers, the
required transmitter pulse shape characteristics are specified in the form of a mask of the
transmitter eye diagram shown in Figure 4. Therefore, if that mask can be used to
determine successful data transmission, it also verifies successful data at the receive end
as well. The eye mask shown in Figure 4 is implemented using a fourth-order BesselThompson filter and is defined as follows: The eye formed from the superimposition of
the data waveforms must have an opening with a width that is between 62.5 and 78
percent of the bit interval time, it must also have a normalized amplitude that can be as
low as 20 percent (not preferred) or as high as 80 percent. The definition of this eye
mask stated by the IEEE standard 802.3z must be applicable to the display of the received
data from the transceiver to verify proper functionality and an eye with those
characteristics defined by the eye mask is what is expected to be observed after testing
the evaluation board.
Figure 4. IEEE Standard Eye Mask.
III. Design
The focus of this design is to provide a fully functioning Gigabit Ethernet card,
with the incorporation of our new module, to the group for next semester so that they can
build a more cost-effective card. Since the most expensive part of this design revolves
around the optomodule, this is where our design is focused. In order to reduce the cost of
the card, a less expensive optomodule is needed; To be able to test other optomodules, a
design needs to be built that incorporates the current optomodule, but can also be used to
test replacement optomodules. The optical module that is used on the Intel card, and we
will be using for our design, is the HFBR-53D5 optomodule from Agilent Technologies.
This optomodule is compliant with IEEE 802.3z 1000 BASE-SX. According to this
standard, a short-wave laser, at 850 nm, is used with a multimode fiber with an inner core
of 50 μm.
The optomodule is a VCSEL (Vertical Cavity Surface Emitting Laser)
mounted in an Optical Subassembly (OSA). The schematic for this circuit is located in
Figure 5 and will form the basis of our design.
Figure 5. Schematic of Optomodule and Connections.
There are various changes in our design versus the design incorporated in the
previous groups. Our main design change incorporates differential signals rather than
single ended signals coming from the coaxial inputs. Even though the previous groups
achieved operating boards, thoughts were that differential signals would provide stronger
results. In a single ended circuit, noise is gained during transmission of the signal,
thereby attenuating the signal.
The same is true for differential mode circuits, but for
every signal generated on both the transmit and receive ports, an inverted signal of that
exact same signal is also generated. Therefore, if the original signal A is altered by some
random noise , then the inverted signal -A will also be adjusted by that same noise value
. When the two signals are subtracted the resulting signal is one where the noise has
been, in essence, removed via the subtraction, and inherently the signal will be magnified
by two which makes the necessary components of the signal easier to be interpreted by
the internal circuitry of the transceiver. This is shown in Figure 6.
Figure 6. Diagram of Differential Operation.
In addition, the new design uses SMA connectors rather than BNC connectors.
SMA connectors offer higher durability due to the fact that they are threaded, which
provides a better connection.
This connection allows SMA connectors to achieve
frequencies up to 18 GHz, while BNC connectors operate up to 4 GHz. Even though we
will not be using frequencies higher than 4 GHz, there are other reasons for choosing the
SMA connector. The SMA connectors are smaller than the BNC connectors, therefore
making it easier to put them onto the board. Also, the oscilloscope that will be used to
test this module comes fitted with SMA connectors as well. Therefore, standard SMA to
SMA cables can be ordered instead of special SMA to BNC cables.
As mentioned previously, the improved functionality of the new versus old
evaluation board is due to the implementation of the differential inputs/outputs. As a
result, new evaluation boards had to be constructed. These new boards, much like those
fabricated for single-ended implementation, consist of two thin layers of metal, separated
by an insulating material with grooves cut into the insulating material to represent nonconducting surfaces. The new boards are also similar to their predecessors in that they
contain small pinholes necessary to mount the Gigabit Ethernet module and the surfacemount components; the main difference is these new boards have been designed to
incorporate differential capabilities with pin cut-outs for two sets of connectors for the
receive and transmit ports. Figure 7 displays the layout of the new differentially enabled
evaluation board.
Figure 7. Layout Picture of Differential Circuit Board.
Figure 8. Differential GBIC Module Layout
The circuit layout, shown in Figure 8, is that of the transceiver module used in
constructing the evaluation board for differential implementation minus the driver
circuitry employed by the Intel Pro/1000F Gigabit Ethernet Card. In addition, Figure 9
shows the predicted implementation of this design. It has been proven from single-ended
implementation that this design, which only focuses on the transceiver itself, will work as
long as the 50 ohm data inputs are maintained. On the transmit lines, this is explicitly
employed with the use of a 191 ohm resistor in parallel with a 68 ohm resistor.
Preliminary observation shows that these two resistors in parallel result in an equivalent
resistance of 50.15 ohms on each of these lines. The equivalent resistance of 50 ohms on
the receive lines from the module however, is not so obvious. Each of these lines
employs the use of a 267 ohm resistor; these resistors provide the biasing necessary to
drive the transmission lines on the reception side. In addition, these lines are more than
likely terminated within the Intel board with 50 ohm resistors to achieve impedance
matching as well.
Receive
Optomodule Pins:
9
8
7
6
5
4
3
2
1
Vcc1
Vcc2
Part
.01 μF
267 Ω
191 Ω
68 Ω
Color
Yellow
Blue
Red
Green
Transmit
Figure 9. Picture of Planned Implementation of Differential Circuit Design.
The issue of matching the data inputs on the evaluation board with those that
existed on the network card is a fundamental concept behind transmission line theory.
Transmission lines exist in high-performance digital circuits where the operating
frequencies approach a Gigahertz. At high frequencies, traditional circuit approaches do
not apply because they do not assume a finite signal velocity, and on materials such as
printed circuit boards high-frequency signals generate an inherent capacitance,
inductance, and resistance of the equivalent circuit. These possible delays in signal
propagation must be taken into account to maintain proper functionality of the clocks and
switches within the circuit.
Capacitors are also used in the circuit design. The capacitors connected between
the power supply and ground function as coupling capacitors. These coupling capacitors
compensate for the small to medium amount of inductance inherent in the wire to the
power supply, the board, and the bonding of the parts to the board. At high frequencies,
the small inductances model an open circuit resulting in no current flow and cutting off
the amplifier. On the other hand, capacitors model a short circuit at high frequencies. By
placing a capacitor close to the pins connected to the power supply and connecting it to
ground, the capacitor provides the current needed to operate the amplifier, while at the
same time recharge over time from the initial power supply. The .01 μF capacitors, used
in the design, compensate for frequencies between 10-100 MHz.
For frequencies
between 1-10 MHz, a capacitor of .1 μF is needed. For our circuit, there are not any parts
that function at this band of frequencies so the .01 μF will solve the inductance problems.
They also function to maintain a constant voltage and Spice simulations demonstrating
this are located in Appendix A.
Taking into account that the transceiver had already been designed for optimal
performance and because that was not the focus of this project, that issue could be
ignored but another issue concerning transmission lines could not be disregarded, and
that is impedance matching. Impedance matching is significant in signal termination.
Every transmission media has a characteristic impedance which is standard for the
transmission of the signal at a desired frequency. When terminating the signal however,
it is imperative that the load placed on the end of the transmission medium be equal to
that of the characteristic impedance such that there is no signal reflection.
Signal
reflection resulting from impedance mismatching induces signal loss that prevents proper
functionality. In regards to this project, 50 ohm terminations have to be maintained on
the evaluation board as well as in the transmission media to ensure optimal performance.
Because RG174 cable which has an operating capacity up to 3GHz and is 50-ohm
terminated, not only will be able to satisfy the high frequency requirement of 1GHz
transmission, but it also matches the 50 ohm terminations present on the board to
minimize signal loss due to signal reflection between connections of various media.
In order to implement the design of this Gigabit Ethernet Card, several parts are
needed. Primarily, an Intel Pro/1000F Gigabit Ethernet Card is needed in order to
interface with the GBIC (Gigabit Interface Card) module, and another Gigabit Ethernet
card in order to establish a network connection. Multimode fiber optic cables with
lengths of 20, 50, and 100 meters will be ordered to test the longest length without high
bit error rates. The Intel Pro/1000F comes with internal testing functions such as internal
loopbacks and end-to-end connectivity to verify the card is sending and receiving a
correct signal.
The following parts are needed in order to build the GBIC: an Agilent HFBR53D5 Optomodule, four SMA connectors, resistors (68 Ω, 191 Ω, 267 Ω), and capacitors
(.01 μF). To connect the card to the Intel board, coaxial cables with an impedance of 50
Ω and an upper frequency of 2.5 GHz is required. By taking the 5th harmonic of a 500
MHz wave, the frequency of signal transmission, the rise and fall times of the edge are
maximized; the 5th harmonic of this frequency is 2.5 GHz. This is shown in Figure 10;
since the function is a cosine, only the odd harmonics are displayed. The coaxial cable
selected that meets these requirements is the RG174 cable. Also, two 5V power supplies
are needed to power the GBIC module. If these power supplies cannot be found, the
power supplies of Zip drives provide the proper voltage and connector size to operate our
circuit.
Figure 10. FFT of 1GHz Square Wave.
Upon building the design that has been put forth, there are some potential
problems that could occur. After assembling and testing the GBIC module, it will be
incorporated into the Intel Pro/1000F board. Pins 2, 3, 7, and 8 will be connected to the
Intel board. These pins as well as other aspect of the Intel board are shown in Figure 11.
These four pins are the transmission and receiving lines of the coaxial. The coaxial cable
will have to be stripped and soldered to the Intel board to provide a good contact.
To
prevent the stripped coaxial cable to be “seen” by the circuit, less than a 1/10 of a
wavelength can be exposed. As the length increases from 1/10 to ¼ wavelength, phase
changes are introduced that can significantly impact circuit performance. At the 5th
harmonic, 2.5 GHz, the length of a wavelength is equal to just less than .1 meters. At
1/10 of a wavelength, the exposed coaxial cable can be no more than .01 meters. With a
short length of exposed with which to work, soldering becomes increasingly difficult.
Interfacing with Intel Pro/1000F Board
Blue
Yellow
Red
Signal Detect
Resistors
Capacitors
Figure 11. Part of the Intel Board with Connections to the GBIC Module.
Another difficulty is the unknown operation of the signal detect on the
optomodule, which is Pin 4. Even though the previous design team neglected this
connection on their design, its function might determine whether the GBIC module will
work with the card. It is thought that this signal might provide the initial synchronization
of two network cards. If connected, the length of this cable is also required to be less
than .01 meters. In order to connect this pin, wrapping wire has been chosen because it
provides no characteristic impedance to alter the operation of the circuit.
With the removal of the Agilent optomodule from the Intel board, the circuit that
biases the coaxial lines remains intact on the Intel board. Since these resistors and
capacitors are incorporated into the design of the GBIC module, some parts may need to
be removed from the Intel board. It is clear that the resistors will be removed and their
removal should pose no problem, but it is also thought that the capacitors should stay. If
these capacitors were removed, the paths would have to be jumped on the board, and this
would be very difficult if possible at all. In addition, these capacitors more than likely
will not affect the operation of the Gigabit Ethernet card if removed.
There are other potential problems not related to the Intel board. One issue is the
problem is soldering the parts onto the board. Since the space between paths is very
limited and small, there is a possibility of jumping a gap and shorting two leads together.
Also, a cold solder could result if the solder is not fully heated up when a component is
added to the board. This could provide a bad connection resulting in poor performance.
Using good soldering techniques, these issues will be minimized. Another issue is the
potential problem of an inoperative optomodule or other part. The optomodules were
removed from the single-ended boards before being added to our new evaluation boards.
During this process, if the pins on the optomodules were heated enough, the internal
components of the module might not work. The results of this problem cannot be
determined until testing.
Upon soldering the coaxial cables to the Intel board, more needs to be done to
prevent the soldered connections from breaking during handling. A likely solution will
be to hot glue the coaxial cables to the extreme edge of the board, where the optomodule
used to be. This has to be done so that it will be possible to remove the glue and the
cables without destroying the board. Also, the gun used for hot gluing the cables to the
board needs to be a low temperature gun to prevent damage of temperature sensitive chip
devices on the Intel board. Overall, this solution seems to be the best given the durability
and other issues discussed. With regard to temperature, soldering the coaxial cables to
the board could pose problems because of the high temperatures used for soldering. To
prevent damage to the chip components on the Intel board, the temperature of the
soldering iron must be turned down to around 4000 C and cannot be touched to the
surface for a prolonged amount of time.
Next, the Intel board poses several problems that will be encountered. There are
terminating resistors for the transmission lines on pins 7 and 8 of the optomodule. Since
the transmission lines will be terminated directly before the optomodule, these four
resistors will be removed from the Intel board. On the receiver side of the optomodule,
pins 2 and 3, bias resistors are located on the Intel board and the evaluation board. These
resistors will need to be removed from the Intel board for the circuit to work. The
removal of all resistors will not affect the performance of the circuit because these
resistors are connected to ground. On receive and transmit channels, there are .01μF
capacitors along the transmission lines. Since these capacitors likely pose no problems,
and it might be difficult to remove and short the connections, these capacitors will be left
in place. If further testing dictates the removal and shorting of these connections, then
methods will be sought to remedy the problem. On the SD pin, the evaluation board does
not contain resistors to bias the lines, but the Intel board does contain the resistor
necessary for this operation. Also, after using the short segment of wire, the line will
become a transmission line. We are assuming that the circuitry used to perform the
termination on pins 2 and 3 will also be present on pin 4.
IV. Results
Once the design for the optomodule and the evaluation board was built, tests were
conducted in order to determine the results of the preliminary design. After conducting
these tests in the lab with a BER tester and an oscilloscope, it was determined that the
optomodule was correctly incorporated into the evaluation board. After this success, the
Intel board was connected to the evaluation board and tested in a working computer in
the lab. Various tests were conducted, and the finished Intel board, with the incorporated
evaluation board, did in fact operate within the computer.
Optomodule and Evaluation Board
A diagram of the set up used to test the evaluation board is shown in Figure 12,
while a picture of the same equipment used appears in Figure 13. It consists of a
Tektronix TDS 694C Digital Oscilloscope, a Microwave Logic gigaBERT-1400 Tx
Pattern Generator, a Microwave Logic gigaBERT-1400 DRx Bit Error Tester, and the
evaluation board designed to optimize the performance of the transceiver module. The
set up was arranged such that the output signals of the pattern generator were sent to the
transmit ports of the transceiver module (pins 7 and 8 of module); one of the receive
signals from the module on the evaluation board was then sent to Channel 1 on the
oscilloscope, and the inverted signal was connected via coaxial cable to the bit error
tester, where it was then connected to Channel 2 on the oscilloscope (pins 2 and 3 of
module). Connected to Channel 3 on the oscilloscope was the clock of the pattern
generator so it could be used as a triggering source when viewing the data stream
waveforms on the oscilloscope. Finally, the fiber optic cable was connected to the optical
cable ports on the transceiver module.
Digital
Oscilloscope
Evaluation
Board
Rx
Pattern
Generator
Tx
Bit Error
Tester
Figure 12. Diagram of equipment utilized in test setup.
Figure 13. Picture of the Setup Used to Test the Evaluation Board.
The configuration of the pattern generator was as follows:
Initially, to verify the
functionality of its design, it was set to produce a square wave with an amplitude 0.5V
and a frequency set to 1GHz. Later the frequency was varied to determine error rates at
higher data rates. Along with varied frequencies, the bit pattern was also varied to
evaluate the performance of the evaluation board was the bit error tester used to measure
the error rate in the data received from the transceiver module. It was initially set with a
patent of 27-1, and it was later varied to 223-1. A patent is a set pattern of ones and zeros
used by the bit-error tester to calculate the error rate during data transfer. Calculations of
error rates at higher patents are more accurate because higher patents can catch errors that
would elude lower patents at high data rates.
After preparing the equipment and arranging the set up as described, the
equipment was run and the resulting output waveforms shown on the digital display of
the oscilloscope are shown in Figure 14. Channels 1 and 2 of the oscilloscope are the
inverted and non-inverted signals from the receiver output ports. The waveform on
channel 3 is the clock from the pattern generator used to trigger the display on the
oscilloscope. Preliminary observation shows that the eye diagram of the waveform on
the oscilloscope display would easily encapsulate eye mask, thus proving superior
functionality. If the knowledge of the mask was unknown however, a bit more detailed
look at the eye would show that the eye opening was approximately 80 percent of the bit
period, which is favorable characteristic for eye diagrams because it displays that the eye
is in fact very wide and open.
Figure 14. Eye Diagram of Received Data.
In addition to the qualitative verification of the transceiver functionality provided
by the eye mask being able to be inscribed in the eye diagram, the bit error tester also
provided quantitative results in the form of bit error raters (BER). Table 1 shows the
different BER for different patterns and different frequencies created by the packet
generator.
As displayed in the table, there were zero errors per 1011 bits in the
transmitted data when transmitting at 1GHz, which means the transceiver topped out at
zero errors in 100 seconds utilizing the 1GHz data rate.
Then, the frequency was
increased to 1.2 and 1.4GHz, and the pattern was varied to 223-1. Changing the pattern to
this increased setting allows more accurate bit error rates to be calculated. The pattern is
a set stream of ones and/or zeros inserted into the data stream when generating the data so
that a known reference can be utilized when calculating the bit error. Increasing the
pattern to 223-1 is appropriate because when operating at high data rates such as 1GHz or
more, low patterns are not sufficient enough to handle high speeds; not only that, but
higher patterns resemble more of the demanding applications found in data transmission
today, and errors that are more noticeable which may be eluded in small patterns which
makes it more efficient for testing the maximum performance of the transceiver.
Ultimately, the eye diagram and the BER are directly related: The larger the opening of
the eye the better BER for data transfer.
Table 1. Error rates (errors/sec) calculated by bit error tester
Bit Error Rate (BER)
Pattern
Frequency
0 at 10-11
27-1
1GHz
1.1*10-8
223-1
1.2GHz
6.8*10-6
223-1
1.4GHz
Thus far, we have encountered a few design issues.
First, a problem was
discovered during initial testing. A signal was input to both differential inputs, and no
output signal was detected. After eliminating testing equipment problems, the evaluation
board was looked at. On the board, there are four holes for electronically connecting the
top of the board to the bottom of the board. These are shown in Figure 15. Since the
board uses both sides for signal transmission, they have to be connected. During our
initial testing, the evaluation board had all four holes open. To solve this problem, we
took short segments of wire from a resistor and soldered it across the holes.
Figure 15. Diagram of Location of Via Pins.
In addition, we wanted to make sure there were no other problems with the setup
on the board. Using a voltage meter and a power supply, the board was tested for power
connectivity across the power and supply paths on the board. It was discovered that both
power supply voltages were relatively zero volts. Since the top of the board needs to
carry the power supply voltage, the power supply leads need to be soldered to the top of
the board. In our board design, the power supply connector is soldered on the bottom
side of the board resulting in no connection to the top of the board. The power supply
connectors had to be unsoldered and replaced making sure that upon soldering, the solder
drips down to the top of the board for each pin connection. Upon solving this problem,
the power supply voltage from pin 1 to 5 and pin 6 and 9 on the optomodule was
relatively 5 volts.
Evaluation Board Interfaced with Intel Card
After verifying the incorporation of the optomodule and evaluation board proved
successful, the Intel board was connected to the finished evaluation board. The coaxial
cable was stripped so that about 1 cm was exposed before being soldered to the board.
The temperature used to solder was about 6000, which was above the specified
temperature. Since no intergrated circuits were nearby, the small increase in temperature
posed no problem. Pins 2, 3, 7, and 8 were connected, as these were the pins required for
data transmission, and the shields of the cables for pins 2 and 3 were connected together,
as were the shields of the cable for pins 7 and 8. Also connected was the signal detect
pin, which was specified in the original design. Short segments of wrapping wire, about
one foot in length, were used to connect the SD pin; It was stripped to expose about 2 cm
of wire before being soldered to the board and the Intel card.
After soldering these connections, the Intel board was inserted into the computer.
The setup used to test the combined evaluation board and Intel board is shown in Figure
16, while a picture of the setup is shown in Figure 17. After determining all connections
were correct, the new Gigabit Ethernet Card did not operate. Thoughts were that a
ground connection was required for the Signal Detect pin from the evaluation board to
the Intel board, so another wrapping wire was used to connect pin 1 on the evaluation
board to pin 1 on the Intel board. After this connection was established, the card was
reinserted into the setup that is displayed in Figures 16 and 17.
Figure 16. Setup for Testing the Complete Gigabit Ethernet Card.
Figure 17. Picture of the Setup Used to Test the Complete Gigabit Ethernet Card.
After reinsertion of the card into the computer, the Intel diagnostics tool was run
in order to determine if the card was operating correctly. A link and loopback test was
performed and both operated correctly. The loopback test is performed on the Intel card
to determine working operation of the card.
The link test determines if the fiber
connectivity is operational. After passing both of these tests, an advance test was done;
this test involved sending packets from one computer to the other. Our new Gigabit
Ethernet card was configured as the sender in one test and the responder in the other. In
both cases, the card passed with perfect results as shown in Figure 18. In addition, Figure
19 shows the Windows network connectivity as the other computer is displayed in
Network Neighborhood. A Microsoft Word file was transferred across this connection
and the file was transferred perfectly.
Figure 18. Screen Capture of Diagnostics Tool Operation.
Figure 19. Screen Capture of Gigabit Ethernet Card Operating under Windows Networking.
V. Conclusions
After obtaining the final results for this project, our initial design proved to be
more than adequate to accomplish the goals of the project. A functional Gigabit Ethernet
card was tested over a computer network in Windows and worked as well as before.
Therefore, next semester’s groups can begin to work to reduce the cost of the optomodule
used in the design. Replacements will be chosen and incorporated into the functional
design we have implemented.
VI. Resources
Introduction to Gigabit Ethernet
http://www.cisco.com/warp/public/cc/techno/media/lan/gig/tech/gigbt_tc.htm
IEEE Std 802.3, 1998 Edition Part 3: Carrier Sense Multiple Access with Collision
Detection (CSMA/CD) access method and physical
http://gtel.gatech.edu:2172/search97/s97is.vts?Action=Search&SearchPage=VSearch.ht
m&ResultTemplate=Toc_Result.hts&ViewTemplate=lpdocview.hts&queryText=(isnum
ber<contains>15560)&collection=stds&SortField=hpag&SortOrder=desc&ResultCount=
15
Eye Diagrams
http://www.samsungelectronics.com/fiberoptics/downloads/tr851sa.pdf
http://www.rfpowernet.com/pdfs/AN_Datacom.pdf
10-Gigabit Ethernet Alliance
http://www.10gea.org/tech-faqs.htm
10-Gigabit Ethernet Alliance Technology Overview White Paper
http://www.10gea.org/10GEA_Whitepaper_0901.pdf
http://www.cisco.com/warp/public/cc/techno/media/lan/gig/tech/gigbt_tc.htm