ECE/CS 352 Digital System Fundamentals
2/16/16
ECE 352: Digital Systems Fundamentals
Department of Electrical and Computer Engineering
University of Wisconsin – Madison
Mentor Graphics Project 1
Dates: September 18 - October 13, 2000 (due in class)
The project is designed to increase your familiarity with modern digital design tools and
concepts and to help your understanding of material covered in class. It will require the use of
Mentor Graphics, CAFE, and skill learned in class. It must represent YOUR INDIVIDUAL
EFFORT. You may not use a partner in this project
1. (20 points, Cafe) Sometimes the design process produces functions that are too large to
minimize by hand. Then automated design tools are needed to help in the process. We will
design a two-level circuit that forms the square root of an 8-bit number. We will investigate
two different numerical implementations: one will round to the nearest integer and the other
will truncate the result. Here is the design process:
Step 1: Define the problem. The
problem can be specified in a tabular
form by using a program to generate
the entries for the "rounded" (RND)
version and "Truncated" (INT)
versions. For example, we used an
Excel spreadsheet to generate a 4-bit
version of the function below. Note
that the RND and INT require a
different number of bits.
From the class homepage you will
download two files: INT.txt and
RND.txt. Each of these files will
consist of the binary parts (NUM
and INT) or (NUM and RND) in 8bit version. Each of these can be
seen as a truth table of 8 input
variables and 7 (INT case) or 8
(RND case) outputs.
Decimal
NUM SQRT INT RND
0
0.00
0
0
1
1.00
1
1
2
1.41
1
1
3
1.73
1
2
4
2.00
2
2
5
2.24
2
2
6
2.45
2
2
7
2.65
2
3
8
2.83
2
3
9
3.00
3
3
10
3.16
3
3
11
3.32
3
3
12
3.46
3
3
13
3.61
3
4
14
3.74
3
4
15
3.87
3
4
Binary
NUM INT RND
0000 00 000
0001 01 001
0010 01 001
0011 01 010
0100 10 010
0101 10 010
0110 10 010
0111 10 011
1000 10 011
1001 11 011
1010 11 011
1011 11 011
1100 11 011
1101 11 100
1110 11 100
1111 11 100
Step 2: Investigate Implementations: We will examine the two implementations by using
CAFE to come up with a minimum literal implementation. To use cafe, you must convert
the tabular data into a form that CAFE can use -- the <table> specification form. The 4-bit
square root example input file and output file for a CAFE run are shown below. You are to
run cafe with the full 8-bit RND and INT versions and compare the results. To do so, copy
the raw data files from the ece352 directory, add the CAFE commands needed to run CAFE,
and run CAFE on both versions.
ECE/CS 352 Digital System Fundamentals
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Report: CAFÉ output files (edited version) of both INT and RND version. Edit the result
files to show the Header (first line printed by CAFE, the Connection array output, and the
generated equations. Note on the printout on which approach has a smaller implementation
in terms of number of literals.
2. (30 points, Decoder circuits)
a. (15 points) Enter the logic schematic of a 2-to-4 line decoder as shown in Figure 3-14,
pp. 113 of the text book using Design Architect. Make a symbol, and name it
2to4_decoder. Create a force file to apply all 8 possible combinations of the inputs at
10 ns interval, and derive the truth table by simulating it with QuickSim.
Report: Logic schematic, symbol, and QuickSim output in list format. Circle the
output lines from the list that constitute the truth table.
b. (15 points) Enter the logic schematic of the circuit shown in Figure 3-57 (problem 3-7)
of the text book in page 171 using Design Architect. Use the 2to4_decoder you
developed in part a. Then devise a force file to derive the truth table of this circuit.
Also, find the longest propagation delay of this circuit.
Report: Logic schematic, QuickSim output in list format. Circle lines on the list
corresponding to the truth table, and discuss how you find the longest
propagation delay from the output list.
3. (50 points, Adders)
a. (10 points) Use only 2-input or 3-input NOR gates to implement a 1-bit partial adder.
An implementation using two XOR gates and an AND gate is shown in Figure 3-29,
page 130 of the text book. Denote its inputs as A, B, and C (carry-in). Enter the logic
schematic using Design Architect. Make a logic symbol and call it PFA. Derive its
true table by devising a force file and apply QuickSim. Find the longest delay to
outputs S, P, and G.
Report: Logic schematic, and logic symbol. QuickSim list output. Circle lines of
the output list that constitute the truth table. Discuss how you find the output
delays.
b. (20 points) Design a 4-bit ripple-carry adder as shown in the middle of Figure 3-29
according the following steps: (i) Using 2- or 3-input NOR gates only to implement
the 4-bit ripple carry chain. Make a symbol of it, and call it ripple_carry. Group all
four Pi's into a P BUS, all four Gi's into a G BUS, and all five Cis into a C BUS. (ii)
Creat two input buses A and B consisting of the 4-bit Ai's and Bi's respectively.
Connect four PFAs to the corresponding wires in the A, B, P, G and C buses using
ripplers. Connect the four output Si's into a S BUS. (iii) Download the force file
adder.force from the course web page (project section) and simulate this ripple carry
adder. (iv) Estimate the maximum delay of this ripple carry adder assuming all inputs
Ai's, Bi's, and C0 are made available simultaneously.
Report: Logic Schematic of the ripple carry adder, QuickSim simulation output
in both the list format and the trace format. Specify values of A, B, C, P, and G
buses using the Hexadecimal format. Clearly mark the desired outputs at the
trace output. Discuss how you estimate the maximum delay by identifying the
critical path (longest delay) on the schematic, and give your estimate of the
longest delay.
c. (20 points) Design a 4-bit carry-look-ahead circuit as shown in Figure 3-29 using
only 2- or 3- input NAND gates (note the constraint). Try to minimize both the
delay and the number of gates used. Enter the design using Design Architect, and
make it a symbol carry_lookahead. As in part b, group its inputs and outputs into P,
ECE/CS 352 Digital System Fundamentals
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G, and C buses (Note that G0-3 and P0-3 should be part of the corresponding buses).
Then, connect four PFAs to construct a 4-bit carry-lookahead adder. Use bus ripper to
connect individual wires of each bus. Denote inputs as A and B buses, and the output
as S bus. Use the same force file as part b to simulate this carry look-ahead adder, and
estimate its maximum delay.
Report: Logic Schematic of the carry look-ahead adder, QuickSim simulation
output in both the list format and the trace format. Specify values of A, B, C, P,
and G buses using the Hexadecimal format. Clearly mark the desired outputs at
the trace output. Discuss how you estimate the maximum delay by identifying
the critical path (longest delay) on the schematic, and give your estimate of the
longest delay.