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Wireless Chip Designer
Sept 26, 2006
Theme: Low Power (Mobile)
www.chipdesignmag.com/wirelesschipdesigner
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Today's Table of Contents:
1. Goodbye, Mr. DSP
2. Base Stations Sales On The Decline?
3. RF Architectural Planning Tool Now Available For Communication Design
4. Power-Rail Analysis Now Available For Full Custom Designs
5. Partnership Results In IP Library
6. Low-Cost FPGAs Offer Embedded SERDES
7. Brazil Design Center Opens
8. VLSI Design Initiative Launched
9. In-Depth Coverage Links
> That 80's Show or AMS IP Creation Flashback
> What's Your Verification Game Plan?
10. New Books
11. Happenings -- Conferences
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1. Viewpoint - Exclusive
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Goodbye, Mr. DSP
Steve Leibson, technology evangelist, Tensilica, Inc.(http://www.tensilica.com)
The classic movie “Goodbye, Mr. Chips” follows the life of British schoolteacher Charles
Edward (Chips) Chipping. At the end of the movie, Mr. Chips passes on. Like Mr. Chips,
digital signal processors (DSPs) have reached the end of their road - at least as on-chip
processor cores. They served the industry well, but System-on-Chip (SoC) technology
has passed them by. Digital signal processing is now mainstream technology, so it may
seem heretical to declare the end for DSP cores.
Early general-purpose processors lacked hardware multipliers because they consume a
large number of gates. Signal-processing algorithms such as FIR and IIR filtering largely
consist of endless multiplications. Consequently, DSPs have incorporated multipliers and
MAC (multiplier/accumulator) units ever since Texas Instruments introduced a DSP with
a single-cycle hardware multiplier in 1982. Today, configurable processor cores such as
Tensilica’s Xtensa family have optional MAC units, so MAC units no longer make DSPs
unique. High signal-processing computational requirements spurred DSP designers to add
parallel, independent execution units. Like hardware multipliers, parallel-execution and
SIMD units are no longer exclusive to DSPs. They can easily be added to a configurable
processor’s instruction set and software-development tool chain.
High-speed computation units need a stream of operands. The results of these operations
create a corresponding result stream. Consequently, a processor’s ability to efficiently
execute computations must match its load/store bandwidth. To address the need for
greater memory bandwidth, DSPs incorporate non-standard memory architectures that
perform multiple memory accesses per cycle. The most widely adopted approaches are
Harvard architectures (e.g. separate memory buses for instructions and operands) and XY
memory architectures, which simultaneously fetch operands from separate memory
banks. Configurable processor cores offer all of the memory-architecture options
developed for DSPs with address-generation units that accelerate algorithm execution, so
these features are no longer unique to DSPs.
It’s often possible to simultaneously execute the same operation on multiple data words
within the inner loop of a signal-processing algorithm using SIMD (single-instruction,
multiple-data) execution units. For algorithms where SIMD execution is useful, the
parallelism can be quite high. A 4-way or 8-way SIMD unit can effectively accelerate an
inner loop respectively by a factor of four or eight. Like the other features discussed
above, many processor architectures including configurable cores incorporate SIMD
units.
High-performance DSPs have become VLIW (very-long instruction word) machines.
They issue multiple independent operations to their parallel execution units during each
cycle. VLIW processors require wider instruction words with perhaps 32 or 64 bits (or
wider) per instruction instead of 16. These wider instruction words produce code bloat—
the program code expands simply because of the larger instruction word, not because
more work is performed.
The added ability to execute multiple independent operations per clock cycle need not
incur code bloat. Tensilica’s Xtensa LX processor core incorporates a VLIW-like feature
called FLIX (flexible-length instruction extensions) that adds 32- or 64-bit multi-issue
operation bundles to the processor’s existing 24/16-bit native instruction set. The
compiler selects FLIX instructions if they’re more efficient than the equivalent sequence
of native instructions, which greatly accelerates code within loops. In control code (all
signal-processing algorithms are laced with such code), parallelism is generally not
helpful, so the compiler selects the processor’s narrower native instructions.
Automated compiler selection of appropriate instructions opens this discussion to a major
difference between DSPs and DSP-augmented configurable processor cores. In general,
the DSP’s highly specialized, irregular, and complicated instruction sets, small register
files, and irregular memory architectures make them poor compiler targets. Compiled
DSP code is relatively inefficient because the compiler must translate from C to the
DSP’s irregular instruction set and small register complement.
Conversely, the general-purpose configurable processor is a good target for compiled
code. Configurable processors excel at executing control code. The processor’s DSP
enhancements are used within the signal-processing algorithm’s inner loops where the
compiler can best harness these specialized instructions. DSP-enhanced configurable
processors offer the performance benefits of DSPs while remaining good compiler
targets.
In summary, DSP cores no longer offer the SoC design team any performance advantages
over configurable processor architectures. All of the DSP architects’ good ideas have
become a configurable processor’s optional abilities. At the same time, configurable
processors retain their superior ability to execute control code and they remain better
compiler targets. Like Mr. Chips, DSPs led the way to a variety of performanceenhancing architectural features, but their time to serve as on-chip processors has passed.
Steven Leibson is the Technology Evangelist for Tensilica, Inc. He holds a BSEE Cum
Laude from Case Western Reserve University and worked as a design engineer and
engineering manager for leading-edge system-design companies including as HewlettPackard and Cadnetix before becoming a journalist.
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2. News
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Base Stations Sales On The Decline?
According to the In-Stat market research firm, revenue from sales of cellular base stations
will remain strong through 2008. In fact, new cellular base station revenue will reach
$53.2 million in 2006. By 2009 though, base station revenue will begin a steep decline.
In the last few years, base station prices, especially WCDMA base stations, have been cut
to a fraction of their cost of just a few years ago. According to the company, spending on
cellular base stations by cellular service providers these last few years has been untypical
– with cellular carriers spending on the deployment of new WCDMA networks as
opposed to just maintaining, upgrading and increasing the capacity of current networks.
Once deployment of most of these new networks is complete, yearly spending will drop
to more typical levels. In-Stat also found that deployment of WiMAX, Wi-Fi and other
wireless technologies will increasingly put pressure on cellular technology.
In-Stat >> http://www.in-stat.com
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3. News
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RF Architectural Planning Tool Now Available For Communication Design
Applied Wave Research (AWR) has recently announced RFA, a system-level
architectural planning tool, which provides an advanced radio frequency (RF) budget
analysis feature and “frequency heritage inspection” capabilities for next-generation
communication design. It is the ideal solution for engineers who need to quickly create
and verify the initial specifications of a radio design. By helping to find potential pitfalls
early in the design process, at the system-level design phase, the solution saves
significant design cycle time and speeds products to market. This new entry-level product
is the latest addition to the company’s Visual System Simulator (VSS) design suite.
Several new technologies introduced by RFA are RF Budget Analysis and RF Inspector.
The RF Budget Analysis feature provides the ability to make traditional RF cascaded
measurements such as gain, noise figure, and third-order intercept, inclusive of image
noise, along a communication link. RF Inspector technology is a new frequency-domain
simulation tool which helps determine the root cause or heritage of any inter-modulation
product of an RF link and includes the effects of conversions, harmonics, intermodulation, and noise. It enables users to isolate sources of unwanted interferers and to
better architect their RF systems.
Applied Wave Research >> http://www.appwave.com
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4. News
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Power-Rail Analysis Now Available For Full Custom Designs
Combining its Columbus-AMS extraction engine with electromigration (EM) and
voltage-drop components from its CoolTime dynamic voltage-drop product, Sequence
Design has created the latest in a series of new tools for power-rail analysis. SpeedviewAMS enables designers to diagnose EM and voltage-drop issues in full-custom designs.
Unlike general-purpose viewers, Speedview directly assists in finding, visualizing, and
deciding how to fix EM violations and voltage drop in a design.
Specific features of Speedview-AMS include the ability to: visualize and quickly isolate
EM and V-drop problems using tailored, geometric displays of per-net parasitic and
analysis data; find every violation, and document how to fix it, using interactively
controlled violations displays with search, annotation, and save functions; and diagnose
voltage drop with an uncluttered, parasitic-only view showing complete parasitic and
device properties. The solution can also visualize overall trends or fine details of analytic
data using interactively controlled color maps of rail polygons.
Sequence Design >> http://www.sequencedesign.com
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5. News
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Partnership Results In IP Library
A partnership between Actel and Gaisler Research has now resulted in the release of the
Gaisler Research Intellectual Property Library (GRLIB). This LEON3 processor-based
application solution is optimized for Actel's RTAX-S FPGAs and is intended to speed
time-to-market while reducing design costs and risks for system design. The Gaisler
GRLIB solution includes simulators, software development tools, either a fault-tolerant
or non-fault-tolerant version of the 32-bit LEON3 SPARC V8-compliant processor, and
two IP cores that are new for Actel customers – a Spacewire Codec and the Gaisler
Research Floating Point Unit (FPU). To complement the solution, Actel offers Core1553
and CorePCIF IP cores from its DirectCore portfolio.
The two companies have also expanded their long-standing relationship with the addition
of Gaisler to Actel's CompanionCore Partner Program. This program is designed to offer
a broad range of proven IP cores and solutions to Actel's FPGA customers. As a program
member, Gaisler will offer Actel customers IP cores, design and development boards and
development support.
Actel >> http://www.actel.com
Gaisler Research >> http://www.gaisler.com
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6. News
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Low-Cost FPGAs Offer Embedded SERDES
Lattice Semiconductor has released the industry’s first low cost FPGAs offering highspeed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS)
block. Based on the innovative LatticeECP2 low-cost architecture, the new
LatticeECP2M FPGA family has been developed on advanced 90-nm CMOS technology
utilizing 300-mm wafers. Previously, high-speed embedded SERDES serial I/O with
speeds over 3 Gbps has been available only on relatively expensive high-end FPGAs.
Priced at approximately one-third the cost of competitive SERDES-based FPGAs, the
ECP2M FPGA family effectively bridges the price/performance gap between low cost
and high-end FPGAs.
LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbit up to 5.3 Mbits,
representing up to a 400% increase over competitive low cost architectures. It offers a
comprehensive array of features that includes 375-MHz block level performance, 18-x-18
multipliers, embedded memory, pre-engineered 400-Mbps DDR2 memory interface
support, full-rate (10 Gbps+) SPI4.2 support, configuration bitstream encryption and
dual-boot configuration support. With the addition of 4 to 16 channels of 3.125-Gbps
SERDES, the LatticeECP2M FPGAs are an innovative response to the need for a low
cost SERDES capability for PCI Express and Ethernet based chip-to-chip and small form
factor backplane applications.
Lattice Semiconductor >> http://www.latticesemi.com
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7. International News
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Brazil Design Center Opens
Fairchild Semiconductor has opened a Global Power Resource design center in São
Paulo, Brazil in an effort to respond to the burgeoning high-technology markets in South
America. The South American region is projected to have a 14 percent growth rate in
2006 and nearly 10 percent in 2007. To help further this growth, Fairchild’s design center
will support its manufacturing customers in the consumer electronic and appliance,
lighting, automotive and telecom markets. The design center is staffed by electrical
engineers with extensive design expertise and a keen understanding of the application
requirements for more compact, energy-efficient, high functionality electronic
applications. These engineers are uniquely equipped to assist application engineers in the
optimization of system power in even their most demanding applications.
Fairchild Semiconductor >> http://www.fairchildsemi.com
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8. International News
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VLSI Design Initiative Launched
The Indian government has launched a VLSI education program across 32 institutes to
increase the availability of chip design talent. The $10 million, five-year program is
meant to supplement a similar program launched in the late 1990s. It will focus on
developing four streams of engineering manpower to meet growing demand for design
engineers from technology companies expanding in India. New VLSI design labs with
advanced EDA tools are also planned.
The first stream will focus on doctorate-level VLSI design and related software
development. The next will look at generating post-graduate engineers in VLSI design
and microelectronics. A third will boost the number of post-graduate engineers in
electronics and computer science with VLSI design as an elective subject. Finally, a
program will provide graduate engineers with exposure to VLSI design.
India's Ministry of Information Technology >> http://www.mit.gov.in.
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9. In-Depth Coverage Links
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Twenty (20) years ago, the first IP blocks were analog. Today, analog IP constitutes
roughly half of all IP – still a sizeable amount. How has the creation flow of analog and
AMS IP changed during the last two decades of progress? To learn more, read: “That 80's
Show or AMS IP Creation Flashback.”
Chip Design Editorial Feature >>
http://www.chipdesignmag.com/wirelesschipdesigner/july2006.html#Section_1
Imagine knowing what impact adding or removing features will have on your milestones.
Imagine finishing your design on time with less stress. Well, it's time to quit imagining
and give this new planning methodology a try on your next project! To learn more, read:
“What's Your Verification Game Plan?”
iDesign Editorial Feature >>
http://www.chipdesignmag.com/display.php?articleId=587
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10. New Books
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Practical RF Handbook
By Ian Hickman
ISBN: 0-7506-8039-3
Imprint: NEWNES
Radio Frequency (RF) is the fundamental technology behind a huge range of modern
consumer electronics and wireless communication devices. This book provides a
comprehensive and methodical guide to RF for engineers, technicians, enthusiasts and
hobbyists with an interest in the electronics behind radio frequency communications. In
Practical RF Handbook, Ian Hickman draws upon his own radio engineering background
to develop a hands-on guide to the difficulties and pitfalls of RF design with a minimum
of maths. Its broad coverage includes devices, circuits, equipment, systems, radio
propagation and external noise to fully acquaint the reader with the necessary circuit
technologies and techniques. The fourth edition brings the book fully up-to-date with new
advances in RF, including coverage of OFDM, UWB, WiFi and WiMax.
Wiley-IEEE Press >> http://www.wiley.com/
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Welcome to the World of Tomorrow - Important Trends in the Chip and Board Industry
By John Blyler, Editor-in-Chief, Chip Design and Embedded Intel Solutions magazines
The design of chip and board level electronic systems grows more complicated every
year. Current challenges include creating circuits at the atomic level (nanotechnology),
multi-core embedded PCB systems and project globalization. The complexities of
challenges facing today's engineers rival those of any other historical age. This
presentation will introduce some of the hottest electronic technologies and trends.
Insights from leading industry experts as well as luminaries from the science fiction
community will highlight trends that are just beginning to affect our lives. Specific trends
in chip-level design starts - developed from exclusive data - will also be presented.
OctoberBest'06
Hawthorn Farm, Hillsboro, OR
October 18, 2006
http://www.ema-oregon.org/OctBest6.php
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11. Happenings - Conferences
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ARM Developers’ Conference
October 3-5, 2006
Santa Clara, CA
www.arm.com/developersconference/
OctoberBest'06
October 18, 2006
Hawthorn Farm, Hillsboro, OR
http://www.ema-oregon.org/OctBest6.php
GSPx Conference and Expo
October 30 - November 2, 2006
Santa Clara, CA
www.gspx.com/index.php/
4th International System-on-Chip
November 1-2, 2006
Newport Beach, CA
www.savantcompany.com/SoC4-Fall2006/main.htm
2006 ICCAD Conference
November 5-9, 2006
San Jose, CA
www.iccad.com
Electronica
November 14-16, 2006
Munich, Germany
www.global-electronics.net
WAMICON 2006 - IEEE Wireless and Microwave Technology Conference
December 4-5, 2006
Clearwater, FL
www.ee.eng.usf.edu/WAMI/conferences/2006
Electronic Design and Solution Fair 2007 with FPGA/PLD Conference
January 25-26, 2007
Pacifico Yokohama, Kanagawa, Japan
www.edsfair.com
DesignCon 2007
January 29 – February 1
Santa Clara, California
www.designcon.com
Design Automation and Test in Europe (DATE)
April 16-20, 2007
Acropolis, Nice, France
www.date-conference.com
Read past issues of Chip Designer, FPGA Developer and Wireless Chip Designer eNewsletter:
http://www.chipdesignmag.com
WIRELESS CHIP DESIGNER e-NEWSLETTER CONTACTS
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Editor: Cheryl Ajluni
mailto:cajluni@extensionmedia.com
Editorial Director: John Blyler
mailto:jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities:
Karen Popp, mailto:kpopp@extensionmedia.com
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